CN203054827U - Data transmission system based on serial peripheral equipment interface bus - Google Patents
Data transmission system based on serial peripheral equipment interface bus Download PDFInfo
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- CN203054827U CN203054827U CN 201220477696 CN201220477696U CN203054827U CN 203054827 U CN203054827 U CN 203054827U CN 201220477696 CN201220477696 CN 201220477696 CN 201220477696 U CN201220477696 U CN 201220477696U CN 203054827 U CN203054827 U CN 203054827U
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Abstract
The utility model provides a data transmission system based on a serial peripheral equipment interface bus. The system is used for serially transmitting data between a main engine (M) and a slave (S) in two directions, wherein the main engine (M) provides a transmission clock (SCK). A method comprises the following steps that when the main engine (M) transmits the data to the slave (S), the main engine (M) utilizes a front half period and a latter half period of the transmission clock (SCK) to alternately strobe output data of the main engine (M) and send the data to the slave (S) through a first data line (MOSI (Master Out Slave In)); and when the slave (S) transmits the data to the main engine (M), the slave (S) receives the transmission clock (SCK) provided by the main engine (M) and utilizes the front half period and the latter half period of the transmission clock (SCK) to alternately strobe output data of the slave (S) and send the data to the main engine (M) through a second data line (MOSI).
Description
Technical field
The utility model relates to a kind of data transmission method and system, relates in particular to a kind of data transmission method and system based on Serial Peripheral Interface (SPI) bus.
Background technology
Serial Peripheral Interface SPI(serial peripheral interface) bus (hereinafter to be referred as " universal serial bus " or " SPI ") technology is a kind of synchronous serial interface that motorola inc releases, be used for main frame (for example CPU) and carry out full duplex, synchronous serial communication with each slave (for example various peripherals or device), with the obvious advantage aspect speed, versatility and cost is used widely.
SPI can send and receive serial data simultaneously.It only needs four lines just can finish the communication of main frame and various peripheral components, and these four lines are: transfer clock line SCKL, main frame input/slave output data line MISO, main frame output/slave input data line MOSI, the effective slave of low level are selected line SSEL.
Fig. 1 has shown the working timing figure of traditional spi bus, wherein spi bus is work in series, and normally transmitting terminal sends data at the rising edge of clock, and receiving end is in the negative edge sampled data, or transmitting terminal sends data at the negative edge of clock, and receiving end is in the rising edge sampled data.This design is very beneficial for receiving end and utilizes clock along sampled data, especially small scale integration.But, along with transmitting terminal and receiving end (especially various slave) are complicated day by day, receiving end inside has the clock zone of self usually, therefore, owing to relate to the stationary problem of the asynchronous signal between SCK clock zone and the receiving end internal clocking territory, the SPI transmission plan (for example has in the application of chip of embedded type CPU) in present application and does not directly use the edge of SCK to come data-signal is latched usually, and adopt the clock edge of SCK being sampled to judge SCK, and come sampled data at corresponding SCK clock edge.
Along with the requirement to the universal serial bus message transmission rate improves day by day, the scheme of various raising universal serial bus transfer rates has been proposed.Wherein, the scheme of traditional raising universal serial bus transfer rate, finish by improving clock frequency or increasing the data line width, yet, improve clock rate and can bring problems of Signal Integrity, increase the data line width and then can take more pin resources, bring adverse effect all can for performance and the cost of the system of universal serial bus and association thereof.In addition, improving under the prerequisite of message transmission rate, how guarantee under the situation that does not increase extra system complexity between SCK clock zone and the receiving end internal clocking territory synchronously, also be the problem that needs solution.
Therefore, how keeping the universal serial bus clock frequency constant, under the constant prerequisite of data width, improving bus transfer rate, and realizing asynchronous signal synchronous between SCK clock zone and the receiving end internal clocking territory, is present problem demanding prompt solution.
The disclosed information of background technology part should not regarded the prompting or any type of hint that this information are constituted correlation technique well known by persons skilled in the art as just in order to strengthen the understanding to general background of the present utility model.
The utility model content
The purpose of this utility model is, the universal serial bus clock frequency is constant keeping, under the constant prerequisite of data width, improve bus transfer rate, avoided improving the problems of Signal Integrity that clock frequency brings or increased more pin resource problems that take that the data line width brings.
Another purpose of the present utility model is, on the basis of improving bus transfer rate, guarantees asynchronous signal synchronous between SCK clock zone and the receiving end internal clocking territory.
For reaching this purpose, according to one side of the present utility model, a kind of data transmission method based on Serial Peripheral Interface (SPI) bus has been proposed, this method is bidirectional linked list transmission data between main frame (M) and slave (S), wherein said main frame (M) provides transfer clock (SCK), it is characterized in that, this method comprises: when by described main frame (M) during to described slave (S) transmission data, described main frame (M) utilizes the output data that preceding semiperiod of described transfer clock (SCK) and later half cycle replace the described main frame of gating (M) and is sent to described slave (S) by first data line (MOSI); And when transmitting data by described slave (S) to described main frame (M), the described transfer clock (SCK) that is provided by described main frame (M) is provided described slave (S), and utilizes the output data that preceding semiperiod of described transfer clock (SCK) and later half cycle replace the described slave of gating (S) and be sent to described main frame (M) by second data line (MISO).Preceding semiperiod and the later half cycle of the transfer clock (SCK) of this method by utilizing universal serial bus are transmitted the transfer rate that data improve universal serial bus simultaneously.
Preferably, when transmitting data by described main frame (M) to described slave (S), described slave (S) judges whether the preceding semiperiod of described transfer clock (SCK) or later half cycle arrive, if, it then is the current data on first data line (MOSI) with the Data Update of the input register of slave, if not, the data that then keep the input register of slave.That is to say, by slave preceding semiperiod and the later half cycle of transfer clock SCK are judged respectively, thereby the asynchronous signal between realization SCK clock zone and the receiving end internal clocking territory is synchronous.
Preferably, judging whether preceding semiperiod of described transfer clock (SCK) or later half cycle arrive comprises: judge that whether the current sampled level of described transfer clock (SCK) was with last time sampled level was identical, if identical, then the current data on first data line (MOSI) is latched into the input register of slave (S); If inequality, then the data with the input register of slave (S) shift out, and the current data on first data line (MOSI) are latched into the input register of slave (S).
Preferably, when transmitting data by described main frame (M) to described slave (S), the two-way output data in the long numeric data of the output register in the preceding semiperiod of described transfer clock (SCK) and the difference described main frame of gating of later half cycle (M); And when transmitting data by described slave (S) to described main frame (M), the two-way output data in the long numeric data of the output register of the preceding semiperiod of described transfer clock (SCK) and the difference described slave of gating of later half cycle (S).
Preferably, described transfer clock (SCK) is by its rising edge and negative edge, and perhaps its high level and low level replace the output data of the described main frame of gating or described slave.
According on the other hand of the present utility model, a kind of data transmission system based on Serial Peripheral Interface (SPI) bus has been proposed, this system is bidirectional linked list transmission data between main frame (M) and slave (S), it is characterized in that this system comprises:
Main frame (M); This main frame (M) provides transfer clock (SCK);
Slave (S);
First data line (MOSI), the data that described main frame (M) is sent are sent to described slave (S);
Second data line (MISO), the data that described slave (S) is sent are sent to described main frame (M);
Clock transfer line (SCKL), the described transfer clock (SCK) that described main frame (M) is provided transfers to described slave (S); Wherein
When by described main frame (M) during to described slave (S) transmission data, described main frame (M) utilizes the output data that preceding semiperiod of described transfer clock (SCK) and later half cycle replace the described main frame of gating (M) and is sent to described slave (S) by described first data line (MOSI);
When transmitting data by described slave (S) to described main frame (M), the described transfer clock (SCK) that is provided by described main frame (M) is provided described slave (S), and utilizes the output data that preceding semiperiod of described transfer clock (SCK) and later half cycle replace the described slave of gating (S) and be sent to described main frame (M) by described second data line (MISO).
Preferably, described main frame (M) also comprises first gate (MUX1), and two input ends of this first gate (MUX1) receive the two-way output data of described main frame respectively, and the output terminal of this first gate connects described first data line (MOSI); Wherein, when by described main frame (M) during to described slave (S) transmission data, the preceding semiperiod of described transfer clock (SCK) and later half cycle replace the data of two input ends of described first gate of gating (MUX1) to the output terminal of described first gate.
Preferably, described slave (S) also comprises second gate (MUX2), two input ends of this second gate (MUX2) receive the two-way output data of described slave (S) respectively, and the output terminal of this second gate connects described second data line (MISO); Wherein, when by described slave (S) during to described main frame (M) transmission data, the preceding semiperiod of described transfer clock (SCK) and later half cycle replace the data of two input ends of described second gate of gating (MUX2) to the output terminal of described second gate.
Preferably, when transmitting data by described main frame (M) to described slave (S), described slave (S) judges whether the preceding semiperiod of described transfer clock (SCK) or later half cycle arrive, if, it then is the current data on first data line (MOSI) with the Data Update of the input register of slave, if not, the data that then keep the input register of slave.
Preferably, judging whether preceding semiperiod of described transfer clock (SCK) or later half cycle arrive comprises: judge that whether the current sampled level of described transfer clock (SCK) was with last time sampled level was identical, if identical, then the current data on first data line (MOSI) is latched into the input register of described slave (S); If inequality, then the input register data with described slave (S) shift out, and the current data on first data line (MOSI) are latched into the input register of described slave (S).
Preferably, described main frame (M) and described slave (S) comprise a plurality of output registers respectively, when transmitting data by described main frame (M) to described slave (S), the two-way output data in the long numeric data of the output register of the preceding semiperiod of described transfer clock (SCK) and the difference described main frame of gating of later half cycle (M); And when transmitting data by described slave (S) to described main frame (M), the two-way output data in the long numeric data of the output register of the preceding semiperiod of described transfer clock (SCK) and the difference described slave of gating of later half cycle (S).
Preferably, described transfer clock (SCK) is by its rising edge and negative edge, and perhaps its high level and low level replace the output data of the described main frame of gating or described slave.
The utility model is doubled the data transfer rate of universal serial bus under the prerequisite of the variation that does not bring board level system design, also can guarantee synchronous between receiving end internal clocking territory and the transfer clock territory.
Other feature and advantage according to method and apparatus of the present disclosure will present at the following accompanying drawing of incorporating this paper into and in hereinafter to detailed description of the present utility model or be illustrated, accompanying drawing and detailed description of the present utility model be used for explained certain principles of the present utility model jointly.
Description of drawings
Should be understood that accompanying drawing is not necessarily to scale, it presents is reduced representation in a way to each feature of describing the utility model ultimate principle.The specific design feature of the utility model disclosed herein comprises for example specific size, direction, position and shape, is partly determined by application and the environment for use of concrete appointment.
In the accompanying drawings, identical Reference numeral refers to the utility model part identical or of equal value in institute's drawings attached.
Fig. 1 has shown the working timing figure of traditional spi bus;
Fig. 2 is the synoptic diagram according to a kind of data transmission method based on the Serial Peripheral Interface spi bus of first embodiment of the present utility model;
Fig. 3 is the synoptic diagram according to a kind of data transmission method based on the Serial Peripheral Interface spi bus of second embodiment of the present utility model;
Fig. 4 is the synoptic diagram according to a kind of data transmission system based on the Serial Peripheral Interface spi bus of the 4th embodiment of the present utility model;
Fig. 5 is the synoptic diagram according to a kind of data transmission system based on the Serial Peripheral Interface spi bus of the 5th embodiment of the present utility model;
Fig. 6 is the synoptic diagram according to a kind of data transmission system based on the Serial Peripheral Interface spi bus of the 6th embodiment of the present utility model;
Fig. 7 is the synoptic diagram according to a kind of data transmission system based on the Serial Peripheral Interface spi bus of the 7th embodiment of the present utility model;
Fig. 8 is the working timing figure according to a kind of data transmission system based on the Serial Peripheral Interface spi bus of embodiment of the present utility model.
Embodiment
Below will be in detail with reference to each embodiment of the present utility model, its example is presented at accompanying drawing and hereinafter in the description.Although described the utility model in conjunction with exemplary embodiment, should be appreciated that this instructions is not intended to the utility model is limited to these exemplary embodiments.On the contrary, the utility model not only is intended to cover these exemplary embodiments, and covering is included in essence of the present utility model and the various substitutes in the scope, modification, equivalent and other embodiment that is limited by appended claims.
One side of the present utility model, a kind of data transmission method based on the Serial Peripheral Interface spi bus has been proposed, this method is utilized preceding semiperiod of transfer clock (SCK) and the later half cycle of universal serial bus, transmits data simultaneously, to improve the data transfer rate of universal serial bus.Below by each embodiment, specify according to method preferred implementation of the present utility model.
Fig. 2 is the synoptic diagram according to a kind of data transmission method based on the Serial Peripheral Interface spi bus of first embodiment of the present utility model, this method is bidirectional linked list transmission data between main frame M and slave S, wherein said main frame M provides transfer clock SCK, and the method for this embodiment comprises:
When by described main frame M during to described slave S transmission data, described main frame M utilizes output data that preceding semiperiod of described transfer clock SCK and later half cycle replace the described main frame M of gating and is sent to described slave S by the first data line MOSI; And
When transmitting data by described slave S to described main frame M, the described transfer clock SCK that is provided by described main frame M is provided for described slave S, and utilizes output data that preceding semiperiod of described transfer clock SCK and later half cycle replace the described slave S of gating and be sent to described main frame M by the second data line MISO.
With the traditional rising edge that only utilizes transfer clock SCK (or negative edge) transmission data, namely in a clock period, only transmit scheme (as shown in Figure 1) difference of the data of a unit data line width, in this embodiment of the present utility model, the preceding semiperiod of the transfer clock that utilizes and later half cycle are as the gating signal of the output data of transmitting terminal (main frame or slave), and when the semiperiod arrives before the transfer clock, gating and transmission of one line output data, when the later half cycle of transfer clock arrives, gating also transmits another road output data, thereby the data of two unit data line widths of transmission in a clock period, the transfer rate with universal serial bus is doubled thus.Here " unit data line width " but refer to first data line and the data bits of second data line parallel transmission separately, for example 1,2,4 and more than.
Notice, for brevity, preceding semiperiod by transfer clock SCK and later half cycle are being described when the output data are carried out gating, embodiment shown in Figure 2 adopts the mode of " edge gating " to describe transfer clock SCK, sequential relationship between the first data line MOSI and the second data line MISO, that is to say, in the sequential chart of embodiment shown in Figure 2, rising edge and negative edge by transfer clock SCK carry out gating to the output data, yet, in another distortion, also can carry out gating to the output data by high level and the low level of transfer clock SCK.That is to say that preferably, transfer clock SCK can pass through its rising edge and negative edge, perhaps high level and low level replace the output data of gating main frame or slave.Above dual mode all belongs to by the preceding semiperiod of transfer clock SCK and later half cycle the output data is carried out gating.
When main frame and low from motor speed and complexity, especially slave does not have internal clocking territory and SCK clock zone to carry out under the application scenario of synchronous requirement, and the method for embodiment shown in Figure 2 can satisfy the synchronous serial data transmission between main frame and the slave fully.Yet internal clocking territory and the SCK clock zone to slave carries out synchronously if desired, can further adopt the method for second embodiment as shown in Figure 3 to realize.
Fig. 3 has shown the synoptic diagram according to a kind of data transmission method based on the Serial Peripheral Interface spi bus of second embodiment of the present utility model.In this second embodiment, on the basis of the method for first embodiment shown in Figure 2, when transmitting data by described main frame M to described slave S, described slave S judges whether the preceding semiperiod of described transfer clock SCK or later half cycle arrive, if, then be the current data on the first data line MOSI with the Data Update of the input register of slave, if not, then keep the data of the input register of slave.
The purpose of this second embodiment is when guaranteeing that slave receives the data that main frame sends, and can realize transfer clock SCK(and the data that receive) with slave internal clocking territory synchronously.It should be noted, when main frame receives the data of slave transmission, because transfer clock SCK itself is provided by main frame, can realize naturally that therefore main frame need not the edge of transfer clock SCK is judged synchronously.
Judge that the method whether preceding semiperiod of described transfer clock SCK or later half cycle arrive has a lot, for example can be by judging that whether the current sampled level of described transfer clock SCK was with last time sampled level was identical, if identical, then the current data on the first data line MOSI is latched into the input register of slave S; If inequality, then the data with the input register of slave S shift out, and the current data on the first data line MOSI are latched into the input register of slave S.
In preferred the 3rd embodiment, on the basis of first or second embodiment, when transmitting data by described main frame M to described slave S, the two-way output data in the long numeric data of the output register among the preceding semiperiod of described transfer clock SCK and the described main frame M of difference gating of later half cycle; And when transmitting data by described slave S to described main frame M, the two-way output data in the long numeric data of the output register of the preceding semiperiod of described transfer clock SCK and the described slave S of difference gating of later half cycle.
Preferably, when main frame and a plurality of slave carry out data transmission, utilize slave to select signal SSEL that described a plurality of slaves are selected.
On the other hand of the present utility model, a kind of data transmission system based on the Serial Peripheral Interface spi bus has been proposed, this system utilizes preceding semiperiod of transfer clock SCK and the later half cycle of universal serial bus, transmits data simultaneously, to improve the data transfer rate of universal serial bus.Below by each embodiment, specify the preferred implementation according to system of the present utility model.
Fig. 4 is a kind of data transmission system based on the Serial Peripheral Interface spi bus according to the 4th embodiment of the present utility model, and this system is bidirectional linked list transmission data between main frame M and slave S, it is characterized in that this system comprises:
Main frame M; This main frame M provide transfer clock SCK;
Slave S;
The first data line MOSI, the data that described main frame M is sent are sent to described slave S;
The second data line MISO, the data that described slave S is sent are sent to described main frame M;
Clock transfer line SCKL, the described transfer clock SCK that described main frame M is provided transfers to described slave S; Wherein
When by described main frame M during to described slave S transmission data, described main frame M utilizes output data that preceding semiperiod of described transfer clock SCK and later half cycle replace the described main frame M of gating and is sent to described slave S by the described first data line MOSI;
When transmitting data by described slave S to described main frame M, the described transfer clock SCK that is provided by described main frame M is provided for described slave S, and utilizes output data that preceding semiperiod of described transfer clock SCK and later half cycle replace the described slave S of gating and be sent to described main frame M by the described second data line MISO.
Preferably, transfer clock SCK can pass through its rising edge and negative edge, and perhaps high level and low level replace the output data of gating main frame or slave.
Preferably, the gating of output data can be realized by gate.In the 5th embodiment shown in Figure 5, described main frame M also preferably includes the first gate MUX1, two input ends of this first gate MUX1 receive the two-way output data of described main frame respectively, and the output terminal of this first gate connects the described first data line MOSI; Wherein, when by described main frame M during to described slave S transmission data, the preceding semiperiod of described transfer clock SCK and later half cycle replace the data of two input ends of the described first gate MUX1 of gating to the output terminal of described first gate.
Similarly, described slave S also preferably includes the second gate MUX2, and two input ends of this second gate MUX2 receive the two-way output data of described slave S respectively, and the output terminal of this second gate connects the described second data line MISO; Wherein, when by described slave S during to described main frame M transmission data, the preceding semiperiod of described transfer clock SCK and later half cycle replace the data of two input ends of the described second gate MUX2 of gating to the output terminal of described second gate.
The 6th embodiment shown in Figure 6 is applied to and need internal clocking territory and the SCK clock zone of slave be carried out under the synchronous application scenario, wherein preferably, when transmitting data by described main frame M to described slave S, described slave S judges whether the preceding semiperiod of described transfer clock SCK or later half cycle arrive, if, then be the current data on the first data line MOSI with the Data Update of the input register of slave, if not, then keep the data of the input register of slave.
Judge that the method whether preceding semiperiod of described transfer clock SCK or later half cycle arrive is a lot, for example can judge that whether the current sampled level of described transfer clock SCK was with last time sampled level was identical, if identical, then the current data on the first data line MOSI is latched into the input register of described slave S; If inequality, then the input register data with described slave S shift out, and the current data on the first data line MOSI are latched into the input register of described slave S.
In the 7th embodiment shown in Figure 7, described main frame M and described slave S preferably include a plurality of output registers respectively, when transmitting data by described main frame M to described slave S, the rising edge of described transfer clock SCK and negative edge be two outputs of a plurality of output registers of the described main frame M of gating respectively; And when transmitting data by described slave S to described main frame M, the rising edge of described transfer clock SCK and negative edge be two outputs of a plurality of output registers of the described slave S of gating respectively.In addition alternatively, when transmitting data by described main frame M to described slave S, the two-way output data in the long numeric data of the output register of the preceding semiperiod of described transfer clock SCK and the described main frame M of difference gating of later half cycle; And when transmitting data by described slave S to described main frame M, the two-way output data in the long numeric data of the output register of the preceding semiperiod of described transfer clock SCK and the described slave S of difference gating of later half cycle.
In general SPI implementation, usually comprise one or more groups shift register in main frame or the slave, the input end of shift register (input register) receives the data that received by main frame or slave, the data displacement output that its output terminal of while (output register) will send.Therefore, output register both can be one group of output register in the shift register among the 3rd embodiment, also can be the output register in many group shift registers.For example, when comprising one group of degree of depth in main frame or the slave and be the shift register of M position, transfer clock SCK can replace the two-way output data in this M bit data of gating, and every road comprises the N bit data, and wherein N is corresponding with the width of first and second data lines.When the shift register of group more than comprising in main frame or the slave, transfer clock SCK can replace the wherein two-way output data of two groups of shift registers of gating.Yet, the utility model is intended to utilize the preceding semiperiod of transfer clock and later half cycle to replace gating and transmission output data, therefore be not limited to the SPI implementation of shift register as data input and output mechanism, the utility model is applicable to the applied environment of realizing data input and output mechanism in other modes outside the shift register too.
Preferably, when main frame and a plurality of slave carry out data transmission, utilize slave to select signal (SSEL) that described a plurality of slaves are selected.
Fig. 8 has shown the working timing figure according to a kind of data transmission system based on the Serial Peripheral Interface spi bus of embodiment of the present utility model.As can be seen from this figure, the utility model utilizes the preceding semiperiod of transfer clock SCK and later half cycle to transmit signal simultaneously, and the universal serial bus data line is doubled.
Above in order to describe and purpose of description, presented certain exemplary embodiments of the present utility model.These exemplary embodiments and non exhaustive, or the utility model is restricted to disclosed precise forms significantly, all are feasible according to many modifications and variations of above-mentioned teaching.Selecting and describing these exemplary embodiments is in order to explain certain principles of the present utility model and practical application thereof, thereby those skilled in the art are made and uses each exemplary embodiment of the present utility model, and various substitute and modification.In fact scope of the present utility model is limited by appending claims and equivalent thereof.
Claims (7)
1. data transmission system based on serial peripheral equipment interface bus, this system be bidirectional linked list transmission data between main frame (M) and slave (S), it is characterized in that this system comprises:
Main frame (M); This main frame (M) provides transfer clock (SCK);
Slave (S);
First data line (MOSI), the data that described main frame (M) is sent are sent to described slave (S);
Second data line (MISO), the data that described slave (S) is sent are sent to described main frame (M);
Clock transfer line (SCKL), the described transfer clock (SCK) that described main frame (M) is provided transfers to described slave (S); Wherein
When by described main frame (M) during to described slave (S) transmission data, described main frame (M) utilizes the output data that preceding semiperiod of described transfer clock (SCK) and later half cycle replace the described main frame of gating (M) and is sent to described slave (S) by described first data line (MOSI);
When transmitting data by described slave (S) to described main frame (M), the described transfer clock (SCK) that is provided by described main frame (M) is provided described slave (S), and utilizes the output data that preceding semiperiod of described transfer clock (SCK) and later half cycle replace the described slave of gating (S) and be sent to described main frame (M) by described second data line (MISO).
2. data transmission system according to claim 1, it is characterized in that, described main frame (M) also comprises first gate (MUX1), two input ends of this first gate (MUX1) receive the two-way output data of described main frame respectively, and the output terminal of this first gate connects described first data line (MOSI);
Wherein, when by described main frame (M) during to described slave (S) transmission data, the preceding semiperiod of described transfer clock (SCK) and later half cycle replace the data of two input ends of described first gate of gating (MUX1) to the output terminal of described first gate.
3. data transmission system according to claim 1, it is characterized in that, described slave (S) also comprises second gate (MUX2), two input ends of this second gate (MUX2) receive the two-way output data of described slave (S) respectively, and the output terminal of this second gate connects described second data line (MISO);
Wherein, when by described slave (S) during to described main frame (M) transmission data, the preceding semiperiod of described transfer clock (SCK) and later half cycle replace the data of two input ends of described second gate of gating (MUX2) to the output terminal of described second gate.
4. data transmission system according to claim 1, it is characterized in that, when transmitting data by described main frame (M) to described slave (S), described slave (S) judges whether the preceding semiperiod of described transfer clock (SCK) or later half cycle arrive, if, then be the current data on first data line (MOSI) with the Data Update of the input register of slave, if not, then keep the data of the input register of slave.
5. data transmission system according to claim 4, it is characterized in that, judging whether preceding semiperiod of described transfer clock (SCK) or later half cycle arrive comprises: judge that whether the current sampled level of described transfer clock (SCK) was with last time sampled level was identical, if identical, then the current data on first data line (MOSI) is latched into the input register of described slave (S); If inequality, then the input register data with described slave (S) shift out, and the current data on first data line (MOSI) are latched into the input register of described slave (S).
6. data transmission system according to claim 5, it is characterized in that, described main frame (M) and described slave (S) comprise a plurality of output registers respectively, when transmitting data by described main frame (M) to described slave (S), the two-way output data in the long numeric data of the output register of the preceding semiperiod of described transfer clock (SCK) and the difference described main frame of gating of later half cycle (M); And
When transmitting data by described slave (S) to described main frame (M), the two-way output data in the long numeric data of the output register of the preceding semiperiod of described transfer clock (SCK) and the difference described slave of gating of later half cycle (S).
7. according to any described data transmission system among the claim 1-6, it is characterized in that described transfer clock (SCK) is by its rising edge and negative edge, perhaps its high level and low level replace the output data of the described main frame of gating or described slave.
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| CN 201220477696 CN203054827U (en) | 2012-09-18 | 2012-09-18 | Data transmission system based on serial peripheral equipment interface bus |
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Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103678209A (en) * | 2012-09-18 | 2014-03-26 | 格科微电子（上海）有限公司 | Method and system for transmitting data on basis of serial peripheral interface buses |
| CN105512070A (en) * | 2015-12-02 | 2016-04-20 | 中国电子科技集团公司第四十一研究所 | Control system based on serial bus |
| CN107086808A (en) * | 2017-05-02 | 2017-08-22 | 北京群菱能源科技有限公司 | A kind of photovoltaic DC-to-AC converter and its control method |
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2012
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Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103678209A (en) * | 2012-09-18 | 2014-03-26 | 格科微电子（上海）有限公司 | Method and system for transmitting data on basis of serial peripheral interface buses |
| CN103678209B (en) * | 2012-09-18 | 2017-03-15 | 格科微电子（上海）有限公司 | Data transmission method and system based on serial peripheral equipment interface bus |
| CN105512070A (en) * | 2015-12-02 | 2016-04-20 | 中国电子科技集团公司第四十一研究所 | Control system based on serial bus |
| CN105512070B (en) * | 2015-12-02 | 2018-07-06 | 中国电子科技集团公司第四十一研究所 | A kind of control system based on universal serial bus |
| CN107086808A (en) * | 2017-05-02 | 2017-08-22 | 北京群菱能源科技有限公司 | A kind of photovoltaic DC-to-AC converter and its control method |
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