CN202872805U - A synchronizer - Google Patents
A synchronizer Download PDFInfo
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- CN202872805U CN202872805U CN201220456401.4U CN201220456401U CN202872805U CN 202872805 U CN202872805 U CN 202872805U CN 201220456401 U CN201220456401 U CN 201220456401U CN 202872805 U CN202872805 U CN 202872805U
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Abstract
The utility model provides a synchronizer which relates to the communication field and which resolves a problem of lack of AFDX time synchronization mechanism. The synchronizer comprises a processor and an input port which is connected with the processor. The input port is used for receiving a serial time code with IRIG-B format and transmitting the time code to the processor. The processor receives the time code transmitted from the input port and acquires a time signal by subdividing the time code on the basis of the time code. The technical scheme provided by the utility model is suitable for a AFDX and achieves time synchronization based on the IRIG-B.
Description
Technical field
The utility model relates to the communications field, relates in particular to a kind of synchronizer.
Background technology
Avionics full duplex real-time ethernet (Avionics Full Duplex Switched Ethernet, AFDX) be Airbus SAS according to the ARINC664 standard, the technology that realizes for the aircraft data network (Aircraft Data Networks) of determining.Be widely used at present interconnecting electronic system in the aviation aircraft is such as engine, flight-control component, cruise system etc.Up to now, AFDX has used at A380, in A400M and the Boeing B787 project.And based on the equipment of this agreement also increasing, so be sought after very perfect testing scheme this kind equipment is tested.For transmission delay between the terminal equipment, the transmission delay that also is network environment is a very important index in test.
The means of time synchronized mainly are to use local PC initialized in the prior art, and total system is unified relative time, and the relative error of communicating by letter between the precision of this method of synchronization and the multiple devices all is unacceptable, and is relatively poor with yupin effect.
The utility model content
The utility model provides a kind of synchronizer, has solved the problem that lacks the AFDX Time Synchronization Mechanism.
A kind of synchronizer comprises processor and input port, and this input port is connected with described processor:
Described input port, the serial timing code for receiving target range instrument group (IRIG)-B form transfers to described processor with described timing code;
Described processor is received from the timing code of described input port transmission, take this timing code as benchmark, described timing code is segmented obtain time signal.
Preferably, described processor comprises:
Signal generating unit is for generation of a narrow pulse signal;
Timer is used for when producing described narrow pulse signal, carries out timing according to the clock of a minor cycle frequency, obtains time signal.
Preferably, described narrow pulse signal length is 100ns., the clock of described minor cycle frequency is specially the clock of 100MHz frequency.
Preferably, described timer is the timer of accuracy of timekeeping 10ns.
The utility model provides a kind of synchronizer, comprise processor and input port, this input port is connected with described processor, described input port, be used for receiving the serial timing code of IRIG-B form, described timing code is transferred to described processor, described processor is received from the timing code of described input port transmission, take this timing code as benchmark, described timing code segmented obtain time signal, realize the time synchronized based on IRIG-B, solved the problem that lacks the AFDX Time Synchronization Mechanism.
Description of drawings
Fig. 1 is the flow chart of a kind of method for synchronizing time of providing of embodiment one of the present utility model;
Fig. 2 is the structural representation of a kind of synchronizer of providing of embodiment two of the present utility model;
Fig. 3 is the method for synchronizing time that provides of embodiment of the present utility model and the realization schematic diagram of synchronizer;
Fig. 4 is the transmission delay schematic diagram.
Embodiment
The means of time synchronized mainly are in the prior art: one, use local PC initialized, total system is unified relative time; Two, directly use this a kind of traditional Time synchronization technique of IRIG-B.
Although directly use IRIG-B also can carry out synchronous, synchronous precision, and the relative error of communicating by letter between the multiple devices all is unacceptable, relatively poor with yupin effect.
In order to address the above problem, embodiment of the present utility model provides a kind of method for synchronizing time.Hereinafter in connection with accompanying drawing embodiment of the present utility model is elaborated.Need to prove, in the situation that do not conflict, the embodiment among the application and the feature among the embodiment be combination in any mutually.
At first by reference to the accompanying drawings, embodiment one of the present utility model is described.
The utility model embodiment provides a kind of method for synchronizing time, uses flow process that the method finishes the transmitting-receiving time synchronized as shown in Figure 1, comprising:
Suppose that two end node A in the network send to B, when if end node A has identical initial time t0 with end node B, record A sends the time t1 of this Frame when end node A sends Frame f1 to end node B so, the time t2 of these frame data received in record when B receives this Frame of data f1, because t1 and t2 are based at the same time starting point t0.So just can calculate the transmission delay Δ t2=t2-t1 of Frame in passage.Otherwise, if do not have t0 constantly as starting point, also be that side a and b does not have unified start time, just have no idea to calculate Δ t2.
To sum up, the key of calculating transmission delay is t0 constantly because the signal of the IRIG-B form that receives in different areas all is identical, therefore among the utility model embodiment, with the signal of IRIG-B form as synchronizing signal.
In this step, be specially the timing code of the form of date Hour Minute Second by the serial timing code of IRIG-B reception.
In this step, at first per second produces a 100ns narrow pulse signal, is called the 1pps signal.When the narrow pulse signal of 100ns produced, just the clock by 100MHz began counting at every turn, and the cycle of 100MHz clock just in time is 10ns.Also namely be again that precision is the time signal of 10ns with time subdivision after receiving the timing code of IRIG-B, that is to say that the markers least unit is 10ns.Just can reach 10ns for the precision of measuring the network environment transmission delay this moment so.Certainly, can set the clock count cycle according to current requirement to precision, the clock cycle is shorter, and time scale reading is less, and certainty of measurement is also just higher.
Below in conjunction with accompanying drawing, embodiment two of the present utility model is described.
The utility model embodiment provides a kind of synchronizer, and its structure comprises processor 201 and input port 202 as shown in Figure 2, and this input port 202 is connected with described processor 201:
Described input port 202, the serial timing code for receiving the IRIG-B form transfers to described processor 201 with described timing code;
Described processor 201 is received from the timing code of described input port transmission, take this timing code as benchmark, described timing code is segmented obtain time signal.
Preferably, described processor 201 comprises:
Preferably, described narrow pulse signal length is 100ns., the clock of described minor cycle frequency is specially the clock of 100MHz frequency.
Preferably, described timer 2012 is the timer of accuracy of timekeeping 10ns.
Embodiment of the present utility model provides a kind of method for synchronizing time and synchronizer, the sending and receiving end receives the serial timing code of IRIG-B form, described timing code is segmented, obtain time signal, transmitting-receiving two-end receives the timing code of IRIG-B form, realize the time synchronized based on IRIG-B, solved the problem that lacks the AFDX Time Synchronization Mechanism.Embodiment of the present utility model adopts the time synchronized based on IRIG-B, after reaching the time synchronized success, just can add absolute time mark to the packet that sends, and also the packet of receiving can be added absolute time mark; The markers of the packet of the packet that sends and reception is asked poor, just can obtain transmission delay, the while can also be calculated the shake in the interval calculation packet time interval between the packet of receiving.
Because the IRIG signal that receives in different areas is identical, just can obtain unified start time by IRIG-B.Thereby can calculate transmission delay.
The all or part of step that one of ordinary skill in the art will appreciate that above-described embodiment can realize with the computer program flow process, described computer program can be stored in the computer-readable recording medium, described computer program (such as system, unit, device etc.) on corresponding hardware platform is carried out, when carrying out, comprise step of embodiment of the method one or a combination set of.
Alternatively, all or part of step of above-described embodiment also can realize with integrated circuit, and these steps can be made into respectively one by one integrated circuit modules, perhaps a plurality of modules in them or step is made into the single integrated circuit module and realizes.Like this, the utility model is not restricted to any specific hardware and software combination.
Each device/functional module/functional unit in above-described embodiment can adopt general calculation element to realize, they can concentrate on the single calculation element, also can be distributed on the network that a plurality of calculation elements form.
Each device/functional module/functional unit in above-described embodiment is realized with the form of software function module and during as independently production marketing or use, can be stored in the computer read/write memory medium.The above-mentioned computer read/write memory medium of mentioning can be read-only memory, disk or CD etc.
Anyly be familiar with those skilled in the art in the technical scope that the utility model discloses, can expect easily changing or replacing, all should be encompassed within the protection range of the present utility model.Therefore, protection range of the present utility model should be as the criterion with the described protection range of claim.
Claims (4)
1. a synchronizer is characterized in that, comprises processor and input port, and this input port is connected with described processor:
Described input port, the serial timing code for receiving target range instrument group (IRIG)-B form transfers to described processor with described timing code;
Described processor is received from the timing code of described input port transmission, take this timing code as benchmark, described timing code is segmented obtain time signal.
2. synchronizer according to claim 1 is characterized in that, described processor comprises:
Signal generating unit is for generation of a narrow pulse signal;
Timer is used for when producing described narrow pulse signal, carries out timing according to the clock of a minor cycle frequency, obtains time signal.
3. synchronizer according to claim 2 is characterized in that, described narrow pulse signal length is 100ns, and the clock of described minor cycle frequency is specially the clock of 100MHz frequency.
4. the synchronizer of stating according to claim 3 is characterized in that, described timer is the timer of accuracy of timekeeping 10ns.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201220456401.4U CN202872805U (en) | 2012-09-07 | 2012-09-07 | A synchronizer |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201220456401.4U CN202872805U (en) | 2012-09-07 | 2012-09-07 | A synchronizer |
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| CN202872805U true CN202872805U (en) | 2013-04-10 |
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| CN201220456401.4U Expired - Lifetime CN202872805U (en) | 2012-09-07 | 2012-09-07 | A synchronizer |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN104570824A (en) * | 2013-10-15 | 2015-04-29 | Ls产电株式会社 | Event input module |
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2012
- 2012-09-07 CN CN201220456401.4U patent/CN202872805U/en not_active Expired - Lifetime
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN104570824A (en) * | 2013-10-15 | 2015-04-29 | Ls产电株式会社 | Event input module |
| US9864358B2 (en) | 2013-10-15 | 2018-01-09 | Lsis Co., Ltd. | Event input module |
| CN104570824B (en) * | 2013-10-15 | 2018-05-29 | Ls产电株式会社 | Event input module |
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| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant | ||
| CX01 | Expiry of patent term | ||
| CX01 | Expiry of patent term |
Granted publication date: 20130410 |