[go: up one dir, main page]
More Web Proxy on the site http://driver.im/

CN202394956U - Semiconductor encapsulation structure - Google Patents

Semiconductor encapsulation structure Download PDF

Info

Publication number
CN202394956U
CN202394956U CN2011204980871U CN201120498087U CN202394956U CN 202394956 U CN202394956 U CN 202394956U CN 2011204980871 U CN2011204980871 U CN 2011204980871U CN 201120498087 U CN201120498087 U CN 201120498087U CN 202394956 U CN202394956 U CN 202394956U
Authority
CN
China
Prior art keywords
chip
sided
several
layer
double
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
CN2011204980871U
Other languages
Chinese (zh)
Inventor
方仁广
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Advanced Semiconductor Engineering Shanghai Inc
Original Assignee
Advanced Semiconductor Engineering Shanghai Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Advanced Semiconductor Engineering Shanghai Inc filed Critical Advanced Semiconductor Engineering Shanghai Inc
Priority to CN2011204980871U priority Critical patent/CN202394956U/en
Application granted granted Critical
Publication of CN202394956U publication Critical patent/CN202394956U/en
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/0401—Bonding areas specifically adapted for bump connectors, e.g. under bump metallisation [UBM]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/04042—Bonding areas specifically adapted for wire connectors, e.g. wirebond pads
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/04105—Bonding areas formed on an encapsulation of the semiconductor or solid-state body, e.g. bonding areas on chip-scale packages
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/12105—Bump connectors formed on an encapsulation of the semiconductor or solid-state body, e.g. bumps on chip-scale packages
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16135—Disposition the bump connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/16145—Disposition the bump connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/16227—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation the bump connector connecting to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16245—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H01L2224/20—Structure, shape, material or disposition of high density interconnect preforms
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H01L2224/23—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process
    • H01L2224/25—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process of a plurality of high density interconnect connectors
    • H01L2224/251—Disposition
    • H01L2224/2518—Disposition being disposed on at least two different sides of the body, e.g. dual array
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32135—Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/32145—Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32245—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73201—Location after the connecting process on the same surface
    • H01L2224/73207—Bump and wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73265—Layer and wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
    • H01L2924/191—Disposition
    • H01L2924/19101—Disposition of discrete passive components
    • H01L2924/19105—Disposition of discrete passive components in a side-by-side arrangement on a common die mounting substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
    • H01L2924/191—Disposition
    • H01L2924/19101—Disposition of discrete passive components
    • H01L2924/19107—Disposition of discrete passive components off-chip wires

Landscapes

  • Semiconductor Integrated Circuits (AREA)

Abstract

The utility model discloses a semiconductor encapsulation structure comprising a carrier plate, at least one double-faced circuit encapsulation unit and at least one chip. The double-faced circuit encapsulation unit is located on the carrier plate and is provided with a double-faced chip, an insulating region, a first wiring layer and a second wiring layer. The double-faced circuit encapsulation unit is provided with a double-faced circuit and is capable of being used for overlapping and combining the chip, thereby facilitating to increase the circuit layers of a single chip, reducing the number of stacked chips necessary for the integral encapsulation structure, improving the integral circuit configuration density of the encapsulation structure and thinning and shortening the volume of the whole encapsulation structure.

Description

Semiconductor packaging structure
Technical field
The utility model relates to a kind of semiconductor packaging structure, particularly has the double-sided circuit layout relevant for a kind of utilization and the double-sided circuit encapsulation unit of the layer that reroutes comes the semiconductor packaging structure of another chip of stacked combination.
Background technology
Now; The semiconductor packages industry is in order to satisfy the demand of various high-density packages; Develop the packaging structure that various different types gradually, (system in package, SIP) design concept is usually used in framework high-density packages structure to wherein various system in package.Generally speaking, system in package can be divided into multi-chip module (multi chip module, MCM), stacked package body on the packaging body (package on package, stacked package body POP) and in the packaging body (package in package, PIP) etc.Said multi-chip module (MCM) is meant lays several chips on same substrate; After chip is set; Utilize same all chips of packing colloid embedding again, and can be subdivided into stacked chips (stacked die) encapsulation or chip (side-by-side) encapsulation side by side again according to the arrangements of chips mode.Moreover; The structure of stacked package body (POP) is meant that completion one earlier has first packaging body of substrate on the said packaging body; Then pile up another second complete packaging body in the packing colloid upper surface of first packaging body again; Second packaging body sees through suitable switching element and is electrically connected on the substrate of first packaging body, thereby becomes a compound packaging structure.In comparison; The structure of stacked package body (PIP) then is to utilize another packing colloid that embedding such as the former encapsulation colloid of second packaging body, switching element and first packaging body etc. together is fixed on the substrate of first packaging body in the said packaging body, thereby becomes a compound packaging structure.
For instance; Please with reference to shown in Figure 1; It discloses a kind of packaging structure of existing tool stacked chips, and it comprises a base plate for packaging 11, one first chip 12, one second chip 13, one the 3rd chip 14, several first leads 15, several second leads 16 and several projections 17.Said base plate for packaging 11 carries said first chip 12, second chip 13 and the 3rd chip 14 in regular turn; Wherein said first chip 12 for example is the chip of CPU (CPU), and said second chip 13 and the 3rd chip 14 for example respectively are the memory body chip (like DRAM or FLASH) of suitable specification.The active surface of said first chip 12 up, and the back side is down and be attached on the said base plate for packaging 11; The active surface of said second chip 13 up, and the back side is down and be attached on the active surface of said first chip 12; The active surface of said the 3rd chip 14 down, and the back side is up and be positioned on the active surface of said second chip 13.Said first chip 12 and said second chip 13 electrically connect said base plate for packaging 11 through said first lead 15 and second lead 16 respectively.Said the 3rd chip 14 electrically connects said base plate for packaging 11 through said second lead 16 more indirectly through the active surface of said second chip 13 of said projection 17 electric connections.
Moreover please with reference to shown in Figure 2, it discloses the packaging structure of another kind of existing multicore sheet, and it comprises a lead frame 21, one first chip 22, one second chip 23, one the 3rd chip 24, several first leads 25, several second leads 26 and several projections 27.Said lead frame 21 has a chip bearing 211, several first pin 212 and several second pin 213, and wherein said first pin 212 and second pin 213 are staggered in the both sides at least of said chip bearing 211.Said first chip 22 for example is the chip of CPU (CPU), and said second chip 23 and the 3rd chip 24 for example respectively are the memory body chip (like DRAM or FLASH) of suitable specification.The active surface of said first chip 22 down, and the back side is up and be attached at the lower surface of said chip bearing 211; The active surface of said second chip 23 up, and the back side is down and be attached at the upper surface of said chip bearing 211; The active surface of said the 3rd chip 24 down, and the back side is up and be positioned on the active surface of said second chip 23.Said first chip 22 and said second chip 23 electrically connect said first pin 212 and second pin 213 through said first lead 25 and second lead 26 respectively.Said the 3rd chip 24 electrically connects a part of said second pin 213 through said second lead 26 more indirectly through the active surface of said second chip 23 of said projection 27 electric connections.
Though; Fig. 1 or 2 packaging structure can be incorporated into three or above chip in the same packaging structure; (active surface) go up to form circuit but its each chip that comprises is in fact all only on single surface, do not have functional circuit as for another surface (back side) of each chip.Therefore, on chip level, make the active surface of each chip further improve circuit layout density again and be not easy, for example possibly be subject to 0.09 or 0.13 micron circuit manufacturing technology of wafer.In addition; On the packaging structure grade, make single packaging structure comprise three or above chip and further reduce its volume again or further improve circuit layout density again and equally also be not easy, the chip of excessive number will take the space of too much substrate or lead frame; Too much gold thread, copper cash or the tin projection of maybe essential use; It also can take many limited encapsulated spaces, and makes volume and highly significantly increase, and is unfavorable for guaranteeing the radiating efficiency separately of a plurality of chips.As a result, encapsulate industry at present and can't in limited encapsulated space, design the package design that has higher circuit layout density than existing multichip package structure more.
So, be necessary to provide a kind of semiconductor packaging structure, to solve the existing in prior technology problem.
The utility model content
In view of this, the utility model provides a kind of semiconductor packaging structure, to solve the existing existing technical problem that can't further improve circuit layout density again of encapsulation technology.
The main purpose of the utility model is to provide a kind of semiconductor packaging structure; It at first produces the semiconductor crystal wafer that has the double-sided circuit layout and reroute layer; Then cut out wafer-level packaging (wafer level package by the semiconductor crystal wafer of arranging (reconstitution) arrangement position again again; WLP) double-sided circuit encapsulation unit; And pile up with this double-sided circuit encapsulation unit and to combine other chips (and passive component); Therefore can utilize the double-sided circuit encapsulation unit to increase the whole required stacked chips quantity of the circuit number of plies, minimizing packaging structure of one chip itself, the integrated circuit layout density of raising packaging structure really, and and then make the volume energy of whole semiconductor packaging structure realize compactization smoothly.
The secondary objective of the utility model is to provide a kind of semiconductor packaging structure; It is on a support plate, to pile up other chips of combination (and passive component) with the double-sided circuit encapsulation unit; Support plate more is provided with column-like projection block simultaneously, so that electrically connect the double-sided circuit encapsulation unit layer that reroutes up through lead, owing to be provided with column-like projection block; Therefore the lead Len req be can significantly reduce, and then wire rod consumption and packaging cost reduced relatively.
For reaching the aforementioned purpose of the utility model, the utility model provides a kind of semiconductor packaging structure, and wherein said semiconductor packaging structure comprises:
One support plate has several electrical junctions and several column-like projection block, and said column-like projection block is formed on a part of said electrical junction;
At least one double-sided circuit encapsulation unit is positioned on the said support plate, and has:
One two-sided chip has several first surface connection pads and several second surface connection pads;
One insulation layer is formed on the periphery of said two-sided chip;
One first layer that reroutes is formed on the first surface of said two-sided chip and insulation layer, and has one first and heavily distribute circuit electrically connecting the first surface connection pad of said two-sided chip, and has several first exposed weld pads; And
One second layer that reroutes is formed on the second surface of said two-sided chip and insulation layer, and has one second and heavily distribute circuit electrically connecting the second surface connection pad of said two-sided chip, and has several second exposed weld pads;
Several first electrically connect elements, reroute between the electrical junction of first weld pad and said support plate of layer in order to be electrically connected at first of said double-sided circuit encapsulation unit; And
Several second electrically connect elements, reroute between the column-like projection block of second weld pad and said support plate of layer in order to be electrically connected at second of said double-sided circuit encapsulation unit.
In an embodiment of the utility model, said two-sided chip is a silicon district, and said insulation layer is an epoxy resin layer.
In an embodiment of the utility model, said support plate is selected from a base plate for packaging, and said electrical junction is several connection pads.
In an embodiment of the utility model, said support plate is selected from a lead frame, and said electrical junction is several pin portions.
In an embodiment of the utility model, said column-like projection block is selected from copper post projection (Cu pillar bumps) or nickel post projection.
In an embodiment of the utility model, said first electrically connects element is selected from flip-chip (flip chip, FC) tin projection (bumps), golden projection, copper post (Cu pillar) projection or the nickel post projection of technology use.
In an embodiment of the utility model, said second electrically connects element is selected from gold thread, copper cash, plating palladium (Pd-coated) copper cash or the aluminum steel that routing (wire bonding) technology is used.
In an embodiment of the utility model, said semiconductor packaging structure comprises in addition:
At least one chip is stacked on second of said double-sided circuit encapsulation unit and reroutes on the layer, and has several exposed weld pads; And
Several the 3rd electrically connect elements, reroute between second weld pad of layer in order to second of the weld pad that is electrically connected at said chip and said double-sided circuit encapsulation unit.
In an embodiment of the utility model, the said the 3rd electrically connects element is selected from tin projection, golden projection, copper post projection or the nickel post projection that controlled collapsible chip connec-tion uses.
In an embodiment of the utility model; The first surface circuit layer that said two-sided chip is provided with said first surface connection pad is selected from the surface circuit of CPU (CPU), logical integrated circuit (logic IC), MEMS (MEMS) or integrated passive component device (IPD), but also optional from the dynamic surface circuit of random access memory (DRAM) or flash memory (FLASH).
In an embodiment of the utility model; The second surface circuit layer that said two-sided chip is provided with said second surface connection pad is selected from the surface circuit of Dynamic Random Access Memory or flash memory, but also can be selected from the surface circuit of CPU, logic IC, MEMS or integrated passive component device.
In an embodiment of the utility model, said chip is selected from the chip of Dynamic Random Access Memory or flash memory, but also can be selected from CPU, the chip of logic IC, MEMS or integrated passive component device.
In an embodiment of the utility model; Said semiconductor packaging structure comprises at least one passive component (passive element) in addition; Said passive component has two-terminal at least, said terminal be electrically connected to second of said double-sided circuit encapsulation unit reroute the layer second weld pad.
Moreover for reaching the aforementioned purpose of the utility model, the utility model provides another kind of semiconductor packaging structure, and wherein said semiconductor packaging structure comprises:
One support plate;
At least one double-sided circuit encapsulation unit is positioned on the said support plate, and has:
One two-sided chip has several first surface connection pads and several second surface connection pads;
One insulation layer is formed on the periphery of said two-sided chip;
One first layer that reroutes; Be formed on the first surface of said two-sided chip and insulation layer; And have one first and heavily distribute circuit electrically connecting the first surface connection pad of said two-sided chip, and have several first exposed weld pads, to electrically connect said support plate; And
One second layer that reroutes; Be formed on the second surface of said two-sided chip and insulation layer; And have one second and heavily distribute circuit electrically connecting the second surface connection pad of said two-sided chip, and have several second exposed weld pads, to electrically connect said support plate; And
At least one chip is stacked on second of said double-sided circuit encapsulation unit and reroutes on the layer, and has several exposed weld pads, with electrically connect said second reroute layer second weld pad.
Description of drawings
Fig. 1 is the sketch map of the packaging structure of an existing tool stacked chips.
Fig. 2 is the sketch map of the packaging structure of another existing multicore sheet.
Fig. 3 A, 3B, 3C and 3D are the sketch mapes of each step of manufacturing approach of the utility model first embodiment semiconductor packaging structure.
Fig. 4 is the sketch map of the utility model first embodiment semiconductor packaging structure.
Fig. 5 is the sketch map of the utility model second embodiment semiconductor packaging structure.
Embodiment
For making the utility model above-mentioned purpose, characteristic and advantage more obviously understandable, hereinafter is special lifts the utility model preferred embodiment, and conjunction with figs., elaborates as follows.Moreover, the direction term that the utility model is mentioned, for example " on ", D score, " preceding ", " back ", " left side ", " right side ", " interior ", " outward ", " side " etc., only be direction with reference to annexed drawings.Therefore, the direction term of use is in order to explanation and understands the utility model, but not in order to restriction the utility model.
Please with reference to shown in Fig. 3 A, 3B, 3C, the 3D and 4; Its summary discloses the sketch map of each step of manufacturing approach of the utility model first embodiment semiconductor packaging structure, manufacture process and process principle thereof that the utility model will utilize Fig. 3 A to 3D and 4 to specify one by one to state each step on first embodiment in hereinafter.
Please with reference to shown in Fig. 3 A; The manufacturing approach of the semiconductor packaging structure of the utility model first embodiment at first is: semiconductor wafer 30 is provided; Wherein said semiconductor crystal wafer 30 is to be processed to form first surface circuit layer (not illustrating) at its first surface earlier with wafer manufacturing process; Then protect the first surface circuit layer, and under the support of a carriage (not illustrating), carry out the turn-over action with a protective tapes (not illustrating); Subsequently, be processed to form second surface circuit layer (not illustrating) with wafer manufacturing process at its second surface again.So, can make said semiconductor crystal wafer 30 have the double-sided circuit layer, and can predefine go out several two-sided chips 31, the two-sided chip 31 of this moment still adjoins each other, and cuts apart singly as yet and leaves.Moreover said semiconductor crystal wafer 30 for example is selected from a Silicon Wafer, and said several two-sided chips 31 are several silicon districts simultaneously, but are not limited to this.
Please with reference to shown in Fig. 3 B; The manufacturing approach of the semiconductor packaging structure of the utility model first embodiment then is: the semiconductor crystal wafer 30 to Fig. 3 A cuts; To form each independent single two-sided chip 31; Prepare a carriage 34 and a protective tapes 33 in addition, but also can use other equivalent support components to substitute.At this moment; Utilize mechanical arm to draw one by one and will be separately independently two-sided chip 31 be arranged in again in regular turn on the protective tapes 33 of this carriage 34; Thereby form another and arrange again the semiconductor crystal wafer 38 of (reconstitution) arrangement position; Be that first surface circuit layer by said two-sided chip 31 is fixed on the said protective tapes 33 down at this moment, with and the second surface circuit layer up.After cutting; Each is reserved and has a spacing 32 between the per two adjacent two-sided chips 31; Then said spacing 32 is carried out the injecting glue operation, to form an insulation bonding pad 35 in said spacing 32 positions, said insulation bonding pad 35 for example is an epoxy resin layer; Its material particularly can be as the epoxy resin compound of circuit board insulating barrier or packaging adhesive material and the mixture of insulation filling particle, but is not limited in this.The connection that can insulate in said insulation bonding pad 35 and support said several two-sided chips 31; Wherein said several two-sided chips 31 are generally to be array/rectangular equidistance to be arranged in the said insulation bonding pad 32, and said several two-sided chips 31 are separated from each other and are not in contact with one another.
Please with reference to shown in Fig. 3 C; The manufacturing approach of the semiconductor packaging structure of the utility model first embodiment then is: use base plate for packaging (or wafer) to form the technology of surface lines; On second and first surface of said two-sided chip 31 and insulation bonding pad 32, form the insulating barrier and the metallic circuit layer of several layers of alternated respectively; To constitute reroute layer (redistribution layer, RDL) 36 respectively jointly.Just, on the second surface of said several two-sided chips 31 and insulation bonding pad 32, form one second layer that reroutes, and then carry out turn-over and make first surface up, and tear original protective tapes 33 and carriage 34 on first surface off.Then, re-use another group protective tapes and carriage and change into and attach the second surface that supports said several two-sided chips 31 and insulation bonding pad 32, so that on the first surface of said several two-sided chips 31 and insulation bonding pad 32, form one first layer that reroutes.These purpose being set giving explanation in addition in hereinafter of layer 36 of rerouting.
Please with reference to shown in Fig. 3 C and the 3D; The manufacturing approach of the semiconductor packaging structure of the utility model first embodiment then is: the bearing of trend along said spacing 32 cuts said insulation bonding pad 32; To isolate several double-sided circuit encapsulation units 40, wherein each double-sided circuit encapsulation unit 40 all comprises: a two-sided chip 41, an insulation layer 42, one first layer 43 and 1 second layer 44 that reroutes that reroutes.Said two-sided chip 41 promptly is equal to the two-sided chip 31 of Fig. 3 C; And have a first surface circuit layer 411 and a second surface circuit layer 412, said first surface circuit layer 411 and second surface circuit layer 412 have several first surface connection pads and several second surface connection pads (not illustrating) respectively.It is the crystal wafer chip dimension packaging body (WLCSP) with double-sided circuit that said double-sided circuit encapsulation unit 40 also can be regarded as.Said first surface circuit layer 411 for example is the surface circuit of CPU (CPU), logic IC (logic IC), MEMS (MEMS) or integrated passive component device (IPD); And said second surface circuit layer 412 for example is the surface circuit of Dynamic Random Access Memory (DRAM) or flash memory (FLASH); But be not limited to this; For example both selection groups can exchange, or select to form identical surface circuit.Residue part after insulation bonding pad 32 cutting and separating that said insulation layer 42 promptly is Fig. 3 C, said insulation layer 42 is formed on the periphery of said two-sided chip 41.Said first reroute the layer 43 promptly be Fig. 3 C wherein one reroute the layer 36; Said first layer that reroutes 43 is formed on the first surface of said two-sided chip 41 and insulation layer 42; And have one first and heavily distribute circuit 430, and have several first exposed weld pads 431 with the first surface connection pad of the first surface circuit layer 411 that electrically connects said two-sided chip 41.
Similar; Said second layer 44 that reroutes promptly is another of Fig. 3 C layer 36 that reroutes; Said second layer that reroutes 44 is formed on the second surface of said two-sided chip 41 and insulation layer 42; And have one second and heavily distribute circuit 440, and have several second exposed weld pads 441 with the second surface connection pad of the second surface circuit layer 412 that electrically connects said two-sided chip 41.The purpose that is provided with of said first and second layer 43,44 that reroutes is first and second surperficial connection pad (not illustrating) of first and second surface circuit layer 411,412 of said two-sided chip 31 is extended outwardly on first and second surface of said insulation layer 42 through the said metallic circuit that reroutes layer 36; So that make last first and second exposed weld pad 431,441 have suitable weld pad size and weld pad spacing, to be adapted at being used in the subsequent applications outwards electrically connecting lead or projection.
Please with reference to shown in Fig. 3 D and 4; The manufacturing approach of the semiconductor packaging structure of the utility model first embodiment is at last: after obtaining said double-sided circuit encapsulation unit 40 according to above-mentioned manufacturing approach, further said double-sided circuit encapsulation unit 40 is applied in the encapsulation process operation of a multi-chip semiconductor package structure.As shown in Figure 4; In the utility model first embodiment, the semiconductor packaging structure comprises: at least one double-sided circuit encapsulation unit 40, a base plate for packaging 70, several wires 81, several first projections 82, at least one chip 90, several second projections 91 and a packing colloid 80.The quantity of said double-sided circuit encapsulation unit 40 can use on demand one or more than.Said base plate for packaging 70 is in order to as a support plate, to carry said double-sided circuit encapsulation unit 40.Said base plate for packaging 70 is the small-sized multilayer boards that are used for carries chips and make packaging body; It has several tin balls 71, several connection pads 72 and several column-like projection block 73; Wherein said tin ball 71 is the I/O portion of said base plate for packaging 70; Said connection pad 72 is the electrical junction of said base plate for packaging 70, and said column-like projection block 73 is formed on the said connection pad 72 of at least one part, for example is formed on the connection pad of locating around said base plate for packaging 70 upper surfaces 72.
Moreover the upper surface of said base plate for packaging 70 is in order to carrying said double-sided circuit encapsulation unit 40, and makes said first layer 43 that reroutes reach said second layer 44 (or opposite configuration) down that reroutes up.Said first surface circuit layer 411 for example is the surface circuit of CPU (CPU), logic IC (logic IC), MEMS (MEMS) or integrated passive component device (IPD); And said second surface circuit layer 412 for example is the surface circuit of Dynamic Random Access Memory (DRAM) or flash memory (FLASH); But be not limited to this; For example both selection groups can exchange according to product demand, or select to form identical surface circuit.Simultaneously, 90 of said chips are optional from the dynamic chips of random access memories or flash memory, but also can be selected from the chip of CPU, logic IC, MEMS or integrated passive component device.The quantity of said chip 90 can use on demand one or more than.
In addition; In the present embodiment; Said first projection 82, lead 81 and the 3rd projection 91 electrically connect element as first, second and third respectively; Wherein said first projection 82 can be selected from flip-chip (flip chip, FC) tin projection (bumps), golden projection, copper post (Cu pillar) projection or the nickel post projection of technology use.For example optional several gold threads, copper cash, plating palladium (Pd-coated) copper cash or the aluminum steel that uses from routing (wire bonding) technology of said lead 81; Said the 3rd projection 82 can be selected from flip-chip (flip chip, FC) several tin projections (bumps), golden projection, copper column (Cu pillar) projection or the nickel post projection of technology use.In when assembling, said first projection 82 reroutes between the connection pad 72 (electrical junction) of weld pad 441 and said base plate for packaging 70 (support plate) of layer 44 in order to be electrically connected at second of said double-sided circuit encapsulation unit 40.Said lead 81 reroutes between the end face of column-like projection block 73 of layer 43 weld pad 431 and said base plate for packaging 70 (support plate) in order to be electrically connected at first of said double-sided circuit encapsulation unit 40.Simultaneously; Said second projection 91 reroutes between layer 43 the weld pad 431 and said chip 90 active lip-deep several weld pads down in order to be electrically connected at first of said double-sided circuit encapsulation unit 40, thereby makes said chip 90 fixing and be stacked on first of said double-sided circuit encapsulation unit 40 layer 43 top of rerouting.After accomplish electrically connecting, said packing colloid 80 promptly capable of using coats the positions such as connection pad 72, column-like projection block 73 and a part of upper surface of the said double-sided circuit encapsulation unit of protection 40, lead 81, first projection 82, second projection 91, chip 90, base plate for packaging 70.So, can be encapsulated into a kind of multi-chip semiconductor package structure with said double-sided circuit encapsulation unit 40.
Please with reference to shown in Figure 5; The semiconductor packaging structure of the utility model second embodiment is similar in appearance to the utility model first embodiment; And roughly continue to use element title and the figure number that is same as Fig. 3 D, be but second embodiment is different from the difference characteristic of first embodiment: the semiconductor packaging structure of said second embodiment comprises: at least one double-sided circuit encapsulation unit 40, a lead frame 100, several wires 81, several first projections 82, at least one chip 90, several second projections 91, at least one passive component 110 and packing colloids 80.Said double-sided circuit encapsulation unit 40 comprises a two-sided circuit package unit 41, an insulation layer 42, one first layer 43 and 1 second layer 44 that reroutes that reroutes, and its detail structure is same as the explanation that preceding text are done to Fig. 3 D, so give detailed description no longer in addition in this.The difference of present embodiment and Fig. 4 is that mainly present embodiment uses lead frame 100 in order to as a support plate, to carry said double-sided circuit encapsulation unit 40; And set up said at least one passive component 110 in addition.Said lead frame 100 has several pin portions 101; Wherein the cited lead frame 100 of present embodiment belongs to the lead frame of square flat outer-pin-free encapsulation (QFN) type; Its pin portion 101 generally is array/rectangular equidistance to arrange a plurality of island metal gaskets at grade; But the pattern of said lead frame 100 is not limited to this, for example also can be as lead frame 21 patterns of Fig. 2.Said pin portion 101 is the electrical junction of said lead frame 100, and said column-like projection block 73 is formed in the said pin portion 101 of at least one part, for example is formed in the pin portion 101 that locates around the said lead frame 100.First of said double-sided circuit encapsulation unit 40 layer 43 that reroutes reaches said second layer 44 down (or opposite configuration) that reroutes up.Also first embodiment with Fig. 4 is identical for the kind of said first surface circuit layer 411, second surface circuit layer 412 and chip 90, so give detailed description no longer in addition in this.
Moreover in the present embodiment, said first projection 82, lead 81 and the 3rd projection 91 electrically connect element as first, second and third respectively, and it selects group also can be with reference to first embodiment of Fig. 4.In when assembling, said first projection 82 reroutes between the pin portion 101 (electrical junction) of weld pad 441 and said lead frame 100 (support plate) of layer 44 in order to be electrically connected at second of said double-sided circuit encapsulation unit 40.Said lead 81 reroutes between the end face of column-like projection block 73 of layer 43 weld pad 431 and said lead frame 100 (support plate) in order to be electrically connected at first of said double-sided circuit encapsulation unit 40.Simultaneously; Said second projection 91 reroutes between layer 43 the weld pad 431 and said chip 90 active lip-deep several weld pads down in order to be electrically connected at first of said double-sided circuit encapsulation unit 40, thereby makes said chip 90 fixing and be stacked on first of said double-sided circuit encapsulation unit 40 layer 43 top of rerouting.Said at least one passive component 110 for example is resistive element, inductance element or capacity cell etc.; Said passive component 110 has two-terminal at least; The welding that said terminal is also suitable and be electrically connected at first of said double-sided circuit encapsulation unit 40 and reroute on layer 43 the weld pad 431; To be stacked on first of said double-sided circuit encapsulation unit 40 layer 43 top of rerouting, and abut against said chip 90 sides.After accomplish electrically connecting, said packing colloid 80 promptly capable of using coats the positions such as connection pad 72, column-like projection block 73 and a part of upper surface of the said double-sided circuit encapsulation unit of protection 40, lead 81, first projection 82, second projection 91, chip 90, passive component 110, base plate for packaging 70.So, can be encapsulated into a kind of multi-chip semiconductor package structure with said double-sided circuit encapsulation unit 40.
As stated; There is the technical problem that can't further improve circuit layout density again compared to existing multicore sheet encapsulation technology; The utility model of Fig. 3 A to 5 is at first produced the semiconductor crystal wafer that has the double-sided circuit layout and reroute layer; Then cut out wafer-level packaging (wafer level package by the semiconductor crystal wafer of arranging (reconstitution) arrangement position again again; WLP) double-sided circuit encapsulation unit; And pile up with this double-sided circuit encapsulation unit and to combine other chips (and passive component), therefore can utilize really the double-sided circuit encapsulation unit increase one chip itself the circuit number of plies, reduce the whole required stacked chips quantity of packaging structure, improve the integrated circuit layout density of packaging structure, and and then the volume energy that makes whole multi-chip semiconductor package structure compactization of realization smoothly.Moreover; The utility model is on a support plate, to pile up other chips of combination (and passive component) with the double-sided circuit encapsulation unit; Make support plate be provided with column-like projection block simultaneously, so that electrically connect the double-sided circuit encapsulation unit layer that reroutes up, owing to be provided with column-like projection block through lead; Therefore the lead Len req be can significantly reduce, and then wire rod consumption and packaging cost reduced relatively.
The utility model is described by above-mentioned related embodiment, yet the foregoing description is merely the example of implementing the utility model.Must be pointed out that disclosed embodiment does not limit the scope of the utility model.On the contrary, being contained in the spirit of claims and the modification and impartial setting of scope includes in the scope of the utility model.

Claims (10)

1. semiconductor packaging structure, it is characterized in that: said semiconductor packaging structure comprises:
One support plate has several electrical junctions and several column-like projection block, and said column-like projection block is formed on a part of said electrical junction;
At least one double-sided circuit encapsulation unit is positioned on the said support plate, and has:
One two-sided chip has several first surface connection pads and several second surface connection pads;
One insulation layer is formed on the periphery of said two-sided chip;
One first layer that reroutes is formed on the first surface of said two-sided chip and insulation layer, and has one first and heavily distribute circuit electrically connecting the first surface connection pad of said two-sided chip, and has several first weld pad; And
One second layer that reroutes is formed on the second surface of said two-sided chip and insulation layer, and has one second and heavily distribute circuit electrically connecting the second surface connection pad of said two-sided chip, and has several second weld pad;
Several first electrically connect elements, reroute between the electrical junction of first weld pad and said support plate of layer in order to be electrically connected at first of said double-sided circuit encapsulation unit; And
Several second electrically connect elements, reroute between the column-like projection block of second weld pad and said support plate of layer in order to be electrically connected at second of said double-sided circuit encapsulation unit.
2. semiconductor packaging structure as claimed in claim 1 is characterized in that: said two-sided chip is a silicon district, and said insulation layer is an epoxy resin layer.
3. semiconductor packaging structure as claimed in claim 1 is characterized in that: said support plate is selected from a base plate for packaging, and said electrical junction is several connection pads; Perhaps, said support plate is selected from a lead frame, and said electrical junction is several pin portions.
4. semiconductor packaging structure as claimed in claim 1 is characterized in that: said column-like projection block is selected from copper post projection or nickel post projection.
5. semiconductor packaging structure as claimed in claim 1 is characterized in that: said first electrically connects element is selected from tin projection, golden projection, copper post projection or nickel post projection.
6. semiconductor packaging structure as claimed in claim 1 is characterized in that: said second electrically connects element is selected from gold thread, copper cash, plating palladium copper cash or aluminum steel.
7. semiconductor packaging structure as claimed in claim 1 is characterized in that: said semiconductor packaging structure comprises in addition:
At least one chip is stacked on second of said double-sided circuit encapsulation unit and reroutes on the layer, and has several exposed weld pads; And
Several the 3rd electrically connect elements, reroute between second weld pad of layer in order to second of the weld pad that is electrically connected at said chip and said double-sided circuit encapsulation unit.
8. semiconductor packaging structure as claimed in claim 1 is characterized in that: said chip is selected from the chip of Dynamic Random Access Memory, flash memory, CPU, logic IC, MEMS or integrated passive component device.
9. semiconductor packaging structure as claimed in claim 1; It is characterized in that: said semiconductor packaging structure comprises at least one passive component in addition; Said passive component has two-terminal at least, said terminal be electrically connected to second of said double-sided circuit encapsulation unit reroute the layer second weld pad.
10. semiconductor packaging structure, it is characterized in that: said semiconductor packaging structure comprises:
One support plate;
At least one double-sided circuit encapsulation unit is positioned on the said support plate, and has:
One two-sided chip has several first surface connection pads and several second surface connection pads;
One insulation layer is formed on the periphery of said two-sided chip;
One first layer that reroutes; Be formed on the first surface of said two-sided chip and insulation layer; And have one first and heavily distribute circuit electrically connecting the first surface connection pad of said two-sided chip, and have several first exposed weld pads, to electrically connect said support plate; And
One second layer that reroutes is formed on the second surface of said two-sided chip and insulation layer, and has one second and heavily distribute circuit electrically connecting the second surface connection pad of said two-sided chip, and
Have several second exposed weld pads, to electrically connect said support plate; And
At least one chip is stacked on second of said double-sided circuit encapsulation unit and reroutes on the layer, and has several exposed weld pads, with electrically connect said second reroute layer second weld pad.
CN2011204980871U 2011-12-02 2011-12-02 Semiconductor encapsulation structure Expired - Fee Related CN202394956U (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
CN2011204980871U CN202394956U (en) 2011-12-02 2011-12-02 Semiconductor encapsulation structure

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CN2011204980871U CN202394956U (en) 2011-12-02 2011-12-02 Semiconductor encapsulation structure

Publications (1)

Publication Number Publication Date
CN202394956U true CN202394956U (en) 2012-08-22

Family

ID=46669861

Family Applications (1)

Application Number Title Priority Date Filing Date
CN2011204980871U Expired - Fee Related CN202394956U (en) 2011-12-02 2011-12-02 Semiconductor encapsulation structure

Country Status (1)

Country Link
CN (1) CN202394956U (en)

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN103779303A (en) * 2012-10-18 2014-05-07 英飞凌科技股份有限公司 Bump package and methods of formation thereof
CN104752383A (en) * 2015-04-15 2015-07-01 江苏晟芯微电子有限公司 Novel semiconductor anti-shedding encapsulation structure
CN106611715A (en) * 2015-10-21 2017-05-03 精材科技股份有限公司 Chip package and method for forming the same
CN107871732A (en) * 2016-09-23 2018-04-03 深圳市中兴微电子技术有限公司 Encapsulating structure
CN113161303A (en) * 2021-03-03 2021-07-23 江苏苏益电器股份有限公司 System-in-package method and structure

Cited By (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN103779303A (en) * 2012-10-18 2014-05-07 英飞凌科技股份有限公司 Bump package and methods of formation thereof
US9373609B2 (en) 2012-10-18 2016-06-21 Infineon Technologies Ag Bump package and methods of formation thereof
CN104752383A (en) * 2015-04-15 2015-07-01 江苏晟芯微电子有限公司 Novel semiconductor anti-shedding encapsulation structure
CN104752383B (en) * 2015-04-15 2017-08-08 苏州聚达晟芯微电子有限公司 A kind of novel semi-conductor anti-dropout encapsulating structure
CN106611715A (en) * 2015-10-21 2017-05-03 精材科技股份有限公司 Chip package and method for forming the same
CN107871732A (en) * 2016-09-23 2018-04-03 深圳市中兴微电子技术有限公司 Encapsulating structure
CN113161303A (en) * 2021-03-03 2021-07-23 江苏苏益电器股份有限公司 System-in-package method and structure

Similar Documents

Publication Publication Date Title
US7598617B2 (en) Stack package utilizing through vias and re-distribution lines
US6900528B2 (en) Stacked mass storage flash memory package
KR100800473B1 (en) Stack chip having redistributed chip pad and stack chip package using the same
EP2033220B1 (en) Stack die packages
TWI355061B (en) Stacked-type chip package structure and fabricatio
US20110089575A1 (en) Multichip package and method of manufacturing the same
US20130228898A1 (en) Semiconductor device having penetrating electrodes each penetrating through substrate
CN106548948A (en) Integrated multi output packaging part and manufacture method
US9299685B2 (en) Multi-chip package having a logic chip disposed in a package substrate opening and connecting to an interposer
JP2013197387A (en) Semiconductor device
CN202394956U (en) Semiconductor encapsulation structure
CN102790042A (en) Semiconductor chip stacking structure
CN102163595A (en) Stacked semiconductor package
CN202394958U (en) Wafer-level semiconductor packaging structure
CN101452860B (en) Multi-chip stacking structure and preparation thereof
KR102696464B1 (en) Semiconductor packages
CN202394961U (en) Semiconductor wafer with radiating columns and packaging structure
CN202394957U (en) Semi-conductor wafer and packaging structure
TWI455280B (en) Semiconductor package structure
US20040238924A1 (en) Semiconductor package
US20230230902A1 (en) Semiconductor package structure and manufacturing method thereof
CN101465341B (en) Stacked chip packaging structure
KR101185858B1 (en) Semiconductor chip and stacked semiconductor package having the same
CN101667545B (en) Multi-chip stacked structure and manufacturing method thereof
CN101236962A (en) Multi-chip stacking structure and its making method

Legal Events

Date Code Title Description
C14 Grant of patent or utility model
GR01 Patent grant
C56 Change in the name or address of the patentee

Owner name: ADVANCED SEMICONDUCTOR (SHANGHAI) CO., LTD.

Free format text: FORMER NAME: ADVANCED SEMICONDUCTOR ENGINEERING (SHANGHAI) INC.

CP01 Change in the name or title of a patent holder

Address after: 201203 Shanghai Jinke Road, Pudong New Area Zhangjiang hi tech Park No. 2300

Patentee after: Advanced Semiconductor (Shanghai) Co., Ltd.

Address before: 201203 Shanghai Jinke Road, Pudong New Area Zhangjiang hi tech Park No. 2300

Patentee before: Advanced Semiconductor (Shanghai), Inc.

CF01 Termination of patent right due to non-payment of annual fee
CF01 Termination of patent right due to non-payment of annual fee

Granted publication date: 20120822

Termination date: 20201202