CN202142534U - Array baseplate, liquid crystal display panel and display device - Google Patents
Array baseplate, liquid crystal display panel and display device Download PDFInfo
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- CN202142534U CN202142534U CN201120288922U CN201120288922U CN202142534U CN 202142534 U CN202142534 U CN 202142534U CN 201120288922 U CN201120288922 U CN 201120288922U CN 201120288922 U CN201120288922 U CN 201120288922U CN 202142534 U CN202142534 U CN 202142534U
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Abstract
The utility model discloses an array baseplate comprising a data line and a grid electrode scanning line, wherein overlapping regions exist between the data line and the grid electrode scanning line; a passivation layer covers on the data line; the width of the data line in at least one overlapping region between the data line and the grid electrode scanning line is less than that of the data line in non-overlapping region between the data line and the grid electrode scanning line; at least one via hole is respectively arranged in a transition region of width changing of the data line on the passivation layer; pixel electrode materials are deposited above the region where the data line is narrowed; and the pixel electrode materials are communicated with the data line through the via holes. By utilizing the array baseplate provided by the utility model, the parasitic capacitance between the data line and the grid electrode scanning line can be decreased and the display effect of an LCD (Liquid Crystal Display) is improved.
Description
Technical field
The utility model relates to technical field of liquid crystal display, relates in particular to a kind of array base palte, liquid crystal panel and display device.
Background technology
In recent years, along with popularizing of digital to television, traditional cathode ray tube (CRT, Cathode Ray Tube) shows because digitlization difficulty and volume is big, weight big, shortcoming such as radiation is arranged is substituted by Display Technique of new generation gradually.That LCD (LCD, LiLuid Crystal Display) has is in light weight, volume is little, low in energy consumption, radiationless, display resolution advantages of higher, becomes main product gradually.
The agent structure of LCD comprises that to the array base palte of box and color membrane substrates the concrete formation of array base palte is shown in Fig. 1 a, and Fig. 1 b is along the sectional view of A-A ' line drawing along array base palte vertical view of the prior art among Fig. 1 a in addition.Wherein array base palte comprises glass substrate 101; Through covering gate metal film on glass substrate 101; Based on the film formed gate electrode of the grid metal that covers 102, controlling grid scan line 103 and storage capacitor electrode 104; On gate electrode 102 and controlling grid scan line 103, be coated with insulating barrier 105, on insulating barrier 105, cover active layer 106 and data wire 109, on active layer 106, be respectively arranged with source electrode 107 and drain electrode 108; Wherein source electrode 107 is oppositely arranged with drain electrode 108, and an end of source electrode 107 contacts with data wire 109; On the insulating barrier 105 that covers active layer 106 and data wire 109, be coated with passivation layer 110, on passivation layer 110, be formed with pixel electrode 111, one of several first via holes 112 that pixel electrode 111 passes through setting on the passivation layer 110 are connected with drain electrode 108.
In the prior art; In the manufacture process of LCD array base palte, thereby because between pixel electrode 111 and the controlling grid scan line 103, between pixel electrode 111 and the data wire 107, data wire 107 makes array base palte have parasitic capacitance with the overlapping that intersects between the controlling grid scan line 103.Parasitic capacitance is meant non-design and the electric capacity that produces; Because the existence of this parasitic capacitance; Just can produce the delay of source signal; And then owing to the delay of source signal changes the display brightness of LCD, simultaneously because the vertical crosstalk that the delay of source signal produces, make can LCD display image produce problems such as flicker, image persistance or image brightness be inhomogeneous.
The utility model content
The utility model embodiment provides a kind of array base palte, in order to improve the display effect of LCD.
A kind of array base palte; Comprise data wire and controlling grid scan line; There is overlapping region between said data wire and the controlling grid scan line; Be coated with passivation layer on the said data wire, the width of said data wire at least one zone that overlaps with controlling grid scan line, with the non-overlapping of controlling grid scan line regional in narrow width; The transitional region that changes at data wire width on the said passivation layer is respectively arranged with at least one via hole; The top of data wire narrowed areas deposits the pixel electrode material, and said pixel electrode material is through said via hole and data wire conducting.
A kind of liquid crystal panel comprises the array base palte that uses the utility model to provide.
A kind of display device comprises the liquid crystal panel that uses the utility model to provide.
The array base palte that the utility model embodiment provides; Because the width of data wire in the zone that overlaps with controlling grid scan line; With the zone of the non-overlapping of controlling grid scan line in width diminish; Thereby avoided in the array base palte of the prior art can influencing the problem of LCD display effect owing to there are a large amount of parasitic capacitances, the array base palte that therefore provides based on the utility model embodiment can improve the display effect of LCD.
Description of drawings
Fig. 1 a is the plan structure figure of LCD array base palte of the prior art;
Fig. 1 b is along the sectional view of A-A ' line drawing along LCD array base palte vertical view of the prior art among Fig. 1 a;
Fig. 2 a is the plan structure figure of LCD array base palte among the utility model embodiment;
Fig. 2 b is the sectional view along the LCD array base palte plan structure figure among the utility model embodiment among Fig. 2 a along A-A ' line drawing;
The manufacturing method of array base plate flow chart that Fig. 3 proposes for the utility model embodiment;
Form the plan structure figure of the array base palte after gate electrode, controlling grid scan line and the storage capacitor electrode on the glass substrate that Fig. 4 a proposes for the utility model embodiment;
Fig. 4 b is to the plan structure figure of the array base palte shown in Fig. 4 a sectional view along A-A ' line drawing;
The array base palte plan structure figure that insulating barrier is set that Fig. 5 a proposes for the utility model embodiment;
Fig. 5 b is to the sectional view of the array base palte plan structure figure shown in Fig. 5 a along A-A ' line drawing;
Array base palte plan structure figure behind the covering passivation layer that Fig. 6 a proposes for the utility model embodiment;
Fig. 6 b is to the sectional view of the array base palte plan structure figure shown in Fig. 6 a along A-A ' line drawing.
Embodiment
Postpone to the source signal that produces owing to parasitic capacitance on the LCD array base palte in the prior art; And then owing to this source signal postpones the display brightness of LCD is changed; Simultaneously because change the vertical crosstalk that source signal postpones generation; Make the display image of LCD produce problems such as flicker, image persistance or image brightness be inhomogeneous; Thereby had influence on the display effect of LCD, the utility model embodiment provides a kind of array base palte, through reducing the overlapping area between data wire and the controlling grid scan line; And then reduce the parasitic capacitance that produces owing to the overlapping between data wire and the controlling grid scan line, thereby make that the display effect of the LCD that the array base palte that provides based on the utility model embodiment is made can be improved preferably.
The array base palte that the utility model embodiment proposes is formed structure shown in Fig. 2 a; Fig. 2 b is the array base palte vertical view that proposes along the utility model embodiment among Fig. 2 a sectional view along A-A ' line drawing in addition; Wherein the array base palte of the utility model proposition comprises glass substrate 101; Through covering gate metal film on glass substrate 101,, on gate electrode 102 and controlling grid scan line 103, be coated with insulating barrier 105 based on the film formed gate electrode of the grid metal that covers 102, controlling grid scan line 103 and storage capacitor electrode 104; On insulating barrier 105, cover active layer 106 and data wire 109; On active layer 106, be respectively arranged with source electrode 107 and drain electrode 108, wherein source electrode 107 is oppositely arranged with drain electrode 108, and an end of source electrode 107 contacts with data wire 109; On the insulating barrier 105 that covers active layer 106 and data wire 109, be coated with passivation layer 110, on passivation layer 110, be formed with pixel electrode 111, one of several first via holes 112 that pixel electrode 111 passes through setting on the passivation layer 110 are connected with drain electrode 108.
Wherein in the prior art; The width of data wire 109 in the zone that between data wire 109 and controlling grid scan line 103, overlaps; Identical with the width of data wire 109 in the zone of non-overlapping between data wire 109 and controlling grid scan line 103; Will cause the overlapping region between data wire 109 and the controlling grid scan line 103 bigger like this, thereby can produce bigger parasitic capacitance.
Because on the array base palte in the prior art, be arranged on the data wire 109 on the insulating barrier 105 and the overlapping region part that is arranged between the controlling grid scan line 103 on the glass substrate 101 can produce parasitic capacitance, according to the computing formula of parasitic capacitance:
C
gd＝ε
0ε
nA/d
Wherein, C
GdRepresent parasitic capacitance, ε
0Show permittivity of vacuum, ε
nThe dielectric constant of expression medium, A representes the overlapping region area of controlling grid scan line 103 and data wire 109, d representes the vertical range between controlling grid scan line 103 and the data wire 109;
Computing formula by above-mentioned parasitic capacitance can know, wanting to reduce parasitic capacitance can reach and reduce parasitic capacitance C through reducing data wire 109 and the overlapping region area A between the controlling grid scan line 103 on the glass substrate 101 on the insulating barrier 105 or increase vertical range d between controlling grid scan line 103 and the data wire 109
GdPurpose, the array base palte that the utility model embodiment proposes here realizes reducing parasitic capacitance C through the overlapping region area A that reduces between the controlling grid scan line 103 on data wire on the insulating barrier 105 109 and the glass substrate 101
GdPurpose.Particularly; The width of data wire 109 in the zone that the utility model embodiment proposes between data wire 109 and controlling grid scan line 103, to overlap; Narrowed width than data wire 109 in the zone of non-overlapping between data wire 109 and controlling grid scan line 103; Thereby reduce the overlapping region area between data wire 109 and the controlling grid scan line 103; And then reduce between data wire 109 and the controlling grid scan line 103 parasitic capacitance that produces owing to the bigger reason of overlapping region, thereby improve the display effect of LCD.
More particularly; The width of data wire 109 in the zone that overlaps with controlling grid scan line 103; With the zone of controlling grid scan line 103 non-overlappings in width diminish; The transitional region of the part that the part that wherein width is little in data wire 109 in passivation layer 110 and width are big is respectively arranged with second via hole 113; And then on second via hole 113 that is provided with respectively on the passivation layer 110, depositing the pixel electrode material, the conducting in zone so just can compensate the effect that reduces to make the resistance increase owing to the width of data wire 109 thereby the width of realization pixel electrode material and data wire 109 diminishes; Cover the pixel electrode material on the transitional region that data wire 109 width change simultaneously, can't and data wire 109 between form parasitic capacitance.
The narrowed width of data wire 109 in the zone that overlaps between data wire 109 that proposes in the foregoing description and the controlling grid scan line 103; The width that data wire 109 narrows down can but be not limited to data wire 109 in the zone of non-overlapping between data wire 109 and the controlling grid scan line 103 width 1/3rd; The shape of the transitional region of the part that the part that width is little in the data wire 109 and width are big can be a rectangle; Also can be other shape, like round rectangle, arc etc.
The array base palte that the utility model embodiment proposes; Be based on that optimum implementation realizes; Wherein, Adjustment data wire 109 and controlling grid scan line 103 between the width of data wire 109 in the zone that overlaps, the narrowed width of data wire 109 that specifically can the zone of all overlappings between data wire 109 and the controlling grid scan line 103 is interior also can a narrowed width with the data wire 109 in one of them overlapping region or the several overlapping region.More specifically; Can the width of the data wire 109 in the zone of all overlappings between the data wire 109 of array base palte and the controlling grid scan line 103 be diminished to identical width; Also can the width of the data wire 109 in the zone of all overlappings between the data wire 109 of array base palte and the controlling grid scan line 103 be diminished to different widths; In addition; The transitional region of the part that the part that width is little in data wire 109 in passivation layer 110 and width are big can be provided with one or more second via hole 113 respectively; It is also inequality so just can to reach the parasitic capacitance that the data wire correspondence of different in width reduces, and the technical staff can do different adjustment according to actual needs, to reach optimum efficiency.
In such scheme; The width of the pixel electrode material of top deposition that can data wire 109 narrowed areas is set to be equal to or less than the width of data wire 109 narrowed areas; The width of pixel electrode material that is preferably the top deposition of data wire 109 narrowed areas is set to equal the width of data wire 109 narrowed areas; Can reduce this regional resistance to greatest extent this moment under the certain situation of data wire 109 narrowed areas width, improve display effect.
Correspondingly, a kind of manufacturing approach of array base palte has been proposed also here, as shown in Figure 3, for making the method flow diagram of this array base palte, specifically comprise:
Shown in Fig. 4 a; The plan structure figure of the array base palte after forming gate electrode 102, controlling grid scan line 103 and storage capacitor electrode 104 on the glass substrate that proposes for the utility model embodiment, Fig. 4 b are to the plan structure figure of the array base palte shown in Fig. 4 a sectional view along A-A ' line drawing.
The grid metallic film that wherein covers on the glass substrate 101 can but be not limited to the monofilm of AlNd, Al, Cu, Mo, MoW or Cr, perhaps be one of AlNd, Al, Cu, Mo, MoW or Cr or composite membrane that combination in any constituted.
Shown in Fig. 5 a, be the array base palte plan structure figure that insulating barrier is set that the utility model embodiment proposes, Fig. 5 b is to the sectional view of the array base palte plan structure figure shown in Fig. 5 a along A-A ' line drawing.On the glass substrate 101 based on pattern that is formed with gate electrode 102, controlling grid scan line 103 after step 31 processing and storage capacitor electrode 104; Deposition active layer 106 and insulating barrier 105; And source electrode 107, drain electrode 108 and data wire 109 be set on insulating barrier 105; One end of source electrode 107 is positioned at the top of the gate electrode 102 on the glass substrate 101, and the other end contacts with data wire 109, and an end of drain electrode 108 is positioned at gate electrode 102 tops on the glass substrate 101; Be oppositely arranged with source electrode 107, the raceway groove between source electrode 107 and the drain electrode 108 exposes active layer 106.And the zone that between data wire 109 and controlling grid scan line 103, overlaps through composition technology, with 1/3rd of data wire 109 width in the zone of non-overlapping between reduced width to the data wire 109 of data wire 109 and the controlling grid scan line 103.
Wherein, The metallic diaphragm of covering grid electrode 102 and controlling grid scan line 103, insulating barrier 105 can but be not limited to the monofilm of SiNx, SiOx or SiOxNy; Perhaps be one of SiNx, SiOx or SiOxNy or composite membrane that combination in any constituted; Source electrode 107 on the insulating barrier 105 and the metallic diaphragm of drain electrode 108 can but be not limited to the monofilm of Mo, MoW or Cr, perhaps constituted composite membrane by one of Mo, MoW or Cr or combination in any.
Shown in Fig. 6 a; The array base palte plan structure figure of the covering passivation layer 110 that proposes for the utility model embodiment; Fig. 6 b is to the sectional view of the array base palte plan structure figure shown in Fig. 6 a along A-A ' line drawing; Several first via holes are set on passivation layer, the shape of first via hole can but be not limited to circle, diameter is advisable with the width that is no more than data wire 109.For example at first via hole 112 that is provided with near 108 1 sides of the drain electrode on the insulating barrier 105 on the passivation layer 110.Above-mentionedly in addition describe; The narrowed width of data wire 109 in the more non-overlapping region of width of data wire 109 in the zone that between data wire 109 and controlling grid scan line 103, overlaps; Then here on passivation layer 110, be in data wire 109 width and narrow down or by second via hole 113 is set respectively in the narrow transitional region that broadens by wide.Wherein, form passivation layer 110 metal film can but be not limited to the PVX film.
Said pixel electrode material can but be not limited to the monofilm of ITO, IZO, perhaps be composite membrane that ITO, IZO constituted.
Particularly, above-mentioned described composition technology includes but not limited to be technologies such as photoresist coating, mask, exposure, etching.
Correspondingly; The utility model embodiment has also proposed a kind of liquid crystal panel that uses the array base palte that proposes among the utility model embodiment to make, and the liquid crystal panel of promptly making based on the new array base palte of the above-mentioned proposition of the utility model is also within the protection range of the utility model.
The utility model also provides a kind of display device, has used above-mentioned liquid crystal panel.Said display device can be LCD TV, notebook computer, mobile phone, panel computer etc.
Obviously, those skilled in the art can carry out various changes and modification to the utility model and not break away from the spirit and the scope of the utility model.Like this, belong within the scope of the utility model claim and equivalent technologies thereof if these of the utility model are revised with modification, then the utility model also is intended to comprise these changes and modification interior.
Claims (10)
1. an array base palte comprises data wire and controlling grid scan line, has overlapping region between said data wire and the controlling grid scan line, is coated with passivation layer on the said data wire, it is characterized in that:
The width of said data wire at least one zone that overlaps with controlling grid scan line, with the non-overlapping of controlling grid scan line regional in narrow width;
The transitional region that changes at data wire width on the said passivation layer is respectively arranged with at least one via hole; The top of data wire narrowed areas deposits the pixel electrode material, and said pixel electrode material is through said via hole and data wire conducting.
2. array base palte as claimed in claim 1 is characterized in that, the width of said data wire at least one zone that overlaps with controlling grid scan line, be with the non-overlapping of controlling grid scan line regional in width 1/3rd.
3. array base palte as claimed in claim 1 is characterized in that, the width of said data wire in each zone that overlaps with controlling grid scan line, with the non-overlapping of controlling grid scan line regional in narrow width.
4. array base palte as claimed in claim 1 is characterized in that, the part of said data wire at least one zone that overlaps with controlling grid scan line be shaped as rectangle, round rectangle or arc.
5. array base palte as claimed in claim 1 is characterized in that, the transitional region that changes at data wire width on the said passivation layer is respectively arranged with a via hole.
6. like each described array base palte of claim 1～5, it is characterized in that said via hole is circle, triangle or square.
7. like each described array base palte of claim 1～5, it is characterized in that the width of the pixel electrode material of the top deposition of data wire narrowed areas is equal to or less than the width of data wire narrowed areas.
8. like each described array base palte of claim 1～5, it is characterized in that said pixel electrode is the monofilm of indium tin metal oxide ITO or zirconium tin metal oxide IZO, perhaps is the composite membrane that ITO and IZO constituted.
9. a liquid crystal panel is characterized in that, comprises each described array base palte of claim 1～8.
10. a display device is characterized in that, comprises the described liquid crystal panel of claim 9.
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| CN201120288922U CN202142534U (en) | 2011-08-10 | 2011-08-10 | Array baseplate, liquid crystal display panel and display device |
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| CN201120288922U CN202142534U (en) | 2011-08-10 | 2011-08-10 | Array baseplate, liquid crystal display panel and display device |
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| CN105760584A (en) * | 2016-02-01 | 2016-07-13 | 浪潮(北京)电子信息产业有限公司 | Internal wiring method and system for chip |
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| CN106932979A (en) * | 2015-12-31 | 2017-07-07 | 乐金显示有限公司 | Array base palte and the display device including it |
| CN108873526A (en) * | 2018-07-19 | 2018-11-23 | 京东方科技集团股份有限公司 | Array substrate and its manufacturing method, display device |
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| CN106154648A (en) * | 2015-03-24 | 2016-11-23 | 群创光电股份有限公司 | Display floater |
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| CN106932979A (en) * | 2015-12-31 | 2017-07-07 | 乐金显示有限公司 | Array base palte and the display device including it |
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| CN106483726A (en) * | 2016-12-21 | 2017-03-08 | 昆山龙腾光电有限公司 | Thin-film transistor array base-plate and preparation method and display panels |
| CN109427821A (en) * | 2017-08-17 | 2019-03-05 | 电子部品研究院 | Display panel and its manufacturing method with reduced parasitic capacitance |
| CN110082973A (en) * | 2018-01-26 | 2019-08-02 | 电子部品研究院 | The display panel and its manufacturing method that parasitic capacitance reduces |
| CN108873526A (en) * | 2018-07-19 | 2018-11-23 | 京东方科技集团股份有限公司 | Array substrate and its manufacturing method, display device |
| CN109407433A (en) * | 2018-11-14 | 2019-03-01 | 惠科股份有限公司 | Array substrate and display panel |
| WO2020097960A1 (en) * | 2018-11-14 | 2020-05-22 | 惠科股份有限公司 | Array substrate and display panel |
| CN109407433B (en) * | 2018-11-14 | 2021-04-02 | 惠科股份有限公司 | Array substrate and display panel |
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| CN111681549A (en) * | 2020-06-16 | 2020-09-18 | 昆山国显光电有限公司 | Array substrate and display panel |
| CN111681549B (en) * | 2020-06-16 | 2022-03-18 | 昆山国显光电有限公司 | Array substrate and display panel |
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