CN202110462U - LDO based on dynamic zero-pole tracking techniques - Google Patents

Abstract

The utility model belongs to the field of power source management and discloses an LDO (Low Dropout Regulator) based on dynamic zero-pole tracking techniques, aiming to solve the problem that the conventional LDO has poor loop stability. The LDO comprises an error amplifier, a buffer, and a slew rate intensifier circuit, and is characterized by further comprising a first capacitor, a second capacitor, and a variable resistor, wherein one end of the first capacitor is connected with the output end of the error amplifier, and the other end of the first capacitor is connected with one end of the variable resistor; and one end of the second capacitor is connected with the error amplifier, and the other end of the second capacitor is connected with the other end of the variable resistor, and serves as the output end of the LDO. In the LDO provided by the utility model, the first capacitor and the variable resistor form a compensating network to serve as the dynamic zero-pole of the system; and through adopting the second capacitor in current multiplication mode to compensate the phase margin of the LDO loop, the stability of the LDO loop is improved further.

Description

A kind of LDO based on dynamically zero limit tracking technique

Technical field

The utility model belongs to field of power management, is specifically related to the design of a kind of low pressure difference linear voltage regulator (LDO, Low Dropout Regulator).

Background technology

Power management module is the basic element circuit of chip, and its design is hand-held particularly important with the portable equipment field.The low pressure difference linear voltage regulator of the outer electric capacity of no sheet is the typical linear stabilizator structure of current trend.Along with being widely used of current portable set, new demand has also been proposed for the performance of LDO: lower power consumption, promptly littler pressure reduction and lower quiescent current; Better transient response, promptly more excellent compensation way and topological structure.

Loop stability is the key index of LDO, the mode that traditional LDO adopts the ESR (Equivalent Series Resistance) on the output capacitance to repay.Because ESR receives environment easily, like temperature, the influence of technology etc. changes greatlyyer, and the stable output current that provides is limited in the not enough optimization that seems in the very little scope.The existence meeting of ESR worsens load instantaneous regulation (load transient regulation) when momentary load changes in addition.

Limit splitting technique and zero pole cancellation technology that multiple new topological sum compensation way: K.N.Leung proposes have appearred now; The STC technology that Man proposes based on FVF; Rincon-Mora propose based on the zero pole cancellation technology of Miller multiplication and the damping factor alignment technique (DFC) of K.N.Leung.But the zero pole cancellation technology that they all have certain limitation: Leung to propose is followed the tracks of the power tube that is operated in the saturation region by the sampling pipe that is operated in linear zone and is obtained load information, and it is accurate inadequately to follow the tracks of load; The STC technology is because topological structure restriction loop gain can not be very high, and the output voltage static accuracy is limited; The circuit of the Miller doubling technology that Rincon-Mora proposes is realized because its special process requires to have limited the application in standard CMOS process; The shortcoming that has loop complexity and big quiescent current based on the LDO compensation framework of DFC technology.

The utility model content

The purpose of the utility model is in order to solve the problem of existing LDO loop stability, to have proposed a kind of LDO based on dynamically zero limit tracking technique.

The technical scheme of the utility model is: a kind of LDO based on dynamically zero limit tracking technique comprises error amplifier, impact damper; Pendulum rate intensifier circuit, first electric capacity, second electric capacity and variable resistor, the output terminal of said error amplifier is connected with the input end of impact damper; The output terminal of impact damper is connected with the output terminal of pendulum rate intensifier circuit; One termination error amplifier output terminal of said first electric capacity, the other end is connected with a variable-resistance end, and an end of said second electric capacity is connected with error amplifier; The other end is connected with the variable-resistance other end, and as the output terminal of LDO.

Said error amplifier comprises PMOS pipe M1, M2, Mb1, M7, M8, and NMOS manages M3, M4, M5, the M6 pipe, wherein Mb1 is as tail current source; M1, M2 is as importing pipe; The M7 diode connects; The electric current of M8 mirror image M7 and as the load P pipe; M3, M4 diode connect as first order load; The electric current of M5 mirror image M3, the electric current of M6 mirror image M4, and the M6 pipe is managed as load N; M5 links to each other with the M7 drain electrode; M6 links to each other as the error amplifier output terminal with the M8 drain electrode.

Said impact damper comprises PMOS pipe Mb2, M9, and wherein, Mb2 is as the bias current pipe, and with device, the drain electrode of Mb2 is connected with the source electrode of M9 M9 as the source, and as the output terminal of impact damper; The grid of M9 is the input end of impact damper, grounded drain.

Said pendulum rate intensifier circuit comprises PMOS pipe Ms, M16, M15, NMOS pipe M13, M14, and wherein, the grid of M16 drain electrode and Ms connects the output terminal of impact damper, and source electrode connects the input voltage of LDO, and drain electrode connects the drain electrode of M14; The M14 diode connects; The electric current of M13 mirror image M14, drain electrode connects the drain electrode of M15.

Said variable resistor by NMOS manage M12, PMOS pipe M11, M10 forms, wherein, NMOS manages the electric current of M14 in the said pendulum rate of the M12 mirror image intensifier circuit; PMOS pipe M10 grid connects the drain electrode of NMOS pipe M12; PMOS pipe M11 diode connects, and drain electrode connects the drain electrode of NMOS pipe M12, and the source electrode of PMOS pipe M11 source electrode and M10 is connected, and as the output terminal of LDO.

The beneficial effect of the utility model: the LDO based on dynamically zero limit tracking technique of the utility model, form corrective network through first electric capacity and variable resistor, as the dynamic zero point of system; The phase margin of the second capacitance compensation LDO circuit loop through adopting the current multiplication pattern, thus the LDO loop stability improved.

Description of drawings

Fig. 1 is the LDO system chart based on dynamically zero limit tracking technique of the utility model.

Fig. 2 be the utility model based on the dynamic physical circuit synoptic diagram of the LDO of zero limit tracking technique.

Fig. 3 is the utility model current-mode capacitance multiplication synoptic diagram, and wherein, figure (a) is a circuit structure diagram, (b) is equivalent schematic.

Fig. 4 is a phase lead compensation network equivalence Organization Chart among the utility model embodiment.

Embodiment

Below in conjunction with accompanying drawing and concrete embodiment the utility model is done further to set forth.

The utility model LDO collocation structure thought is following: error amplifier adopts the OTA of one pole symmetrical structure; Impact damper is realized with the pmos source follower; Increase is to the driving force of PMOS adjustment pipe, and frequency compensation adopts miller electric capacity and the dynamic method that zero point, (variable MOS resistance+fixed capacity) combined.For improving the transient response of LDO when the load changing, increased the Slew Rate intensifier circuit.

Fig. 1 is based on the dynamically system block diagram of the LDO of zero limit tracking technique, comprises error amplifier Gain Stage, impact damper Buffer, pendulum rate intensifier circuit SRE, first capacitor C _c, second capacitor C _mWith variable resistor R _c, the output terminal of said error amplifier Gain Stage is connected with the input end of impact damper Buffer, and the output terminal of impact damper Buffer is connected with the output terminal of pendulum rate intensifier circuit SRE, said first capacitor C _cA termination error amplifier Gain Stage output terminal, the other end and variable resistor R _cAn end be connected said second capacitor C _mAn end be connected the other end and variable resistor R with error amplifier Gain Stage _cThe other end be connected, and as the output terminal of LDO.

Fig. 2 is the physical circuit synoptic diagram of described LDO.Error amplifier Gain Stage comprises PMOS pipe M1, M2, Mb1, M7, M8, and NMOS manages M3, M4, M5, M6, wherein Mb1 is as tail current source; M1, M2 is as importing pipe; The M7 diode connects; The electric current of M8 mirror image M7 and as the load P pipe; M3, the equal diode of M4 connects as first order load; The electric current of M5 mirror image M3, the electric current of M6 mirror image M4, and the M6 pipe is managed as load N; M5 links to each other with the M7 drain electrode; M6 links to each other as the output terminal of error amplifier with the M8 drain electrode.

Impact damper Buffer comprises PMOS pipe Mb2, M9, and wherein, Mb2 is as the bias current pipe, and with device, the drain electrode of Mb2 is connected with the source electrode of M9 M9 as the source, and as the output terminal of impact damper Buffer; The grid of M9 is the input end of impact damper Buffer, grounded drain.

Pendulum rate intensifier circuit SRE comprises PMOS pipe Ms, M16, M15, NMOS pipe M13, M14, and wherein, the grid of M16 drain electrode and Ms connects the output terminal of Buffer together, and source electrode connects the input voltage of LDO, and drain electrode connects the drain electrode of M14; The M14 diode connects; The electric current of M13 mirror image M14, drain electrode connect the drain electrode of the M15 of diode connection.The electric current of M16 pipe mirror image M15.

Variable resistor Rc by NMOS manage M12, PMOS pipe M11, M10 forms, wherein, NMOS manages the electric current of M14 in the said pendulum rate of the M12 mirror image intensifier circuit; PMOS pipe M11 diode connects, and drain electrode connects the drain electrode of NMOS pipe M12, and the source electrode of PMOS pipe M11 source electrode and M10 is connected, and as the output terminal of LDO; PMOS pipe M10 grid connects the drain electrode of NMOS pipe M12.

Here, the diode connection refers to the grid of metal-oxide-semiconductor and drains and directly links together.

The current-mode capacitance multiplication synoptic diagram that the utility model utilizes is as shown in Figure 3.Figure (a) is a circuit structure diagram, V _nThe small signal of end changes in first capacitor C _cOn electric current be V _nC _cS collects the small-signal current and the scaled mirror of the electric capacity of flowing through and amplifies through the low impedance points (1/gm) of current mirror, return input end V _nFigure (b) is an equivalent schematic, equivalent capacity C _Eq=(1+K _x) C _c, and then realized that the Miller of electric capacity doubles.

Among Fig. 1, second capacitor C _mAs the Miller multiplication capacitor of current-mode, R _cBe the MOS resistance that is operated in linear zone, comprises load information.First capacitor C _cWith variable resistor R _cBe connected across the output and the power tube output of EA gain stage, produce and follow the tracks of compensation output limit dynamic zero point.Buffer isolates big electric capacity and big resistance, and plays pendulum rate humidification.C _fWith feedback resistance R _F1, R _F2Form Hi-pass filter, it is a pair of zero extremely right to produce, thereby realizes that phase lead compensation improves loop stability.Pendulum rate intensifier circuit SRE can change the instantaneous charging current to power tube gate capacitance Cp according to load current condition.

Can know the stable state output voltage of LDO by Fig. 1:

$V_{\mathrm{Out}}=\frac{R_{f1}+R_{f2}}{R_{f1}}{V}_{\mathrm{Ref}}$ Formula (1)

System's loop transfer function:

$H_1\left(s\right)=\frac{H_1\left(0\right)(1+s/Z_1)(1+s/Z_2)}{(1+s/P_1)(1+s/P_2)(1+s/P_3)}$ Formula (2)

In the formula (2), the low frequency loop gain:

$H_1\left(0\right)=A_v{g}_{\mathrm{Mp}}[r_{\mathrm{Op}}//(R_{f1}+R_{f2})//R_L]\frac{R_{f1}}{R_{f1}+R_{f2}}$ Formula (3)

Zero limit is respectively:

$P_1=\frac{1}{(K_x{C}_m+C_c)g_{\mathrm{mp}}{r}_{\mathrm{op}}{R}_{\mathrm{oeq}}};$

$P_2=\frac{g_{\mathrm{Mb}}}{C_p};$ $P_3=\frac{g_{\mathrm{Mp}}}{C_L}$ Formula (4)

$Z_1\≈\frac{1}{R_{\mathrm{Ds}\_\mathrm{Mos}}{C}_c}=\frac{u_p{C}_{\mathrm{Ox}}{(W/L)}_1(V_{\mathrm{Gs}}-V_{\mathrm{Tp}})}{C_c}=\frac{u_p{C}_{\mathrm{Ox}}{(W/L)}_1}{C_c}\sqrt{\frac{2I_0{K}_1{K}_2}{u_p{C}_{\mathrm{Ox}}{(W/L)}_2}}$ Formula (5)

$Z_2=Z_f=\frac{1}{R_{f1}{C}_f}$ Formula (6)

Wherein, A _vBe the DC current gain of error amplifier, g _MpBe the mutual conductance of adjustment pipe Mp, r _OpBe the conducting resistance of adjustment pipe Mp, K _xBe the mirror image ratio of M3 and M5, g _MbBe the mutual conductance of Mb2, R _OeqBe the equivalent output resistance of error amplifier, μ _pBe the mobility in hole, C _OxBe the gate oxide electric capacity of unit area, W is the width of grid, and L is the length of grid, V _GsBe the voltage between the two poles of the earth, grid source, V _TpThreshold voltage for the PMOS pipe.

Z in the formula (5) ₁Be dynamic zero point, be used for following the tracks of the dynamic limit P of compensation output ₃, K wherein ₁, K ₂Sampling ratio for the load current sampling network; Z _fAt zero point within the gain band width product (GBW, Gain-Bandwidth product) of phase lead compensation network generation, be used for improving loop phase nargin.Corresponding P _fOutside GBW, do not give providing above, concrete analysis will provide below.Hence one can see that, and this LDO is an one-pole system, has good stability.

Fig. 4 phase lead compensation network equivalence Organization Chart, capacitor C _fWith the feedback network resistance R _F1, R _F2Form the high-pass filtering network, thereby improve system stability, and can improve transient response and PSRR, reduce output noise.Its transition function expression formula is following:

$H_2\left(s\right)=\frac{V_{\mathrm{Fb}}}{V_{\mathrm{Out}}}=\left(\frac{R_{f1}}{R_{f1}+R_{f2}}\right)\left[\frac{1+s{C}_f{R}_{f2}}{1+s{C}_f(R_{f1}//R_{f2})}\right]$ Formula (7)

$P_f=\frac{1}{(R_{f1}//R_{f2})C_f}=\frac{1+\frac{R_{f2}}{R_{f1}}}{R_{f2}{C}_f};$ $Z_f=\frac{1}{R_{f2}{C}_f}$ Formula (8)

Can draw from formula (8):

Be Z _fPf is in more low frequency relatively, with Z _fBe placed on a little less than near the GBW P _fOutside GBW, can the compensation loop frequency characteristic.But the separation pitch of zero limit is big more; It is big more to need

; The mismatch that has the layout of resistance on the one hand; What is more important; The noise of error amplifier input end and mismatch can be amplified to output terminal with bigger multiple; So the design of

exists compromise, gets

here

In Fig. 2, V _InBe unadjusted supply voltage, MB1, MB2, MB3 are the quiescent biasing pipes; M1～M8 is the error amplifier gain stage; M9 is a buffer stage; Load current sampling network Ms, M13, M14 sampled power tube current is to obtain load information; M10 is the MOS resistance that is operated in linear zone, its overdrive voltage (| V _Gs|-| V _Tp10|) comprise the information (like formula (5)) of load current, first capacitor C _cForm zero point with the resistance of M10, follow the tracks of compensation output limit; Second capacitor C _mUtilize the mirror image ratio of load current mirror M3, M5, realize the Miller capacitance multiplication of current-mode.C _cWith C _mEquivalence value at the error amplifier output terminal is (K _xC _m+ C _c) g _Mpr _Op

In order to improve loop GBW; Avoid the influence of parasitic poles; And the needs of current-mode Miller multiplication; The error amplifier of design is the trsanscondutance amplifier (OTA, Operational Transconductance Amplifier) of non-closed loop of the symmetry of one-pole system, except other nodes of output terminal are low-impedance node.Impact damper Buffer is a P type impact damper, and the prosposition that electrifies moves the effect with isolation buffer.Because the constant-current bias of Mb2 is Ib2 among the impact damper Buffer, make power tube Mp gate charges electric current is limited within the Ib2, but limited not the discharge current of power tube Mp grid.This just makes at V _OutWhen reducing suddenly, make the discharge current of power tube Mp grid increase.The design of low-power consumption makes that the quiescent bias current of Mb2 can not be very big, at V _OutWhen increasing suddenly, limited reconstituting the joint performance, this also is the inherent shortcoming of P type Buffer.The utility model adopts Slew Rate to strengthen network M15～M16 according to the charging current value of load state change to power tube grid parasitic capacitance, promotes transient state adjustment performance.

In addition, the taking all factors into consideration of effect that strengthens according to quiescent dissipation and pendulum rate and the MOS resistance compensation needs of M10, load current sampling network sampling ratio designs:

$K_1=\frac{{(W/L)}_{M_S}}{{(W/L)}_{M_P}}=1:1300,$ $K_2=\frac{M_{12}}{M_{14}}=1:8$

Therefore, in low loading range, the load information that M10 comprises possibly all be lower than noise signal.For this reason, Mb3 introduces one road bias current, in the dynamic limit variation range of output that is fixedly installed on dynamic zero point in the low loading range.

Can find out that the LDO based on dynamically zero limit tracking technique of the utility model forms corrective network through first electric capacity and variable resistor, as the dynamic zero point of system; The phase margin of the loop of the second capacitance compensation LDO through adopting the current multiplication pattern improves the loop stability of LDO.

Those of ordinary skill in the art will appreciate that embodiment described here is in order to help the principle of reader understanding's the utility model, should to be understood that the protection domain of the utility model is not limited to such special statement and embodiment.Those of ordinary skill in the art can make various other various concrete distortion and combinations that do not break away from the utility model essence according to disclosed these teachings of the utility model, and these distortion and combination are still in the protection domain of the utility model.

Claims (5)

1. the LDO based on dynamically zero limit tracking technique comprises error amplifier, impact damper and pendulum rate intensifier circuit; It is characterized in that, also comprise first electric capacity, second electric capacity and variable resistor, the output terminal of said error amplifier is connected with the input end of impact damper; The output terminal of impact damper is connected with the output terminal of pendulum rate intensifier circuit; One termination error amplifier output terminal of said first electric capacity, the other end is connected with a variable-resistance end, and an end of said second electric capacity is connected with error amplifier; The other end is connected with the variable-resistance other end, and as the output terminal of LDO.

2. the LDO based on dynamically zero limit tracking technique according to claim 1 is characterized in that, said error amplifier comprises PMOS pipe M1, M2, Mb1, M7, M8, and NMOS manages M3, M4, M5, the M6P pipe, wherein Mb1 is as tail current source; M1, M2 is as importing pipe; The M7 diode connects; The electric current of M8 mirror image M7 and as the load P pipe; M3, the equal diode of M4 connects as first order load; The electric current of M5 mirror image M3, the electric current of M6 mirror image M4, and the M6 pipe is managed as load N; M5 links to each other with the M7 drain electrode; M6 links to each other as the output terminal of said error amplifier with the M8 drain electrode.

3. the LDO based on dynamically zero limit tracking technique according to claim 1 is characterized in that, said impact damper comprises PMOS pipe Mb2, M9; Wherein, Mb2 is as the bias current pipe, M9 as the source with device; The drain electrode of Mb2 is connected with the source electrode of M9, and as the output terminal of impact damper; The grid of M9 is the input end of impact damper, grounded drain.

4. the LDO based on dynamically zero limit tracking technique according to claim 1; It is characterized in that said pendulum rate intensifier circuit comprises PMOS pipe Ms, M16, M15, NMOS pipe M13, M14; Wherein, The grid of M16 drain electrode and Ms connects the output terminal of impact damper, and source electrode connects the input voltage of LDO, and drain electrode connects the drain electrode of M14; The M14 diode connects; The electric current of M13 mirror image M14, drain electrode connects the drain electrode of M15.

5. according to claim 4ly it is characterized in that based on the dynamic LDO of zero limit tracking technique that said variable resistor is managed M12, PMOS pipe M11, M10 by NMOS and formed, wherein, NMOS manages the electric current of M14 in the said pendulum rate of the M12 mirror image intensifier circuit; PMOS pipe M10 grid connects the drain electrode of NMOS pipe M12; PMOS pipe M11 diode connects, and drain electrode connects the drain electrode of NMOS pipe M12, and the source electrode of PMOS pipe M11 source electrode and M10 is connected, and as the output terminal of said LDO.

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