CN202075970U - VGA display drive controller based on FPGA system - Google Patents

Abstract

The utility model discloses a VGA (Video Graphic Array) display drive controller based on an FPGA (Field-Programmable Gate Array) system. The VGA display drive controller comprises a CPU (Central Processing Unit) main control unit and a three-channel 8-bit high-speed video DAC (Digital-to-Analog Converter), wherein the CPU main control unit sends an instruction or data to an FPGA logic control unit. After the FPGA logic control unit analyzes the instruction or data, graphic data of an SDRAM (Synchronous Dynamic Random Access Memory) video memory unit is converted into a VGA signal through the three-channel 8-bit high-speed video DAC, and then the VGA signal is outputted to a VGA display for display. The VGA display drive controller supports more display resolution ratios, such as VGA (640*480), SVGA (Super Video Graphics Array) (800*600) and XGA (Extended Graphics Array) (1024*768); an external high-capacity SDRAM is adopted to provide 16/24 bit true color display; a perfect read-write arbitration mechanism is adopted to prevent the VGA screen from vibration caused by SDRAM read/write conflicts; and the VGA display drive controller provided by the utility model is low in cost.

Description

VGA display driver controller based on the FPGA system

Technical field

The utility model belongs to embedded display system, a kind of VGA equipment display technique that is applicable to of specific design.

Background technology

VGA (Video Graphics Array) is the computer display standard of using simulating signal that IBM Corporation proposed in 1987, this standard is of little use for PC market now, but in a lot of resolution requirement is not very high occasion, for example real-time demonstration of the image information of embedded display system etc., VGA still has very big application market.Simultaneously VGA remains the common low side standard of supporting of institute of maximum manufacturers, PC before loading own unique driver, all necessary support VGA standard.For example the start-up picture of the Windows series of products of Microsoft still uses the VGA display mode.

General VGA display system mainly partly is made up of sequential control circuit, video memory control circuit, read-write arbitration control and cpu i/f control etc.Control circuit is mainly finished functions such as sequential generation, video memory data manipulation, major clock selection and D/A conversion; Video memory then provides the video data spatial cache; Cpu i/f control by the visit video memory, can be implemented to the content map of VGA screen as display control program.

Along with the development of FPGA (Field-Programmable Gate Array) and the continuous decline of price thereof, the application advantage of FPGA manifests gradually.In Embedded System Design, in order to realize the VGA Presentation Function, both can use special-purpose VGA interface chip, also can use the soft nuclear of VGA interface IP based on FPGA.Though use the VGA special chip to have advantages such as more stable VGA sequential and more display modes, its cost height; And use the soft nuclear of VGA interface IP to have significant advantages such as flexible design, integrated level height, system cost be low, but its function singleness, display mode is few.

Summary of the invention

The purpose of this utility model is to overcome above-mentioned VGA special chip cost height, and the soft nuclear of common VGA IP can't satisfy the shortcoming of plurality of display modes, and a kind of VGA display driver controller based on the FPGA system is provided.

The technical solution of the utility model is: based on the VGA display driver controller of FPGA system, it comprises the CPU main control unit, 8 high-speed video DAC of triple channel, described CPU control module sends order or data arrive the fpga logic control module, after fpga logic control module resolve command or the data, with the graph data of SDRAM video memory unit, after 8 high-speed video DAC of triple channel are transformed into the VGA signal, output to the VGA display and show again.

Described fpga logic control module comprises:

The GenericPort logic module; With the system control cpu physical connection, be used to resolve order and the read-write control that system control cpu writes;

PLLs control module: be used to control the various efficient clocks under the different display resolutions;

Arbitrated logic module: be used for coordinating to finish cpu i/f and the VGA timing sequencer is visited SDRAM;

Asynchronous FIFO module: be used to coordinate system control cpu by GenericPort access sdram video memory unit and SDRAM Logic control module access sdram video memory unit;

SDRAM Logic control module: be used for the control of SDRAM video memory unit;

The VGA time-sequence control module: the row, the field sync signal that produce various standard formats are exported;

The register assembly.

The coordination of described asynchronous FIFO module is: when FIFO writes when full, fifo control logic produces writes full signal, fpga logic control module and then produce the wait signal, and the notice system control cpu suspends writing of data, to avoid loss of data; When FIFO read sky, fifo control logic produces read spacing wave, fpga logic control module and then generation wait disablement signal, and the notice system control cpu can write data the dual-ported memory of FIFO.

The coordination of described arbitrated logic module is: the timesharing read-write of control SDRAM video memory unit, and to read SDRAM video memory operator precedence.

The described SDRAM of reading video memory operator precedence is to have adopted VGA to refresh the privilege of access pattern, and the CPU visit only is in the interruption cycle that VGA refreshes.

When system works when pattern (ConfigMode) is set, system control cpu is finished the relevant parameters setting by the internal register of parallel bus read-write fpga logic control module.System control cpu by the asynchronous FIFO module, through the SDRAM Logic control module, writes image B itMatrix data in plug-in SDRAM video memory unit under the GenericPort pattern simultaneously.When system works when screen display mode (DisplayMode), the VGA time-sequence control module is through the SDRAM logic control element, access sdram video memory unit, read Pixel Information, again after 8 high-speed video DAC of triple channel are transformed into the VGA signal, cooperate row, field sync signal, output to the VGA display and show.

The more display resolution of the utility model support, as: VGA (640 * 480), SVGA (800 * 600), XGA (1024 * 768); Adopt plug-in high capacity SDRAM, provide 16/24 true colour display screen to show; Adopt perfect read-write arbitration mechanism, the VGA screen shake of having avoided the SDRAM read/write conflict to cause; Its cost is low.

Description of drawings

Fig. 1 is the theory diagram of the utility model based on the VGA display driver controller of FPGA system.

Fig. 2 is the theory diagram of SDRAM Logic control module of the present utility model.

Fig. 3 is the theory diagram of asynchronous FIFO module of the present utility model.

Embodiment

As shown in Figure 1, CPU control module 200 sends order or data arrive fpga logic control module 100, after fpga logic control module 100 resolve command or the data, again with the graph data of SDRAM video memory unit 300, after 8 high-speed video DAC400 of triple channel are transformed into the VGA signal, output to VGA display 500 and show.

Fpga logic control module 100 as shown in Figure 1,

1, the GenericPort logic module 110:

GenericPort logic module 110 is by 16 bit parallel data buss, 23 bit address buses and other read-write control signal, with the system control cpu physical connection, and go out relevant register address, register data, video memory data fifo register, video memory address fifo register and corresponding read-write control, and then control of definite subsequent module and relevant parameter read-write according to the command analysis that system control cpu writes.

2, PLLs control module

PLLs control module 120 belongs to the infinite loop work system, stateless machine structure.Based on PLL resource in the dirigibility of FPGA, particularly sheet, the dot frequency of the resolution such as VGA, SVGA, XGA that can provide support.Very high to frequency requirement because of the demonstration of VGA resolution, according to international standard, the best dominant frequency under different field frequencies such as VGA, SVGA is 180MHz, is the FPGA dominant frequency.It is dominant frequency clock source that system adopts the 48MHz clock of outside input, reaches the 180MHz clock after PLL is by 15/4 frequency multiplication, obtains various efficient clocks under the different display resolutions by frequency divider then.Other considers the power consumption of semiconductor product, we take separately to enable control for each frequency divider, and different clocks offers function register pack module in the fpga logic control module, arbitrated logic module, SDRAM Logic control module, VGA time-sequence control module etc. respectively.

3, the arbitrated logic module 130

It is to finish the coordination to the SDRAM visit of cpu i/f and VGA timing sequencer, because SDRAM video memory bus has only one group, CPU is when visiting it by asynchronous FIFO, keeping of VGA time-sequence control module refreshes also in high speed access SDRAM video memory bus, so just have the problem of seizing of video memory bus, the arbitrated logic module need make the award.Because the CPU write operation belongs to random occurrence, the request of VGA refresh data then belongs to measurable incident and has periodically, so adopted VGA to refresh the privilege of access pattern here, be that the CPU visit only is in the interruption cycle that VGA refreshes: row field blanking, a row front and back shoulder etc., under this low priority situation, CPU visit meeting is periodically interrupted, need to the special two-way asynchronous FIFO of big degree of depth address/data (First In First Out) that adds of CPU visit for this reason, so just can exchange the significantly raising of bus access efficient for less resource consumption.

4, the asynchronous FIFO module 140

Have lot of data need carry out cross clock domain transmission and to the data transmission rate request than higher occasion, Asynchronous FIFOBe a kind of simply, solution efficiently.Asynchronous FIFO writes data with a kind of clock, then uses another clock sense data, and the transition activities of read-write pointer is by different clock generating.

Because system control cpu does not match by the speed of GenericPort access sdram video memory unit and the speed of SDRAM Logic control module access sdram video memory unit, and clock is also inequality, for fear of conflict, we add the asynchronous FIFO buffer module here and coordinate.The data of GenericPort visit are divided into data and SDRAM address, therefore need two asynchronous FIFOs to cushion and finish, and we are set to: the data FIFO bit wide is 16bit, and the degree of depth is 1000; Address FIFO bit wide is 23bit, and the degree of depth is 1000.

The theory diagram of asynchronous FIFO module of the present utility model is seen Fig. 3.When FIFO writes when full, fifo control logic produces writes full signal, fpga logic control module and then produce the wait signal, and the notice system control cpu suspends writing of data, to avoid loss of data; When FIFO read sky, fifo control logic produces read spacing wave, fpga logic control module and then generation wait disablement signal, and the notice system control cpu can write data the dual-ported memory of FIFO.

5, the SDRAM Logic control module 150

Control register module 151:

The control register module comprises the various registers of Control work pattern.System can dispose the mode of operation of SDRAM according to actual needs, and mode of operation can dispose by cpu i/f, also can save cpu i/f and disposes by parameter preset.Register mainly comprises two classes: the one, and the initialize mode control register is used to control the producing method that the SDRAM initialization directive is flowed; The 2nd, SDRAM pattern control register is used for refreshing and other operational order parameter control of SDRAM;

Initialization requests generation module 152

After system powered on, the generation of initialization request signal need postpone control.Behind 100us～200us, clock could be stablized because system powers on, and SDRAM just can begin initialization operation then.For preventing to decipher the appearance of burr, adopt gray code counter to realize the control of this delay.After system reset finishes, the enabling counting device, when the counter meter after the value of setting, count value keeps, decoding simultaneously produces initialized request signal, after the SDRAM initialization was finished, it is invalid that request becomes;

Refresh requests generation module 153

The refresh requests generation module, the refresh request signal that can produce SDRAM according to the frequency of mode register configuration.This part circuit also is to adopt gray code counter to realize.The counter meter produces refresh request signal after the value of setting, turn back to initial value simultaneously and continue counting;

Instruction moderator module 154

Instruction moderator module is carried out priority arbitration to the read-write requests of initialization requests, refresh requests and system, produces initialization response initial*hold, refresh response ref*hold and read-write response sdram*wr*hold.Initialization operation only carries out once when powering on, and it is the basis of SDRAM operate as normal, so its priority is the highest, the priority of refresh requests is inferior high, and the priority of read-write requests is minimum.When carrying out, a certain operation can not respond request afterwards;

Command decoder module 155

The command decoder module is according to the result of instruction moderator, and the sdram controller mode register deciphers initialization directive, refreshing instruction, read write command respectively the setting of mode of operation parameter, and the result of decoding is exactly the steering order word of output.When initial*hold=1, decoding produces the initialization directive stream of SDRAM; When ref*hold=1, decoding produces refreshing instruction; As sdram*wr*hold=1 and read effectively (Sdram*rd*n=0) or when imitating (Sdram*wr*n=0), according to the order parameter decoding output BANK activation instruction of register setting, read instruction and the preliminary filling instruction.In addition, when SDRAM carries out any operation, all indicate SDRAM busy with sdram*busy=1; Indicate the SDRAM free time with sdram*busy=0.With the sdram*ready=1 indication mechanism to the effective read-write operation of SDRAM data.

Data path module 156.

6, the VGA time-sequence control module 160

With XGA is example, the VGA time-sequence control module utilizes the major clock of the 65MHZ behind the FPGA internal clocking frequency multiplication of phase locked loop, produce row, the field sync signal of standard x GA form, be expert at simultaneously, reference signal all produces a signal effectively the time and gives the output buffer module, as the enable signal of reading of output buffering.According to the VESA standard, the pixel clock that resolution is 1024 * 768, frame frequency is the standard x GA signal of 60HZ is 65MHZ, be equivalent to 1024 pixel clock cycles the effective time of line synchronizing signal, unit synchronous head width is equivalent to 136 pixel clock cycles, front porch width is for being equivalent to 26 pixel clock cycles, and the back porch width is for being equivalent to 162 pixel clock cycles.Be equivalent to 768 line period length the effective time of field sync signal, synchronous head is 6 line period length, and crop is 3 line period length, and back porch is 29 line period length.According to this standard, when row, a reference signal are all effective, exportable 1024 * 768 valid data of piece image.

7, the register assembly 170.

In sum, the utility model has fully been used the characteristic of the fast parallel deal with data of FPGA, each functional module closely cooperates, solved the problem that the embedded system realtime graphic shows, system reliability and design flexibility have been increased simultaneously, and significantly reduced the circuit board size, saved cost, expanded range of application.

Claims (1)

1. VGA display driver controller based on the FPGA system, it comprises the CPU main control unit, 8 high-speed video DAC of triple channel, it is characterized in that described CPU control module sends order or data arrive the fpga logic control module, after fpga logic control module resolve command or the data, with the graph data of SDRAM video memory unit, after 8 high-speed video DAC of triple channel are transformed into the VGA signal, output to the VGA display and show again.

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