CN201732104U - Testing plug board - Google Patents
Testing plug board Download PDFInfo
- Publication number
- CN201732104U CN201732104U CN201020246460XU CN201020246460U CN201732104U CN 201732104 U CN201732104 U CN 201732104U CN 201020246460X U CN201020246460X U CN 201020246460XU CN 201020246460 U CN201020246460 U CN 201020246460U CN 201732104 U CN201732104 U CN 201732104U
- Authority
- CN
- China
- Prior art keywords
- plate
- golden finger
- pcb
- printed circuit
- circuit board
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
Images
Landscapes
- Testing Of Individual Semiconductor Devices (AREA)
- Tests Of Electronic Circuits (AREA)
Abstract
The utility model relates to a testing plug board which comprises a printed circuit board (PCB), the surface of which is provided with a plurality of plug board connectors and a plurality of golden fingers; the number of the plug board connectors is the same as that of the golden fingers; each plug board connector is provided with one golden finger which is correspondingly and electrically connected; the plug board connectors are connected with an external standard socket; and the golden fingers are connected with an external DUT plate. The testing plug board leads the specific DUT plate to be matched with multiple sockets for use, thus effectively utilizing the resource, shortening the package reliability evaluation period of an integrated circuit, and reducing the evaluation cost.
Description
Technical field
The utility model relates to integrated circuit packaging and testing field, relates in particular to a kind of test plate (scrambleboard).
Background technology
To carry out failtests after the integrated circuit encapsulation, to reject substandard product, for example, burn test b I (burn in), initial failure level estimate EFR (early fail rate), high-temperature operation lifetime test HTOL (high temperature operating life) and low-temperature operation lifetime test LTOL (lowtemperature operating life) are exactly requisite test event in integrated circuit encapsulation (package IC) failtests.
During test, testing sample (i.e. integrated circuit after the encapsulation) is inserted on the test socket plate (being the DUT plate) by socket (socket) earlier, is connected on the ATE (automatic test equipment) by described DUT plate again.
The packaged type of integrated circuit has a variety of, for example, and dip DIP, thin compact package TSOP, BGA Package BGA, plastics dip PDIP, bump chip encapsulation BCC and the encapsulation of falling.Different integrated circuit encapsulation are because the packaged type difference, the electric connection mode that forms with ATE (automatic test equipment) during test is also different, so, different integrated circuit encapsulation need the different DUT plate of Design and Machining, at present, the DUT plate that uses in the experiment of integrated circuit package reliability has TSOP I-48, TSOP II-54, CABGA-144, TSOP II-66, PDIP-48, BCC-84 and DIM-72 etc.
In the prior art, different integrated circuit is packaged with different DUT plates and matches, test the reliability of newly-designed integrated circuit encapsulation, will design new DUT plate matches, therefore, when reliability assessment is done in the new integrated circuit encapsulation that the client is provided, want earlier Design and Machining DUT plate, like this, prolonged the assessment cycle of whole integrated circuit encapsulation, in addition, this DUT plate may no longer be used (not matching with other integrated circuit encapsulation) after assessment finished, this causes the bigger wasting of resources, and the price of a DUT plate is about 10,000 dollars (comprising design charges and processing charges), makes that the cost of integrated circuit encapsulation assessment is higher.
The utility model content
The purpose of this utility model is to provide a kind of test plate, this test plate is as the be connected bridge of integrated circuit encapsulation with the DUT plate, a DUT plate can be complementary with multiple different integrated circuit encapsulation, when reliability assessment is done in new integrated circuit encapsulation, save the step of the new DUT plate of Design and Machining, shorten integrated circuit package reliability assessment cycle, effectively utilized existing resource, reduced assessed cost.
To achieve the above object, the utility model provides a kind of test plate, comprises a printed circuit board (PCB), and the surface of described printed circuit board (PCB) is provided with a plurality of plate connectors and a plurality of golden finger; The quantity of described plate connector equates that with the quantity of described golden finger each described plate connector has the corresponding golden finger that is electrically connected; Described plate connector is connected with the external perimysium reference socket; Described golden finger is connected with outside DUT plate.
Above-mentioned test plate, wherein, described golden finger is arranged on the edge of described printed circuit board (PCB).
Above-mentioned test plate, wherein, described a plurality of golden finger is evenly distributed on the first surface and second surface of described printed circuit board (PCB), and the golden finger on golden finger on the described printed circuit board (PCB) second surface and the described printed circuit board (PCB) first surface is distributed in respectively on described second surface and the first surface correspondingly.
Above-mentioned test plate, wherein, described golden finger equidistantly distributes.
Above-mentioned test plate, wherein, the central authorities that described printed circuit board (PCB) is provided with the edge of golden finger are provided with window, and described golden finger is evenly distributed in the both sides of described window.
Above-mentioned test plate, wherein, in the same side of described window, described golden finger equidistantly distributes.
Above-mentioned test plate, wherein, described a plurality of plate connectors are by the centre of array distribution at described printed circuit board (PCB).
Above-mentioned test plate, wherein, in delegation and/or same row, described golden finger equidistantly distributes.
The pin coupling of the golden finger of test plate of the present utility model and specific DUT plate, the plate connector of test plate mates with the pin of multiple standard socket commonly used, make that this specific DUT plate can be used with multiple socket, when reliability assessment is done in new integrated circuit encapsulation, save the step of the new DUT plate of Design and Machining, shorten integrated circuit package reliability assessment cycle, effectively utilized existing resource, reduced assessed cost.
Description of drawings
Test plate of the present utility model is provided by following embodiment and accompanying drawing.
Fig. 1 is the vertical view of DIM-72 DUT plate.
Fig. 2 is the structural representation of the utility model test plate embodiment one.
Fig. 3 is the synoptic diagram that the utility model test plate and DUT plate coupling are used.
Fig. 4 is that the utility model test plate embodiment one mates the synoptic diagram that uses with the TSOP66 socket.
Fig. 5 is that the utility model test plate embodiment one mates the synoptic diagram that uses with the DIP48 socket.
Fig. 6 is the structural representation of the utility model test plate embodiment two.
Embodiment
Below with reference to Fig. 1～Fig. 6 test plate of the present utility model is described in further detail.
Test plate of the present utility model comprises a printed circuit board (PCB), and the surface of described printed circuit board (PCB) is provided with a plurality of plate connectors and a plurality of golden finger;
The quantity of described plate connector equates that with the quantity of described golden finger each described plate connector is electrically connected with a golden finger;
Described plate connector is connected with the external perimysium reference socket;
Described golden finger is connected with outside DUT plate.
Embodiment one:
In the present embodiment, the test plate is based on the DIM-72DUT plate, as shown in Figure 1, described DIM-72DUT plate 100 is dual inline type template (dual in-line module), this DIM-72DUT plate 100 is provided with a plurality of slots 101, and each slot 101 is provided with 72 pins (pins), in the prior art, 100 of this DIM-72DUT plates are applicable to the dual in line integrated circuit encapsulation, and the number of pins of this integrated circuit encapsulation should be smaller or equal to 72.
Referring to Fig. 2, the test plate of present embodiment comprises a printing board PCB (printed circuitboard) 200, is provided with a plurality of plate connectors 201 and a plurality of golden finger (golden finger) 202 on the surface of this printed circuit board (PCB) 200;
The quantity of described plate connector 201 equates with the quantity of described golden finger 202, each described plate connector 201 is electrically connected with a golden finger 202 that (described plate connector 201 is embedded in the described printed circuit board (PCB) 200 with the coupling part of golden finger 202, therefore, not shown these coupling parts in Fig. 2);
Described plate connector 201 is the connector of described printed circuit board (PCB) 200 and socket;
Described golden finger 202 is the connector of described printed circuit board (PCB) 200 and DUT plate.
In the present embodiment, the plate connector of described test plate and the number of golden finger are based on a slot of DIM-72 DUT plate, be that the test plate of present embodiment is applicable to that number of pins is smaller or equal to 72 integrated circuit encapsulation (pins≤72, wherein pins represents the number of pins of integrated circuit encapsulation);
Please continue referring to Fig. 2, the surface of the printed circuit board (PCB) 200 of present embodiment is provided with 72 plate connectors 201 and 72 golden fingers 202;
Described 72 golden fingers 202 are distributed on the first surface and second surface of described printed circuit board (PCB) 200, golden finger number on described printed circuit board (PCB) 200 first surfaces equals the golden finger number on described printed circuit board (PCB) 200 second surfaces, be on the first surface of described printed circuit board (PCB) 200 and the second surface 36 golden fingers 202 (for clear, only showing the part golden finger in Fig. 2) to be arranged respectively;
Spacing on described printed circuit board (PCB) 200 front surfaces between two golden fingers 202 equals on described printed circuit board (PCB) 200 second surfaces spacing between two golden fingers 202, and described spacing is 2.54mm (this spacing is got the industry standard spacing), i.e. d1=2.54mm;
Described golden finger 202 is arranged on the edge on described printed circuit board (PCB) 200 surfaces, and the golden finger 202 on golden finger on the second surface 202 and the first surface is distributed on second surface and the first surface correspondingly respectively;
When described printed circuit board (PCB) 200 inserted in the slot 101 of described DIM-72 DUT plate 100, described golden finger 202 was electrically connected with the pin of described slot 101;
Described golden finger 202 can be thin thin metal sheeting;
Described 72 plate connectors 201 are arranged on the centre on described printed circuit board (PCB) 200 surfaces, and these 72 plate connectors 201 are two parallel rows, and the number of every socket plate connector 201 equates, 36 plate connectors 201 of promptly every row;
Among the same row, the space D 1 between adjacent two plate connectors 201, D2, D3 equate that as shown in Figure 2, described spacing is 2.54mm, i.e. D1=D2=D3=2.54mm arbitrarily;
Described plate connector 201 can be the metal jack, and the pin of this metal jack and standard socket (socket) is complementary, and spacing L and standard socket between the two socket plate connectors 201 are complementary.
Referring to Fig. 3, the using method of the test plate of present embodiment is: the pin of standard socket is inserted described plate connector 201, the realization standard socket is electrically connected with described printed circuit board (PCB) 200, packaged integrated circuit 303 is inserted standard socket, the realization integrated circuit encapsulates be electrically connected (just the realizing the electrical connection of integrated circuit packaging and testing plate) with standard socket, a side that described printed circuit board (PCB) 200 is provided with golden finger 202 is inserted in the slot 101 of described DIM-72 DUT plate 100, described golden finger 202 closely is connected with the pin of described slot 101, realizes being electrically connected of described printed circuit board (PCB) 200 and described DIM-72 DUT plate 100 (just realizing being electrically connected of integrated circuit encapsulation and described DIM-72 DUT plate 100).
As shown in Figure 4, the standard socket that inserts described plate connector 201 is a TSOP66 socket 301, this TSOP66 socket 301 is applicable to the TSOP66 type integrated circuit encapsulation of adopting thin compact package mode, the number of pins of this TSOP66 socket 301 is 66, described 66 pins (not showing among Fig. 3) are divided into two rows, among the same row, spacing between adjacent two pins is 2.54mm, described TSOP66 socket 301 is provided with the metal wire 302 that is used to connect the integrated circuit encapsulation, the encapsulation of TSOP66 type integrated circuit snaps in this TSOP66 socket 301, the pin of described TSOP66 type integrated circuit encapsulation and 302 extruding of the metal wire of this TSOP66 socket 301 form closely connection.
As shown in Figure 5, the standard socket that inserts described plate connector 201 is a DIP48 socket 401, this DIP48 socket 401 is applicable to the DIP48 type integrated circuit encapsulation of adopting the dip mode, the number of pins of this DIP48 socket 401 is 48, described 48 pins (not showing among Fig. 4) are divided into two rows, among the same row, spacing between adjacent two pins is 2.54mm, described DIP48 socket 401 is provided with the metal jack 402 that is used to connect the integrated circuit encapsulation, the pin of DIP48 type integrated circuit encapsulation inserts in the described metal jack 402, and the encapsulation of realization DIP48 type integrated circuit is electrically connected with DIP48 socket 401.
This shows, use the test plate of present embodiment, DIM72 DUT plate 100 can use smaller or equal to 72 encapsulation of DIP type integrated circuit and TSOP type integrated circuit encapsulation coupling with number of pins.
Embodiment two
In the present embodiment, the test plate is still based on DIM72 DUT plate.
Referring to Fig. 6, test plate of the present utility model is a printed circuit board (PCB) 500, is provided with a plurality of plate connectors 501 and a plurality of golden finger (golden finger) 502 on the surface of this printed circuit board (PCB) 500;
The quantity of described plate connector 501 equates with the quantity of described golden finger 502, each described plate connector 501 is electrically connected with a golden finger 502 that (described plate connector 501 is embedded in the described printed circuit board (PCB) 500 with the coupling part of golden finger 502, therefore, not shown these coupling parts in Fig. 6);
Described plate connector 501 is the connector of described printed circuit board (PCB) 500 and socket;
Described golden finger 502 is the connector of described printed circuit board (PCB) 500 and DUT plate.
In the present embodiment, the plate connector of described test plate and the number of golden finger are based on two adjacent slots 101 of DIM-72 DUT plate 100 same rows, the test plate that is present embodiment is applicable to that the integrated circuit smaller or equal to 144 encapsulates (72＜pins≤144, wherein pins represents the number of pins of integrated circuit encapsulation) to number of pins greater than 72;
The surface of the printed circuit board (PCB) 500 of present embodiment is provided with 144 plate connectors 501 and 144 golden fingers 502;
Described 144 golden fingers 502 are distributed on the first surface and second surface of described printed circuit board (PCB) 500, golden finger number on described printed circuit board (PCB) 500 first surfaces equals the golden finger number on described printed circuit board (PCB) 500 second surfaces, be on the first surface of described printed circuit board (PCB) 500 and the second surface 72 golden fingers 502 (for clear, only showing the part golden finger in Fig. 6) to be arranged respectively;
Described golden finger 502 is arranged on the edge on described printed circuit board (PCB) 500 surfaces, the central authorities that described printed circuit board (PCB) 500 is provided with one side of golden finger 502 are provided with window 503, golden finger 502 on described printed circuit board (PCB) 500 first/second surfaces is evenly distributed in the both sides of this window 503, and the golden finger 502 on golden finger on the second surface 502 and the first surface is distributed on second surface and the first surface correspondingly respectively;
In the same side of described window 503, described golden finger 502 equidistantly distributes, and described spacing is 2.54mm, i.e. d3=d4=d5=2.54mm;
Described 144 plate connectors 501 are arranged on the centre on described printed circuit board (PCB) 500 surfaces, these 144 plate connectors 501 are shaped as two square boxs that vary in size arranging of described printed circuit board (PCB) 500 surfaces, big square box surrounds little square box, big square box comprises 76 plate connectors 501, and little square box comprises 68 plate connectors 501;
In each square frame, the space D 4 between adjacent two plate connectors 501, D5, D6, D7 equate that as shown in Figure 6, described spacing is 2.54mm, i.e. D4=D5=D6=D7=2.54mm; Space D 8 between two square frames also is 2.54mm, i.e. D8=2.54mm.
Please continue referring to Fig. 3, the using method of the test plate of present embodiment is: the pin of standard socket is inserted described plate connector 501, the realization standard socket is electrically connected with described printed circuit board (PCB) 500, packaged integrated circuit 504 is inserted standard socket, the realization integrated circuit encapsulates be electrically connected (just the realizing the electrical connection of integrated circuit packaging and testing plate) with standard socket, one side that described printed circuit board (PCB) 500 is provided with golden finger 502 is inserted in two adjacent slots 101 of described DIM-72 DUT plate 100 same rows, described golden finger 502 closely is connected with the pin of described slot 101, realizes being electrically connected of described printed circuit board (PCB) 500 and described DIM-72 DUT plate 100 (just realizing being electrically connected of integrated circuit encapsulation and described DIM-72 DUT plate 100).
This shows, be suitable for the test plate of present embodiment, DIM72 DUT plate 100 can the integrated circuit smaller or equal to 144 encapsulates the coupling use greater than 72 with number of pins, as encapsulation of BCC type integrated circuit and the encapsulation of flip chip type integrated circuit.
The design (comprising number and shape) of the golden finger of the utility model test plate is based on the DUT plate that will mate, the number that is golden finger is not limited to 72 and 144, the shape of golden finger is not limited to thin thin metal sheeting, the number of the plate connector of the utility model test plate equates with the number of golden finger, the shape of plate connector is based on the shape of the pin of standard socket, i.e. the plate connector of the utility model test plate should be complementary with standard socket commonly used.
Claims (8)
1. a test plate is characterized in that comprise a printed circuit board (PCB), the surface of described printed circuit board (PCB) is provided with a plurality of plate connectors and a plurality of golden finger;
The quantity of described plate connector equates that with the quantity of described golden finger each described plate connector has the corresponding golden finger that is electrically connected;
Described plate connector is connected with the external perimysium reference socket;
Described golden finger is connected with outside DUT plate.
2. test plate as claimed in claim 1 is characterized in that described golden finger is arranged on the edge of described printed circuit board (PCB).
3. test plate as claimed in claim 2, it is characterized in that, described a plurality of golden finger is evenly distributed on the first surface and second surface of described printed circuit board (PCB), and the golden finger on golden finger on the described printed circuit board (PCB) second surface and the described printed circuit board (PCB) first surface is distributed in respectively on described second surface and the first surface correspondingly.
4. as claim 1,2 or 3 described test plates, it is characterized in that described golden finger equidistantly distributes.
5. test plate as claimed in claim 3 is characterized in that the central authorities that described printed circuit board (PCB) is provided with the edge of golden finger are provided with window, and described golden finger is evenly distributed in the both sides of described window.
6. test plate as claimed in claim 5 is characterized in that, in the same side of described window, described golden finger equidistantly distributes.
7. test plate as claimed in claim 1 is characterized in that, described a plurality of plate connectors are by the centre of array distribution at described printed circuit board (PCB).
8. test plate as claimed in claim 7 is characterized in that, in delegation and/or same row, described golden finger equidistantly distributes.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201020246460XU CN201732104U (en) | 2010-06-30 | 2010-06-30 | Testing plug board |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201020246460XU CN201732104U (en) | 2010-06-30 | 2010-06-30 | Testing plug board |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN201732104U true CN201732104U (en) | 2011-02-02 |
Family
ID=43523263
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201020246460XU Expired - Fee Related CN201732104U (en) | 2010-06-30 | 2010-06-30 | Testing plug board |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN201732104U (en) |
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102721839A (en) * | 2012-07-09 | 2012-10-10 | 上海华岭集成电路技术股份有限公司 | Test adaptation board |
| CN103293457A (en) * | 2012-02-29 | 2013-09-11 | 韩商联测股份有限公司 | Testing board for burn-in tester |
| CN103837810A (en) * | 2012-11-27 | 2014-06-04 | 江苏绿扬电子仪器集团有限公司 | A device for testing characteristics of transistors in different packaging modes |
| CN109425810A (en) * | 2017-08-18 | 2019-03-05 | 台湾积体电路制造股份有限公司 | Semiconductor test apparatus, semiconductor test system and semiconductor test method |
-
2010
- 2010-06-30 CN CN201020246460XU patent/CN201732104U/en not_active Expired - Fee Related
Cited By (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103293457A (en) * | 2012-02-29 | 2013-09-11 | 韩商联测股份有限公司 | Testing board for burn-in tester |
| CN103293457B (en) * | 2012-02-29 | 2016-02-10 | 韩商联测股份有限公司 | For the test board of aging testing apparatus |
| CN102721839A (en) * | 2012-07-09 | 2012-10-10 | 上海华岭集成电路技术股份有限公司 | Test adaptation board |
| CN103837810A (en) * | 2012-11-27 | 2014-06-04 | 江苏绿扬电子仪器集团有限公司 | A device for testing characteristics of transistors in different packaging modes |
| CN109425810A (en) * | 2017-08-18 | 2019-03-05 | 台湾积体电路制造股份有限公司 | Semiconductor test apparatus, semiconductor test system and semiconductor test method |
| CN109425810B (en) * | 2017-08-18 | 2021-08-24 | 台湾积体电路制造股份有限公司 | Semiconductor test apparatus, semiconductor test system, and semiconductor test method |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US10656200B2 (en) | High volume system level testing of devices with pop structures | |
| US10393799B2 (en) | Electronic device package | |
| CN106771987A (en) | A kind of IC chip ageing tester and method of testing based on mother baby plate | |
| CN201732104U (en) | Testing plug board | |
| CN104316859A (en) | Chip testing equipment with high universality | |
| JP5872391B2 (en) | Electronic component testing equipment | |
| US6597189B1 (en) | Socketless/boardless test interposer card | |
| US7777514B2 (en) | Methods for transferring integrated circuits to a printed circuit board | |
| CN213337905U (en) | Chip testing device and system | |
| CN212723014U (en) | Detachable probe card device | |
| CN101257767A (en) | Printed circuit board and manufacturing method thereof | |
| CN204465503U (en) | General digital logical integrated circuit replacement module | |
| CN211698066U (en) | Electrical property detector of QFP packaging integrated circuit | |
| CN102306641B (en) | Storage module and packaging method | |
| CN101496234B (en) | Extended package substrate | |
| CN208568976U (en) | HTOL test board | |
| KR0141453B1 (en) | Manufacturing method of known-good die | |
| CN215581876U (en) | Side edge packaging type printed circuit board | |
| CN220473650U (en) | Aging board suitable for SOT23-3 packaged chip aging test | |
| CN113220513B (en) | Test keysets | |
| CN103869105A (en) | General type test board | |
| CN212111533U (en) | Probe card with new structure for testing DFN packaged IC | |
| JP2011237446A (en) | Method for collectively moving ic | |
| CN220357116U (en) | Test keysets | |
| CN219302518U (en) | Chip adapter plate |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant | ||
| ASS | Succession or assignment of patent right |
Owner name: SEMICONDUCTOR MANUFACTURING INTERNATIONAL (BEIJING Free format text: FORMER OWNER: SEMICONDUCTOR MANUFACTURING INTERNATIONAL (SHANGHAI) CORPORATION Effective date: 20130219 |
|
| C41 | Transfer of patent application or patent right or utility model | ||
| COR | Change of bibliographic data |
Free format text: CORRECT: ADDRESS; FROM: 201203 PUDONG NEW AREA, SHANGHAI TO: 100176 DAXING, BEIJING |
|
| TR01 | Transfer of patent right |
Effective date of registration: 20130219 Address after: 100176 No. 18 Wenchang Avenue, Beijing economic and Technological Development Zone Patentee after: Semiconductor Manufacturing International (Beijing) Corporation Address before: 201203 Shanghai City, Pudong New Area Zhangjiang Road No. 18 Patentee before: Semiconductor Manufacturing International (Shanghai) Corporation |
|
| CF01 | Termination of patent right due to non-payment of annual fee | ||
| CF01 | Termination of patent right due to non-payment of annual fee |
Granted publication date: 20110202 Termination date: 20180630 |