CN201682485U - Analog-to-digital combined data acquisition device - Google Patents
Analog-to-digital combined data acquisition device Download PDFInfo
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- CN201682485U CN201682485U CN2010202960544U CN201020296054U CN201682485U CN 201682485 U CN201682485 U CN 201682485U CN 2010202960544 U CN2010202960544 U CN 2010202960544U CN 201020296054 U CN201020296054 U CN 201020296054U CN 201682485 U CN201682485 U CN 201682485U
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Abstract
The utility model relates to a analog-to-digital combined data acquisition device, belonging to the technical field of data acquisition. The analog-to-digital combined data acquisition device comprises a first-stage analogue amplification conditioning circuit, a parallel multipath analogue amplification conditioning circuit, an AD sampling module and a digital control module. The parallel multipath analogue amplification conditioning circuit comprises an N-path amplification conditioning circuit formed by connecting two operational amplifiers in series. The output end of the first-stage analogue amplification conditioning circuit is connected with the N-path input end of the parallel multipath analogue amplification conditioning circuit, the N-path output end of the parallel multipath analogue amplification conditioning circuit is respectively connected with the N-path analogue input end of the AD sampling module, and the AD sampling module is connected with the digital control module through a control port. The acquisition device can intelligently realize automatic switchover of measuring range according to the size of analogue input signals, ensures the sampling precision, amplifies the dynamic range, automatically switches the time without additional measuring range, improving the sampling rate and ensuring the bandwidth of the system.
Description
Technical field
The utility model relates to a kind of analog-digital joint data acquisition device that adopts the associating of analog circuit and digital control circuit and carry out, and belongs to the data acquisition technology field.
Background technology
When measuring with transducer, do not know measured size sometimes, test circuit can't be selected suitable multiplication factor when beginning.When measured when neglecting little suddenly the variation greatly, if the multiplication factor of selecting hour, can obtain big measured sampled value, but just very little to the little measured sampled value that obtains, can not realize accurate measurement; If when selecting multiplication factor big, little measured can accurately being sampled, but measuredly will can't obtain correct sampled value because of no to scale to big.Therefore, along with the variation of analog value, the multiplication factor of test circuit and range must be able to dynamically change thereupon in measuring process.
General acquisition system all is that an analog signal connects one road analog amplify circuit and an AD sampling channel, analog amplify circuit adopts the programme-controlled gain amplifying circuit to change Amplifier Gain automatically usually, thereby make signal after amplifying, have suitable dynamic range, realize that promptly range automaticallyes switch.But this mode has limited the bandwidth of acquisition system, can't realize high-speed data acquisition.Need certain process and response time because change the gain of amplifying circuit, after changing, the gain of amplifying circuit also need a tracking to keep the sampling time just can carry out the AD conversion, make the required time of range automatic switchover longer, can't satisfy the collection needs of fast-changing high-frequency signal.
The utility model content
The purpose of this utility model provides a kind of analog-digital joint data acquisition device, with bigger to the analog quantity of unknown size and excursion and change violent transient impact analog quantity and realize super wide gain high-speed data acquisition.
For achieving the above object, analog-digital joint data acquisition device of the present utility model comprises first order simulation amplification modulate circuit, modulate circuit is amplified in the parallel duplex simulation, AD sampling module and digital control module, described parallel duplex simulation is amplified modulate circuit and is comprised N road amplification modulate circuit, N wherein〉2, each road in the described N road all is to amplify modulate circuit by the two-stage that the series connection of two operational amplifiers constitutes, the output that the operational amplifier of modulate circuit is amplified in described first order simulation links to each other with the N road input that modulate circuit is amplified in described parallel duplex simulation, the N road output that modulate circuit is amplified in the simulation of described parallel duplex links to each other with the N road analog input end of corresponding described AD sampling module respectively, and described AD sampling module links to each other by control port with digital control module.
Further, described digital control module comprises single-chip microcomputer, program storage, SDRAM data storage and sampled data memory.
Further, described single-chip microcomputer is a BF532 type dsp chip, and described program storage adopts the M29W320DB16 cake core, and described SDRAM data storage adopts the MT48LC32M16 cake core, and described sampled data memory adopts the K9F1G08 cake core.
Further, N=4 in the modulate circuit is amplified in described parallel duplex simulation.
Further, described AD sampling module comprises an AD7934 type AD chip.
Analog-digital joint data acquisition device of the present utility model in use, analog quantity input AI is connected to first order simulation earlier and amplifies modulate circuit, signal after amplification and conditioning is connected to the parallel duplex simulation simultaneously and amplifies in the input of modulate circuit, behind parallel N road amplification modulate circuit, the signal that analog signal becomes N different amplification is input on the different passage of AD sampling module simultaneously, N passage of digital control module may command AD sampling module triggers the AD conversion simultaneously, conversion is in case finish to read immediately the sampled value of the passage that satisfies sampling precision and measuring range, when analog quantity input hour, harvester can read sampled value from the bigger passage of multiplication factor, when the analog quantity input becomes big gradually, the continuous transformed samples passage of acquisition system meeting progressively reads sampled value from the passage that multiplication factor diminishes.Therefore, this harvester can be according to the size of analog input signal, realize that intelligently range automaticallyes switch, guaranteed sampling precision, enlarged dynamic range, and analog input signal is transformed into the signal of different amplification simultaneously after modulate circuit is amplified in the parallel duplex simulation, can trigger the AD conversion simultaneously behind the different sampling channels of access AD sampling module, digital control module can read the sampled value of respective channel according to the precision needs, need not extra range automaticallyes switch the time, thereby improved sampling rate, guaranteed the bandwidth of system.
Description of drawings
Fig. 1 is the systematic schematic diagram of the utility model embodiment;
Fig. 2 is the circuit diagram of the utility model embodiment;
Fig. 3 is the passage and switching bound graph of a relation of the utility model embodiment;
Fig. 4 is the automatic switchover triangular wave figure of the four-way system of the utility model embodiment.
Embodiment
Amplifying modulate circuit with N=4 road Parallel Simulation is that example describes analog-digital joint data acquisition device of the present utility model in detail, and the systematic schematic diagram of this device as shown in Figure 1.Analog-digital joint data acquisition device comprises that modulate circuit is amplified in first order simulation, modulate circuit, AD sampling module and digital control module are amplified in the parallel duplex simulation, the output that the operational amplifier of modulate circuit is amplified in first order simulation links to each other with the N road input that modulate circuit is amplified in the parallel duplex simulation, the N road output that modulate circuit is amplified in the parallel duplex simulation links to each other with the N paths analog input end of AD sampling module respectively, and the AD sampling module links to each other by control port with digital control module.
During N=4, the circuit diagram of harvester as shown in Figure 2.First order simulation is amplified modulate circuit and is comprised operational amplifier IC3, the parallel duplex simulation is amplified modulate circuit and is made up of four tunnel simulation amplification modulate circuits, wherein each road all is to amplify modulate circuit by the two-stage that the series connection of two operational amplifiers constitutes, operational amplifier IC1, IC2 are connected into the four the tunnel and amplify modulate circuit, operational amplifier IC5, IC6 are connected into Third Road and amplify modulate circuit, operational amplifier IC7, IC8 are connected into the second the tunnel and amplify modulate circuit, and operational amplifier IC9, IC10 series connection constitutes the first via and amplifies modulate circuit; Operational amplifier IC4A forms reference voltage driving circuit, and the reference voltage of modulate circuit is amplified on each road of AD sampling module may command.Amplifying modulate circuit with the first via is example: operational amplifier IC9 forms second level amplifying circuit, and operational amplifier IC10 forms modulate circuit, with the signal that conversion of signals can receive for the AD chip, can align negative signal and sample; Diode D4, capacitor C 15,32 pairs of signals of resistance R ration the power supply pressure, filtering, current limliting guarantee that signal can not surpass the range of the analog input interface of AD chip.
U1 among Fig. 2 (AD7934) is the AD sampling A, can carry out the AD conversion to 4 tunnel analog quantitys, and conversion accuracy is 12, the highest 1.5MHz of sample frequency.Digital control module mainly comprises dsp chip U2 (BF532), program storage U3 (M29W320DB16), SDRAM data storage U4 (MT48LC32M16), sampled data memory composition U5 (K9F1G08).U2(BF532) be 16 high-speed dsp chips of AD company, the high operation speed of kernel can reach 600MHz.U3 (M29W320DB16) is the FLASH memory of one 16 32M byte, is mainly used to the system operation programs of storage device.U4 (MT48LC32M16) is the SDRAM memory of one 16 32M byte, is mainly used to store operational data and sampled data temporarily.U5 (K9F1G08) is the FLASH memory of one 8 1G byte, is mainly used to permanent and long-time preserve sampled data and customer parameter etc.
After analog quantity AI input realizes that through IC3 the first order is amplified conditioning, being connected to four the tunnel simultaneously amplifies in the input of modulate circuit, after amplifying, nursing one's health, be transformed into signal VIN0, VIN1, VIN2 and VIN3 respectively, be connected to then in the four paths analog inputs of AD sampling A with different amplification.The DSP control module can be controlled the AD sampling A by pin AMS3, AWE, TIMR0 and data/address bus and carry out parameters such as the frequency of AD conversion, triggered time, convert the hardware interrupts that triggers DSP by pin PF8 as AD, and can be kept among the SDRAM by the sampled value that pin AMS3, ARE and data/address bus read certain passage, data are saved in the FLASH memory of U5 (K9F1G08) again after waiting signal acquisition process to finish. temporarilyThese data can be sent in the host computer by communication interface and analyze.
The parallel duplex simulation is amplified modulate circuit and can be determined according to actual needs by this N of N(, generally greater than 2, having 4 the tunnel in this circuit) the identical amplification modulate circuit of individual circuit theory forms, they have identical input and output accordingly separately, the multiplication factor difference of each circuit, and arrange according to certain rules to guarantee its measuring range and precision.The output of each circuit is all nursed one's health in the desired input range of AD sampling A, is connected to then on the different sampling channel of AD sample circuit.This circuit adopts the AD chip of one 4 input, if the way of parallel duplex simulation amplification modulate circuit is more, can adopt multi-disc AD chip.Also can adopt more multiple input path and the higher AD chip of inversion frequency.Digital control circuit also can adopt other circuit, as long as operating rate and memory space etc. meet the demands.
Specific embodiment:
As shown in Figure 3.When N=4, the multiplication factor that modulate circuit is amplified in first order simulation is made as 1, the multiplication factors that modulate circuits are amplified in four tunnel simulations that modulate circuit is amplified in parallel duplex simulation are made as 1,2,4,8 respectively, and then the multiplication factor corresponding to each sampling channel VIN0～VIN3 of AD chip is respectively 1,2,4,8.The input range of each AD sampling channel all is 0～5V, then the scope of the input analog amount of VIN3 passage correspondence is 0～0.625V, the scope of the input analog amount of VIN2 passage correspondence is 0～1.25V, the scope of the input analog amount of VIN1 passage correspondence is 0～2.5V, and the scope of the input analog amount of VIN0 passage correspondence is 0～5V.The sampling precision of AD sampling A is 12, so the reading after its AD conversion is 0～4096.For guaranteeing the consistency of data, all convert the sampled value of other passage the value of VIN3 passage to, promptly the range of readings of VIN3 is 0～4096, and the range of readings of VIN2 is 0～4096 * 2, the range of readings of VIN1 is 0～4096 * 4, and the range of readings of VIN0 is 0～4096 * 8.
For guaranteeing sampling precision and realizing that passage automaticallyes switch, can establish when input analog amount after amplifying, 80% o'clock that reaches AD sampling channel input range for switching higher limit (being 4V), the switching upper limit of so corresponding each passage and switching lower limit were as shown above in order to switch lower limit (being 1.6V) in 32% o'clock that reaches AD sampling channel input range.
The triangular wave that changes for 0～5V then, the sampling initial channel is made as VIN3, when waveform by 0V when 0.5V changes, VIN3 passage reading by the multiplication factor maximum, system automatically switches to VIN2 passage reading after waveform surpasses 0.5V, system automatically switches to VIN1 passage reading after waveform surpasses 1V, and system automatically switches to VIN0 passage reading after waveform surpasses 2V.Waveform reaches 5V to begin to descend, and system automatically switches to VIN1 passage reading after waveform drops to 1.6V, and system automatically switches to VIN2 passage reading after waveform drops to 0.8V, and system automatically switches to VIN3 passage reading after waveform drops to 0.4V.Its variation is as shown below.
For different situations, N can get different values, and the also desirable different value of the multiplication factor on each road is then switched the upper limit accordingly and also can be got different values according to actual conditions and required precision with the switching lower limit.
Claims (5)
1. analog-digital joint data acquisition device, it is characterized in that, this device comprises first order simulation amplification modulate circuit, modulate circuit is amplified in the parallel duplex simulation, AD sampling module and digital control module, described parallel duplex simulation is amplified modulate circuit and is comprised N road amplification modulate circuit, N wherein〉2, each road in the described N road all is to amplify modulate circuit by the two-stage that the series connection of two operational amplifiers constitutes, the output that the operational amplifier of modulate circuit is amplified in described first order simulation links to each other with the N road input that modulate circuit is amplified in described parallel duplex simulation, the N road output that modulate circuit is amplified in the simulation of described parallel duplex links to each other with the N road analog input end of corresponding described AD sampling module respectively, and described AD sampling module links to each other by control port with digital control module.
2. a kind of analog-digital joint data acquisition device according to claim 1 is characterized in that: described digital control module comprises single-chip microcomputer, program storage, SDRAM data storage and sampled data memory.
3. a kind of analog-digital joint data acquisition device according to claim 2, it is characterized in that: described single-chip microcomputer is a BF532 type dsp chip, described program storage adopts the M29W320DB16 cake core, described SDRAM data storage adopts the MT48LC32M16 cake core, and described sampled data memory adopts the K9F1G08 cake core.
4. according to each described a kind of analog-digital joint data acquisition device in the claim 1 to 3, it is characterized in that: N=4 in the modulate circuit is amplified in described parallel duplex simulation.
5. a kind of analog-digital joint data acquisition device according to claim 4 is characterized in that: described AD sampling module comprises an AD7934 type AD chip.
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| CN2010202960544U CN201682485U (en) | 2010-08-19 | 2010-08-19 | Analog-to-digital combined data acquisition device |
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| CN2010202960544U CN201682485U (en) | 2010-08-19 | 2010-08-19 | Analog-to-digital combined data acquisition device |
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Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101917196A (en) * | 2010-08-19 | 2010-12-15 | 河南科技大学 | Analog-to-digital joint type data acquisition device |
| CN104410418A (en) * | 2014-12-03 | 2015-03-11 | 杭州腾振科技有限公司 | Analog-digital conversion circuit with high dynamic range |
| CN106374928A (en) * | 2016-09-30 | 2017-02-01 | 西电通用电气自动化有限公司 | Implementation circuit and method for enhancing small signal data collection resolution of analog chain |
| CN110702976A (en) * | 2019-11-01 | 2020-01-17 | 湖南银河电气有限公司 | Wide-range high-precision current sensor/ammeter |
| CN111162784A (en) * | 2020-01-08 | 2020-05-15 | 北京工业大学 | Implementation mode of high-resolution analog-to-digital converter |
-
2010
- 2010-08-19 CN CN2010202960544U patent/CN201682485U/en not_active Expired - Lifetime
Cited By (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101917196A (en) * | 2010-08-19 | 2010-12-15 | 河南科技大学 | Analog-to-digital joint type data acquisition device |
| CN101917196B (en) * | 2010-08-19 | 2013-07-17 | 河南科技大学 | Analog-to-digital joint type data acquisition device |
| CN104410418A (en) * | 2014-12-03 | 2015-03-11 | 杭州腾振科技有限公司 | Analog-digital conversion circuit with high dynamic range |
| CN106374928A (en) * | 2016-09-30 | 2017-02-01 | 西电通用电气自动化有限公司 | Implementation circuit and method for enhancing small signal data collection resolution of analog chain |
| CN110702976A (en) * | 2019-11-01 | 2020-01-17 | 湖南银河电气有限公司 | Wide-range high-precision current sensor/ammeter |
| CN111162784A (en) * | 2020-01-08 | 2020-05-15 | 北京工业大学 | Implementation mode of high-resolution analog-to-digital converter |
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Granted publication date: 20101222 Effective date of abandoning: 20130717 |
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