CN201409119Y

CN201409119Y - CMOS switch chip circuit

Info

Publication number: CN201409119Y
Application number: CN2009200726959U
Authority: CN
Inventors: 陶园林
Original assignee: SHANGHAI ECRANIC ELECTRONIC CO Ltd
Current assignee: Haide Zhongye Technology Innovate Engineering Co., Ltd., Shanghai; SHANGHAI ECRANIC MICROELECTRONICS CO., LTD.
Priority date: 2009-05-21
Filing date: 2009-05-21
Publication date: 2010-02-17
Anticipated expiration: 2019-05-21

Abstract

The utility model discloses a CMOS switch chip circuit, which comprises a NMOS pipe and a PMOS pipe, and is characterized in that the substrate of the NMOS pipe is earthed, the source electrode thereof is connected with the output end of a first resistance, the drain electrode is connected with the input end of a second resistance, the source electrode of the first PMOS pipe is connected with theinput end, the drain electrode is connected with the output end, the substrate of the first PMOS pipe is connected with a substrate bias circuit, and the substrate bias circuit is further connected with the input end and the output end. Compared with a traditional CMOS switch chip circuit, the circuit can realize high transmission rate and bandwidth under the condition of keeping a certain low conducting resistance, and simultaneously can effectively improve the ESD performance of the switch chip.

Description

A kind of cmos switch chip circuit

Technical field:

The utility model relates to the switch chip field, is specifically related to a kind of cmos switch chip circuit.

Background technology:

The cmos switch chip is widely used in signal transmission and the control system.Fig. 1 is a traditional cmos switch chip circuit, and it is made up of two parts, NMOS pipe N1 and PMOS pipe P1.NMOS manages N1 by its grid 2 voltage control, when grid 2 voltages are high level, and the N1 conducting, on the contrary end.PMOS manages P1 by grid 4 voltage control, when grid 4 voltages are low level, and the P1 conducting, on the contrary end.

In conventional P type substrate N-well process, substrate 5 ground connection of NMOS pipe N1, and the substrate 6 of PMOS pipe P1 connects the N trap, its voltage floats, and connects the source end of supply voltage VDD or P1 usually.If P1 substrate 6 meets VDD, can be when the conducting of P1 pipe because the substrate bias effect of metal-oxide-semiconductor increases the cut-in voltage of P1 pipe, thereby the conducting resistance of P1 pipe is increased, and the variation of conducting resistance also becomes greatly in whole signal transmission ranges, thereby influences the flatness of resistance.If the substrate 6 of P1 pipe connects the source end of P1, can avoid the P1 pipe when conducting, to serve as a contrast of the influence of inclined to one side effect like this to P1 pipe cut-in voltage, but can bring another problem like this, promptly when the P1 pipe turn-offs, because this moment, 1,3 terminal voltages were uncertain, might there be voltage difference in 1,3 ends, and such 1 end or 3 ends are to the just possible conducting of the PN diode of N trap, cause the P1 pipe to turn-off fully, leakage current generating is arranged.

Usually, 1,3 ends of Fig. 1 circuit are directly connected to the package pins of chip, and this just needs 1,3 ends that higher ESD tolerance will be arranged.In the design of high-speed cmos switch chip,, will under the situation of protecting just right conducting resistance, reduce the area of switching tube N1, P1 as far as possible, thereby reduce the parasitic capacitance of 1,3 ends for speed and the bandwidth that improves switch.But, because the source-

drain electrode

1,3 of N1, P1 pipe is directly linked chip pin, reduce the area of N1, P1 pipe, will reduce the ESD holding capacity of 1,3 ends.A kind of solution to this problem is to add esd protection structure at 1,3 ends.But esd protection structure also can increase the parasitic capacitance at these two ends, thereby reduces the speed and the bandwidth of cmos switch.

Summary of the invention:

The purpose of this utility model is to provide a kind of cmos switch chip circuit, to solve the problem of above-mentioned switching speed, bandwidth and ESD performance.

Technic relization scheme of the present utility model is as follows: a kind of cmos switch chip circuit, comprise NMOS pipe and PMOS pipe, the substrate ground connection that it is characterized in that the NMOS pipe, its source electrode connects output by first resistance, drain electrode connects input by second resistance, and the source electrode of a PMOS pipe connects input, and drain electrode connects output, the substrate of the one PMOS pipe connects the substrate biasing circuit, and this substrate biasing circuit also is connected with output with input.This substrate biasing circuit comprises three PMOS pipes, wherein the drain electrode of the 2nd PMOS pipe connects input, the grid of the 2nd PMOS pipe connects the grid of a PMOS pipe, the source electrode of the 2nd PMOS pipe and substrate all connect the substrate of a PMOS pipe, the drain electrode of the 3rd PMOS pipe connects output, the grid of the 3rd PMOS pipe connects the grid of a PMOS pipe, the source electrode of the 3rd PMOS pipe and substrate all connect the substrate of a PMOS pipe, the source electrode and the substrate of the 4th PMOS pipe connect power supply, the drain electrode of the 4th PMOS pipe connects the substrate of a PMOS pipe, and the grid of a PMOS pipe is connected by the grid of phase inverter with the 4th PMOS pipe.

Compare with traditional cmos switch chip circuit, the utility model can be realized high transmission rate and bandwidth under the situation that keeps certain low on-resistance, can effectively improve the ESD performance of switch chip simultaneously.

Description of drawings:

Fig. 1 is a traditional cmos switching circuit structure;

Fig. 2 is another traditional cmos switching circuit structure;

Fig. 3 is the cmos switch circuit structure that the utility model proposes.

Embodiment:

Below in conjunction with accompanying drawing and embodiment the utility model is elaborated.

As shown in Figure 3, the utility model structure is as follows: NMOS pipe N1 and PMOS pipe P1 constitute basic cmos switch, wherein NMOS manages substrate 5 ground connection of N1, its source electrode connects output 3 by first resistance R 2, drain electrode connects input 1 by the source electrode that second resistance R 1 meets input 1, the one PMOS pipe P1, and drain electrode connects output 3, the substrate of the one PMOS pipe P1 connects the substrate biasing circuit, and this substrate biasing circuit also is connected with output with input.This substrate biasing circuit comprises three PMOS pipe P2～P4, wherein the drain electrode of the 2nd PMOS pipe P2 connects input, the grid of the 2nd PMOS pipe P2 connects the grid 4 of PMOS pipe P1, the source electrode of the 2nd PMOS pipe P2 and substrate all connect the substrate 6 of PMOS pipe P1, the drain electrode of the 3rd PMOS pipe P3 connects output, the grid of the 3rd PMOS pipe P3 connects the grid of PMOS pipe P1, the source electrode of the 3rd PMOS pipe P3 and substrate all connect the substrate of PMOS pipe P1, source electrode and the substrate of the 4th PMOS pipe P4 connect power supply, the drain electrode of the 4th PMOS pipe P4 connects the substrate of PMOS pipe P1, and the grid of PMOS pipe P1 is connected with the grid of the 4th PMOS pipe P4 by phase inverter INV.The grid of number in the figure 2 expression NMOS pipe N1.

Compare with traditional cmos switch circuit, the utility model leaks two ends in nmos switch pipe N1 source increased the input/output terminal that two resistance connect switch respectively; Increased the substrate biasing circuit that three PMOS pipe P2～P4 and gun stocks INV constitute PMOS switching tube P1 in addition.

Improving chip ESD aspect of performance, operation principle of the present utility model is as follows: in traditional cmos process, the PMOS of identical conducting resistance pipe and NMOS pipe, the ESD performance of NMOS pipe compare the PMOS pipe will a little less than.Particularly in the cmos switch chip circuit, because the source-drain electrode of PMOS pipe and NMOS pipe is all directly linked the package pins of chip, they directly bear ESD in chip uses impact, so the ESD tolerance of NMOS pipe source drain terminal has directly determined the ESD performance of whole C MOS switch chip.The utility model connects the input and output of switch by respectively increasing a resistance in the leakage of the source of NMOS pipe, thereby has increased the ability of the anti-ESD rush of current of nmos switch pipe source drain terminal, has improved the ESD performance of entire chip.

In CMOS technology, resistance R 1, R2 can be realized by the low-resistance polysilicon, because the MOS switching tube adopts interdigital structure more in domain structure, a switching tube can be formed in parallel by hundreds of even thousands of little metal-oxide-semiconductors, therefore can improve the ESD performance of NMOS pipe at respectively connect one tens ohm polysilicon resistance of the source drain terminal of the little NMOS pipe of each root, this also just is equivalent to be connected in series a small resistor by the resistance parallel connection of hundreds of～several thousand pieces tens ohm at the source of nmos switch pipe drain terminal, so it can be ignored to the influence of switch conducting resistance.

Raising for switching speed and bandwidth, operation principle of the present utility model is: when PMOS pipe P1 grid 4 connects low level, the P1 pipe is opened, P2, P3 open simultaneously, P4 ends, make the underlayer voltage of PMOS switching tube P1 follow its source-drain voltage like this, so just eliminated the substrate bias effect of PMOS pipe, make the conducting resistance of PMOS pipe reduce.Like this, under certain conducting resistance condition, just can reduce the area of PMOS switching tube, thereby reduce the parasitic capacitance of switch input/

output terminal

1,3, improve the speed and the bandwidth of switch from face.

When PMOS switching tube P1 grid 4 connect high level, P1 carried and ends, and P2, P3 end simultaneously, and the P4 conducting makes the substrate 6 of P1 pipe connect power supply by the P4 pipe from face.Like this no matter the level of 1,3 ends how, the PMOS switching tube can be protected the substrate leakage current of positive minimum.

Claims

1, a kind of cmos switch chip circuit, comprise NMOS pipe and PMOS pipe, the substrate ground connection that it is characterized in that the NMOS pipe, its source electrode connects output by first resistance, drain electrode connects input by second resistance, and the source electrode of a PMOS pipe connects input, and drain electrode connects output, the substrate of the one PMOS pipe connects the substrate biasing circuit, and this substrate biasing circuit also is connected with output with input.

2, cmos switch chip circuit as claimed in claim 1, it is characterized in that this substrate biasing circuit comprises three PMOS pipes, wherein the drain electrode of the 2nd PMOS pipe connects input, the grid of the 2nd PMOS pipe connects the grid of a PMOS pipe, the source electrode of the 2nd PMOS pipe and substrate all connect the substrate of a PMOS pipe, the drain electrode of the 3rd PMOS pipe connects output, the grid of the 3rd PMOS pipe connects the grid of a PMOS pipe, the source electrode of the 3rd PMOS pipe and substrate all connect the substrate of a PMOS pipe, the source electrode and the substrate of the 4th PMOS pipe connect power supply, the drain electrode of the 4th PMOS pipe connects the substrate of a PMOS pipe, and the grid of a PMOS pipe is connected by the grid of phase inverter with the 4th PMOS pipe.