CN201035091Y - Output electric voltage status indication circuit used for electric power chip - Google Patents
Output electric voltage status indication circuit used for electric power chip Download PDFInfo
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Abstract
The utility model discloses a status indication circuit of power source chip output voltage, comprising a double threshold value comparator, a counter, an oscillator and a delay latch unit. The double threshold value comparator is used to limit the output voltage V<OUT> range of the switch power source chip; the counter always outputs a pair of opposite signal; the oscillator produces periodic square wave signal for the counter; the delay latch unit detects the abnormal state time of output voltage. If in the buffer time fault is corrected and output voltage gets back to the normal range, the circuit still outputs a normal voltage indication signal. If after the buffer time fault isn't corrected and output voltage is still out of the prescriptive range, the circuit outputs an abnormal voltage indication signal, so as to make subordinate chip easy to take relevant protection measures. The circuit has the advantages of saving chip layout area, decreasing chip power consumption, having simple structure, and being easy to realize.
Description
Technical Field
The utility model belongs to the power chip field specifically is an output voltage state indicating circuit for power chip.
Background
In recent years, the Integrated Circuits (Integrated Circuits) industry has been developing rapidly, and among them, digital Signal chips (Digital Signal processes) and Mixed Signal chips (Mixed Signal ICs) are the more robust power to develop. In such a background, a switching power supply chip as a power supply for other chips is also widely used. The switching power supply chip adopts other external power supplies (such as lithium batteries and alternating current-direct current transformers for commercial power) as input power supplies, and stable output voltage is obtained through conversion of internal circuits of the chip and peripheral energy storage devices. If the output voltage is higher than the input voltage, the voltage is called a boost chip; if the output voltage is lower than the input voltage, we call it a buck chip.
In the process of supplying power to other chips, a large fluctuation of the output voltage of the switching power supply chip can be caused by many factors, such as output short circuit, insufficient power supply of an input power supply, abnormal operation of a circuit inside the chip, and the like. These all cause the output voltage to deviate from the preset value of the designer, which results in unstable working state of the chip at the next stage and even damages the chip. Therefore, an output voltage indicating circuit needs to be designed for the switching power supply chip, so that a subordinate chip can take protective measures in time. In the switching power supply chip, other protection circuits (such as input under-voltage protection, output over-current protection, overheating protection and the like) are also arranged, and the existence of the protection circuits enables the switching power supply chip to have certain capability of solving abnormal conditions, so that the output voltage indicating circuit should reserve certain buffer time for the process of solving the abnormal conditions by the protection circuits, if the output voltage of the chip returns to normal within set time, the output voltage indicating circuit still outputs a 'normal' signal, and if the output voltage of the chip does not return to normal within set time, the output voltage indicating circuit outputs an 'abnormal' signal, and the lower-level chip is allowed to take protection measures. Typically this output lag time does not exceed 1 millisecond.
In the design of the conventional output voltage detection circuit, the detection circuit often has only one threshold, namely only for V OUT Is detected, and an upper or lower limit of the threshold is detected. In the patent document "output voltage detection circuit" (application number: 00N 3000), an output voltage detection circuit is designed to detect only a case where an output voltage is higher than a normal value, but not a case where the output voltage is lower than the normal value. In practical applications, it is not uncommon for the output voltage to be lower than normal, which is the case when the output is shorted.
Usually, one comparator can only have one threshold, and two comparators are necessary to achieve detection of two different voltages. In the patent document "voltage detection circuit" (application number: 99N 6974), the voltage detection circuit is designed to realize the detection of the same voltage high and low threshold values, i.e. to have the function of window detection, but it still uses two comparators. Because two comparators are used, the area of a chip is inevitably increased, devices are increased, the bias current is increased, and the power consumption of the chip is increased.
Disclosure of Invention
An object of the utility model is to provide an output voltage state indicating circuit for power chip, chip territory area can be saved to this circuit, reduces the chip consumption to simple structure easily realizes.
The utility model provides an output voltage state indicating circuit for power supply chip, which comprises a dual-threshold comparator, a counter, an oscillator and a delay latch unit; wherein, the dual-threshold comparator is used for limiting the output voltage V of the switching power supply chip OUT Range when the output voltage V OUT When the signal is between the high and low threshold values, outputting a high level signal, otherwise, outputting a low level signal; output terminal O of counter 2 、O 3 The two output terminals are always a pair of opposite signals; two input terminals EN1 and EN2 of the oscillator are respectively connected with an output terminal O1 of the dual-threshold comparator and the other output port O of the delay latch unit 6 The connection is carried out in a connecting way, for generating a periodic square wave signal for the counter; three input ports of the delay latch unit are respectively connected with two output ports O of the counter 2 、O 3 Output port O of sum threshold comparator 1 One output end of the oscillator is connected with an enable port EN2 of the oscillator, and the other output end of the oscillator is used for outputting a voltage indication signal PG; dual threshold comparisonThe device converts two input output voltage signals into current signals through differential pair transistors, and sets a window range for the output voltage; when the output voltage falls out of the window range, the oscillator in the indicating circuit starts to work, the counter starts to count along with a clock signal generated by the oscillator, if the output voltage returns to the normal range within one cycle of time, the output voltage indicating signal of the delay latch unit is displayed as normal, otherwise, the output voltage indicating signal is displayed as abnormal.
The utility model discloses the theory of operation is: the dual-threshold comparator sets a window range for the output voltage, when the output voltage falls out of the window range, the oscillator in the indicating circuit starts to work, the counter starts to count along with a clock signal generated by the oscillator, and if the output voltage returns to a normal range within one cycle time, the output PG of the indicating circuit still indicates 'normal'; if the output voltage has not recovered to the normal range within one cycle time, the output PG of the indicating circuit indicates "abnormal". The output voltage dual-threshold comparator converts two input signals into current signals through a differential pair transistor, sets a window range for the output voltage, and indicates that an oscillator of the circuit starts to work after the output voltage falls out of the window. The circuit has an oscillator and a counter for setting the hysteresis time. The counter counts under the periodic square wave signal generated by the oscillator, and the output signal of the counter changes after the counting is completed for one cycle. The delay latch unit also changes the output signal PG accordingly. If the counting is less than one cycle, the output signal of the counter will not change, and the output signal PG of the delay latch unit will not change.
Compare with traditional single threshold value output voltage detection circuit, the utility model discloses the circuit has a comparator and realizes the function that the dual threshold value is compared for detect output voltage's high, two low threshold values, alright like this in order to detect more abnormal conditions. Compare with the output voltage detection circuit that has dual threshold value of certain improved generation, the utility model discloses use a comparator to realize dual threshold's settlement, saved chip territory area greatly, reduced the chip consumption, simple structure moreover easily realizes.
Drawings
Fig. 1 is a schematic diagram of a circuit structure of an output voltage indicating circuit according to the present invention;
fig. 2 (a) and (b) are circuit diagrams of two specific implementations of the dual-threshold comparator 1, and fig. 2 (c) is a waveform diagram of an output;
fig. 3 (a) and (b) are circuit diagrams of two specific implementations of the delay latch unit 4;
fig. 4 is a timing waveform diagram of the potential of each main terminal in the circuit of the present invention.
Detailed Description
As shown in fig. 1, the output voltage indicating circuit of the present invention includes: the circuit comprises a dual-threshold comparator 1, a counter 2, an oscillator 3 and a delay latch unit 4. The final output signal PG (Power Good) indicates whether the output voltage is operating within a set normal range.
The dual-threshold comparator 1 has 3 input terminals, and two negative input terminals are connected with a reference voltage V generated in the chip REF The threshold voltages corresponding to the two negative terminals are V TH - And V TH + . Feedback signal V with positive input terminal connected with output voltage of power supply chip FB ，O 1 Is the comparator output signal. When the output voltage has V TH - ＜V OUT ＜V TH + When, V O1 =1, otherwise, V O1 ＝0。
The truth table of the inputs and outputs of the counter 2 is as follows:
the oscillator 3 has two input terminals: the enable signal EN1 and the enable signals EN2, EN1 are connected to the output terminal O of the dual threshold comparator 1 1 EN2 is connected to O of delay latch unit 4 6 And a terminal.
The effect in the circuit is to generate a periodic square wave signal for the counter 2. In the design, in order to reduce the chip cost and the layout area, a ring oscillator 3 with a relatively simple structure can be adopted, and the oscillator 3 generates a square wave with a period T. The output delay time of the circuit design is NT as can be seen from the description of the counter 2.
The delay latch unit 4 has three input terminals IN1, IN2, IN3, a first output terminal O, and a second output terminal O 6 And Powergood (PG), the input terminal IN1 is connected with the output terminal O of the counter 2 2 An input terminal IN2 is connected to an output terminal O of the counter 2 3 The input terminal IN3 is connected to the output O of the dual threshold comparator 1 1 First output terminal O 6 The second output terminal PG is an output voltage indication signal connected to the enable terminal EN2 of the oscillator.
The dual-threshold comparator 1 has two threshold voltages, i.e. high and low, which are set in a range that we consider the normal operating range of the output voltage. When the output voltage is within this range, the circuit does not operate, and when the output voltage is outside this range, the entire circuit starts operating. The specific process is as follows:
(1) When the voltage detected by the dual-threshold comparator 1 is in the set range, the output signal of the dual-threshold comparator 1 is at a high level, and since the output signal is the enable signal of the counter 2 and the oscillator 3, and is active low, both the counter 2 and the oscillator 3 do not operate, and the delay latch unit 4 also maintains the indication signal when the output voltage is in the normal operating range, the output voltage indication signal PG maintains a high level, i.e., indicates that the output voltage is in the normal range.
(2) When the output voltage detected by the dual-threshold comparator 1 falls outside the operating range set by us, the dual-threshold comparator 1 detects the change and immediately reflects the change in its output, the output goes low, the enable terminals of the counter 2 and the oscillator 3 are enabled, and they start to operate. The counter 2 is an N-bit counter, the period of the square wave generated by the oscillator 3 is T, the output signal of the counter 2 is kept unchanged in NT time, and after the counting time exceeds NT, the output signal changes, and at this time, the delay latch unit 4 no longer keeps the normal level of the output voltage, but outputs a level indicating abnormality. If the counting time of the counter 2 does not exceed the NT time, the output of the counter 2 does not change, and the delay latch unit 4 still outputs the normal indication signal.
Each of the portions will be described in further detail below by way of example.
The dual-threshold comparator 1 implements a voltage dual-threshold comparison function by using a single comparator, and its circuit diagram is shown in fig. 2 (a) or (b).
As shown in FIG. 2 (a), the gate of PMOS transistor P1 is connected to the chip output voltage V OUT Is fed back to the voltage source V FB The grid of the PMOS pipe P2 is connected with a reference voltage V inside the chip REF PMOS tubes P1 andthe PMOS pipe P2 forms a differential pair circuit and is used as an input pipe of the comparator. A first current source 113 provides bias current to the differential pair, with the positive terminal connected to V DD And the negative electrode is connected with the source electrodes of the PMOS pipe P1 and the PMOS pipe P2. The NMOS tube N2 and the NMOS tube N3 are diode-connected and used as loads of the PMOS tube P1 and the PMOS tube P2, the drain electrode of the NMOS tube N2 is connected with the drain electrode of the NMOS tube P1, the drain electrode of the NMOS tube N3 is connected with the drain electrode of the PMOS tube P2, and the NMOS tube N2 is the same as the NMOS tube N3. NMOS transistor N1 and NMOS transistor N2 form a current mirror, and V is converted into FB Converted into a current signal I 1 PMOS transistor P3, PMOS transistor P4 and PMOS transistor P5 form a current mirror, and I 1 Conversion into I 2 And I 3 And has I 1 ＝I 2 ＝I 3 . Drain current I flowing through NMOS transistor N3 4 Likewise is composed of V REF Converted into NMOS transistors N3 and N4, and NMOS transistors N3 and NCurrent mirror I composed of tube N5 4 Conversion to I 5 、I 6 。I 4 ，I 5 ，I 6 The relationship of (A) is as follows:
to implement the function of window comparison, we make I 4 ＜I 5 ，I 4 ＜I 6 。I 5 ，I 6 I.e. determines two thresholds for the comparator. For example, we set V OUT Is [90% ]V OUT ，110％V OUT ]Then, I 5 ＝90％I 4 ，I 6 ＝110％I 4 。
Since NMOS transistors N2 and N3 are the same NMOS transistor, when V is REF ＝V FB When, I 1 ＝I 4 . The PMOS tube P4 and the NMOS tube N4 form a current comparison branch of the comparator for I 2 And I 5 Comparing to output low threshold output signal O 4 And transmits the signal to the second-stage inverter pole connection unit 110. The PMOS tube P5 and the NMOS tube N5 form another current comparison branch of the comparator for I 3 And I 6 Comparing to output high threshold output signal O 5 And transmits the signal to the three-stage inverter pole connection unit 111. When V is FB ＜90％V REF When is, O 4 At a low level, V FB ＞90％V REF When is, O 4 Is high level; also has when V FB ＜110％V REF When is, O 5 At a low level, V FB ＞110％V REF When is, O 5 Is high. The two-stage inverter pole connection unit 110 and the three-stage inverter pole connection unit 111 are used for shaping and adjusting output phases to enable O 5 Lags behind O 4 Phase 180 deg.. The two output signals passing through the second stage inverter pole connecting unit 110 and the third stage inverter pole connecting unit 111 enter an AND gate 112 to obtain a final windowIndicating voltage signal O 1 . This structure allows information reflected by two thresholds to be output as one signal. We obtained when 90% v REF ＜V FB ＜110％V REF When is, O 1 =1, otherwise O 1 ＝0。
Another circuit of the dual-threshold comparator 1 is also a differential-input single-ended-output circuit, as shown in fig. 2 (b). The PMOS transistor P8 and the PMOS transistor P9 form a differential input transistor, a source of the PMOS transistor P8 is connected to one end of the resistor 122, the other end of the resistor 122 is connected to a negative terminal of the second current source 131, and a source of the PMOS transistor P9 is connected to a negative terminal of the second current source 131. The NMOS transistors N6 and N8 are diode-connected MOS transistors and are respectively used as loads of a PMOS transistor P8 and a PMOS transistor P9. The NMOS transistors N6 and N7 form a current mirror, and the current flowing through the PMOS transistor P8 is mirrored to a branch formed by the NMOS transistor N7 and the PMOS transistor P6; similarly, the NMOS transistors N8 and N9 constitute a current mirror, and mirror the current flowing through the PMOS transistor P9 to the branch formed by the NMOS transistor N9 and the PMOS transistor P7. The PMOS tube P6 and the PMOS tube P7 form a current mirror structure, and the drain current of the PMOS tube P6 is mirrored to the PMOS tube P7 and is output from the drain. In this way, the currents flowing through the PMOS transistors P8 and P9 are finally compared in the branch formed by the PMOS transistor P7 and the NMOS transistor N9, and the output result O1 is obtained after the shaping of the first inverter 129 and the second inverter 130. In this case, the PMOS transistors P8 and P9 are identical, the NMOS transistors N6 and N7, the NMOS transistors N8 and N9, and the PMOS transistors P6 and P7 are also identical. The resistor 122 in this circuit functions to set the threshold of the comparator, and the PMOS transistor P9 is required to provide a higher gate voltage to flip the comparator due to the voltage drop across the resistor 122. The resistance of the resistor 122 is calculated by mathematical derivation, and when the comparator is turned over, the currents flowing through the PMOS transistors P8 and P9 should be equal, so that:
I DP8 ＝I DP9 since the PMOS transistors P8 and P9 are both in the saturation region when the comparator is in operation, there is a
Since the PMOS transistors P8 and P9 are identical devicesAt V GSP8 ＝V GSP9 Namely, it isI D Is the current supplied by the second current source 131 if we let the positive pole of the comparator be connected to V REF The negative electrode is connected with V FB And V is FB ＝110％V REF When the comparator is turned over, then the condition to be satisfied is
If we let the positive pole of the comparator connect with V FB The negative electrode is connected with V REF And V is FB ＝90％V REF When the comparator is turned over, the conditions to be met are the same
Therefore, the comparison function of the two thresholds can be realized by only enabling the positive electrode of the comparator to be connected with the minimum value in the VFB and the VREF, and enabling the negative electrode of the comparator to be connected with the maximum value in the VFB and the VREF, and the maximum value and the minimum value selection circuit and the setting circuit in the prior art can be adopted.
The input-output plots of the circuits in fig. 2 (a) and 2 (b) are shown in fig. 2 (c).
As shown in fig. 3 (a), the delay latch unit 4 is composed of first and second nand gates 401 and 402 and a first selector 403. Two input ends of the first NAND gate 401 are respectively connected with O 2 Is connected with the output end of the second NAND gate 402; the output end of the first NAND-gate is connected with one input end of the second NAND-gate 402, and the other input end of the second NAND-gate 402 is connected with O 3 The output of the first nand gate 401 is connected to the other input terminal of the second nand gate 402, the output of the second nand gate 402 is connected to the selection terminal C of the first selector 403, and is output to the enable terminal EN2 of the oscillator 3. The first selector 403 further has two input terminals a and B, the terminal a is always connected to the high level signal V DD And B is connected with the output O of the dual-threshold comparator 1 1 The output terminal of the first selector 403 is PG (PowerGood), which is also the output of the output voltage status indication circuitA signal.
C terminal and O 1 、O 2 The logical relationship of the terminal levels is:
the truth table of the inputs and outputs of the first selector 403 is as follows:
| |
0 | 1 |
| V PG | V A | V B |
the first NAND-gate 401 and the second NAND-gate 402 form a latch unit, which can latch O 1 、 O 2 The signal from NT time. The first selector 403 is an output signal selection unit that obtains a signal describing the length of time from the latch unit, and changes the output signal PG (Power Good) beyond this time.
A circuit of another specific implementation of the delay latch unit 4 is shown in fig. 3 (b). The delay latch unit 4 is composed of first and second nor gates 411 and 412, a third inverter 413, and a second selector 414. Two input terminals of the first nor gate 411 are respectively connected with O 3 Is connected to the output of the third inverter 413; having an output connected to an input of a second nor gate 412, the second nor gate412 has another input terminal O 2 The output of the first nor gate 411 is connected to the other input terminal of the second nor gate 412, the output of the second nand gate 402 is connected to the third inverter 413, the output terminal of the third inverter 413 is connected to the selection terminal C of the second selector 414, and is output to the enable terminal EN2 of the oscillator 3. The second selector 414 further has two input terminals a and B, the terminal a is always connected to the high level signal V DD Terminal BConnected to the output O of the dual threshold comparator 1 1 The output terminal of the second selector 414 is PG (Power Good), which is also an output signal of the output voltage status indication circuit. C terminal and O 2 、O 3 The logical relationship of the terminal levels is:
the truth table of the inputs and outputs of the first selector 403 is as follows:
| |
0 | 1 |
| V PG | V A | V B |
the first and second nor gates 411 and 412 and the third inverter 413 constitute a latch unit for latching the O 2 、O 3 The signal from NT time. Second selectionThe output signal selector 414 is an output signal selecting unit that obtains a signal describing the length of time from the latch unit, and changes the output signal PG (PowerGood) beyond this time.
The following is a detailed analysis of how the overall circuit determines and indicates the chip output voltage V OUT In a state where the dual threshold comparator 1 uses either one of the circuits shown in fig. 2 (a) or (b), the delay latch unit 4 uses the circuit shown in fig. 3 (a).
Suppose that the two thresholds of the dual threshold comparator 1 are V TH - And V TH + When V is OUT Is fed back to the voltage source V FB In the range of [ V ] TH - ，V TH + ]When it is, consider V OUT Operating within the normal range. At this time, the output V of the dual threshold comparator 1 O1 =1, neither the counter 2 nor the oscillator 3 is active. Output O of counter 2 2 、O 3 Is a constant value: v O2 ＝1，V O3 =0, potential V of the selection terminal C of the first selector 403 C =1, the selected input signal is the input voltage V of the B terminal B ，V B At this time, it is high, so V PG =1, the circuit indicates that the output voltage is operating in the normal range. When the output voltage V is OUT Out of the predetermined range for some reason, i.e. V FB ＜V TH - Or V FB ＞V TH + Output O of time, dual threshold comparator 1 1 And is changed to 0. At O 1 Under the action of (1), the enable end EN of the counter 2 and the enable end EN1 of the oscillator 3 are set to be 0, the CLR end of the counter 2 simultaneously obtains descending pulses, and the counter 2 is cleared to obtain V O2 ＝0、V O3 =1, then the other enable terminal EN2 of the oscillator 3 is set to 0, the oscillator 3 starts to operate, the CLK1 outputs a continuous periodic square wave signal, and the counter 2 starts to count under the action of the periodic square wave signal. Before the counter 2 finishes one full-bit counting, namely within NT time after the chip output voltage exceeds the preset range, the chip output voltage V OUT Return to within normal range, no 2 、O 3 The original value is still kept unchanged, and the output signal PG of the delay latch unit 4 is also kept unchanged, V PG =1; if the counter 2 has completed one full-bit count, i.e. V OUT After the abnormal condition occursIn NT time, other protection circuits of the chip still cannot relieve the fault, V OUT Still outside the normal range, then O 2 、O 3 Is changed, V O2 ＝1、V O3 =0, so V C =1, first selector 403 selects B terminal signal, output voltage O of dual threshold comparator 1 1 Is output by the first selector 403, then V PG ＝V O1 ＝0。
The timing waveform diagram describing the signals of the main terminals in the above circuit is shown in fig. 4.
The axis of abscissa indicates a time axis, and the axis of ordinate indicates a potential axis of each terminal. Graph 301 represents the output voltage V of the switching power supply chip OUT ，V TH - 、V TH + Respectively representing V of our settings OUT A lower threshold and an upper threshold of a voltage normal range; plot 302 represents the output OUT of dual threshold comparator 1; graph 303 represents the periodic signal output by the output CLK1 of the oscillator 3; the graph 304 represents an output O of the counter 2 2 (ii) a The further output O of the counter 2 is indicated by a plot 305 3 (ii) a A graph 306 represents the output signal PG (PowerGood) of the output voltage status indication circuit.
At 0-t 1 Within a time interval, V OUT Within a predetermined range [ V ] TH - ，V TH + ]In, O 1 =1, oscillator 3 does not generate square wave signal, V CLK1 ＝0，V PG ＝1。
At t 1 Time of day, V OUT Out of a predetermined range [ V ] TH - ，V TH + ]The dual threshold comparator 1 detects V OUT Change of (2), output O 1 =0, oscillator 3 is enabled, output terminal CLK1 generates periodic square wave signal, CLR terminal of counter 2 is at O 1 Negative jump pulse effectNext, the counter 2 is cleared (O) 2 ＝0、 O 3 = 1), and starts counting.
At t 1 -t 2 Within a time period due to Δ T 1 ＝t 2 -t 1 < NT (N is the number of bits of counter 2, T is the square wave period), so O 2 、O 3 No change will occur. V O2 ＝0、V O3 ＝1，V C =0, selecting V A Signals input from the port, therefore V PG ＝1。
At t 2 Time of day, V OUT Returning to the normal range, the oscillator 3 stops generating the square wave signal. V O2 ＝0、V O3 ＝1，V C ＝0，V PG ＝1
At t 2 -t 3 Within a time interval, V OUT Within a predetermined range [ V ] TH - ，V TH + ]Inner, V O1 =1, oscillator 3 does not generate square wave signal, V PG ＝1。
At t 3 Time of day, V OUT Out of a preset range [ V ] TH - ，V TH + ]The dual threshold comparator 1 detects V OUT Change of (2), output V O1 =0, oscillator 3 is enabled, generating periodic square wave signal, CLR terminal of counter 2 is at O 1 The counter 2 is reset to zero (V) under the action of the negative jump pulse O1 ＝0、V O2 = 1), and starts counting. In the first selector 403, V C =0, select A end signal output, so V PG ＝1。
At t 3 -t 4 During the time interval, the counter 2 counts, since one cycle, O, is not reached 1 、O 2Remain unchanged so V PG ＝1。
At t 4 At that moment, the counter 2 counts a full cycle, i.e. Δ T 2 ＝t 4 -t 3 = NT, so V O2 ，V O3 Change occurs when V O2 ＝1、V O3 And =0. Selection terminal V of selector 403 C =1, selecting O 1 Signal, V PG ＝V O1 And =0. Enable terminal V of oscillator 3 EN2 =1, no square wave signal is generated anymore.
At t 4 -t 5 Within a time interval, V OUT Has not yet recovered to the normal range, but the counter 2 has stopped counting, V O2 ＝1、V O3 ＝0，V C ＝1。V PG ＝V O1 ＝0。
At t 5 Time of day, V OUT Reverting to the preset voltage range V TH - ，V TH + ]Output V of the dual threshold comparator 1 O1 ＝1。V O2 ＝1、V O3 ＝0。V PG ＝V O1 ＝1。
Claims (5)
1. An output voltage state indicating circuit for a power supply chip comprises a double-threshold comparator (1), a counter (2), an oscillator (3) and a delay latch unit (4); wherein,
the dual-threshold comparator (1) is used for limiting the output voltage V of the switching power supply chip OUT Range, when output voltage V OUT When the signal is between the high and low threshold values, outputting a high level signal, otherwise, outputting a low level signal;
first and second output terminals (O) of the counter (2) 2 、O 3 ) A first and a second output terminal (O) respectively connected with two terminals (IN 1, IN 2) of the delay latch unit (4) 2 、O 3 ) Always outputting a pair of opposite signals;
two input terminals of the oscillator (3) are respectively connected with an output terminal of the dual-threshold comparator (1) and a first output terminal (O) of the delay latch unit (4) 6 ) Connected to generate periodic square wave signals for the counter (2);
three input terminals of the delay latch unit (4) are respectively connected with the first and second output terminals (O) of the counter (2) 2 、O 3 ) And an output terminal (O) of the dual threshold comparator (1) 1 ) Phase (C)To its first output (O) 6 ) The enable terminal (EN 2) of the oscillator (3) is connected, and the second output end is used for outputting a voltage indication signal (PG);
the dual-threshold comparator (1) converts two input output voltage signals into current signals through differential pair transistors, and sets a window range for the output voltage; when the output voltage falls out of the window range, an oscillator (3) in the indicating circuit starts to work, a counter (2) starts to count along with a clock signal generated by the oscillator (3), if the output voltage returns to a normal range within one cycle time, an output voltage indicating signal (PG) of a delay latch unit (4) is displayed to be normal, and otherwise, the output voltage indicating signal (PG) is displayed to be abnormal.
2. The output voltage status indication circuit of claim 1, wherein: the structure of the dual-threshold comparator (1) is as follows: the grid of the PMOS tube P1 is connected with the output voltage V of the chip OUT Is fed back to the voltage source V FB The grid of the PMOS pipe P2 is connected with a reference voltage V inside the chip REF The PMOS tube P1 and the PMOS tube P2 form a differential pair circuit which is used as an input tube of the comparator; the first current source (113) provides bias current for the differential pair, and the anode of the first current source (113) is connected with V DD The negative electrode is connected with the source electrodes of the PMOS pipe P1 and the PMOS pipe P2; NMOS transistor N2 and NMOS transistor N3 are diode connected and used as load of PMOS transistor P1 and PMOS transistor P2, and drain electrode of NMOS transistor N2 is connected with PMOS transistor P1The drain electrode of the NMOS tube N3 is connected with the drain electrode of the PMOS tube P2, the NMOS tube N2 is the same as the NMOS tube N3, the NMOS tube N1 and the NMOS tube N2 form a current mirror, and the PMOS tube P3, the PMOS tube P4 and the PMOS tube P5 also form a current mirror; a current mirror composed of an NMOS tube N3, an NMOS tube N4 and an NMOS tube N5; the PMOS tube P4 and the NMOS tube N4 form a current comparison branch of the comparator, and output a low-threshold output signal O 4 And transmits the signal to a two-stage inverter pole connection unit (110); the PMOS tube P5 and the NMOS tube N5 form another current comparison branch of the comparator, and output a high-threshold output signal O 5 And transmits the signal to a three-stage inverterA member (111); the two-stage inverter pole connection unit (110) and the three-stage inverter pole connection unit (111) are used for shaping and adjusting the output phase to enable a high-threshold output signal O 5 Lags behind the low threshold output signal O 4 Phase 180 °; two output signals passing through a second-stage reverser pole connecting unit (110) and a third-stage reverser pole connecting unit (111) enter an AND gate (112) to obtain a window indicating voltage signal O 1 。
3. The output voltage status indication circuit of claim 1, wherein: the structure of the dual-threshold comparator (1) is as follows: the PMOS tube P8 and the PMOS tube P9 are the same and form a differential input tube, the source electrode of the PMOS tube P8 is connected with one end of a resistor (122), the other end of the resistor (122) is connected with a second current source (131), the source electrode of the PMOS tube P9 is connected with the negative end of the second current source (131), and the positive end of the second current source 131 is connected with V DD (ii) a The NMOS transistors N6 and N8 are in diode connection and are respectively used as drain electrode loads of PMOS transistors P8 and P9; the NMOS transistors N6 and N7 are the same, a current mirror is formed, and the current flowing through the PMOS transistor P8 is mirrored to a branch formed by the NMOS transistor N7 and the PMOS transistor P6; the NMOS transistors N8 and N9 are the same and form a current mirror, and the current flowing through the PMOS transistor P9 is mirrored to a branch formed by the NMOS transistor N9 and the PMOS transistor P7; the PMOS tube P6 and the PMOS tube P7 are the same to form a current mirror structure, and the drain current of the PMOS tube P6 is mirrored to the PMOS tube P7 and is output from the drain; the currents flowing through the PMOS tubes P8 and P9 are compared in a branch circuit formed by the PMOS tube P7 and the NMOS tube N9, and are output after being shaped by the first reverser (129) and the second reverser (130);
the positive pole of the dual-threshold comparator (1) is terminated by the minimum value of VFB and VREF, and the negative pole is terminated by the maximum value of VFB and VREF.
4. The output voltage status indication circuit according to claim 2 or 3, wherein: the structure of the delay latch unit (4) is as follows:
the delay latch unit (4) comprises a first NAND gate (401), a second NAND gate (402), a selector (403)) Forming; two input ends of the first NAND gate (401) are respectively connected with a first output terminal O of the counter 2 And an output of the second nand-gate (402); the output end of the first NAND gate is connected with one input end of a second NAND gate (402), and the other input end of the second NAND gate (402) is connected with a second output terminal O of the counter 3 The output of the first NAND gate (401) is connected with the other input end of the second NAND gate (402), the output of the second NAND gate (402) is connected to the selection end C of the selector (403) and is output to the enable end EN2 of the oscillator (3); the selector (403) has two input terminals A and B, the input terminal A is always connected with a high level signal V DD The input end B is connected with the output terminal O of the dual-threshold comparator (1) 1 The output terminal of the first selector (403) is an output voltage indication signal (PG).
5. The output voltage status indication circuit according to claim 2 or 3, wherein: the structure of the delay latch unit (4) is as follows:
the delay latch unit (4) is composed of a first NOR gate, a second NOR gate (411, 412), a third inverter (413) and a second selector (414); two input ends of the first NOR gate (411) are respectively connected with the second output terminal O of the counter 3 Is connected with the output end of the third inverter (413); the output end of the first NOR gate is connected with one input end of a second NOR gate (412), and the other input end of the second NOR gate (412) is connected with a first output end O of the counter 2 The output of the first nor gate (411) is connected with the other input end of the second nor gate (412), the output of the second and not gate (402) is connected to the third inverter (413), the output end of the third inverter (413) is connected with the selection end C of the second selector (414) and is output to the enabling end EN2 of the oscillator (3); a second selector (414) having two input terminals A and B, wherein the input terminal A is always connected with a high level signal V DD The input end B is connected with the output terminal O of the dual-threshold comparator (1) 1 The output terminal of the second selector (414) is an output voltage indication signal (PG).
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| Application Number | Priority Date | Filing Date | Title |
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| CNU2007200841799U CN201035091Y (en) | 2007-04-13 | 2007-04-13 | Output electric voltage status indication circuit used for electric power chip |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNU2007200841799U CN201035091Y (en) | 2007-04-13 | 2007-04-13 | Output electric voltage status indication circuit used for electric power chip |
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| CN201035091Y true CN201035091Y (en) | 2008-03-12 |
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| CNU2007200841799U Expired - Fee Related CN201035091Y (en) | 2007-04-13 | 2007-04-13 | Output electric voltage status indication circuit used for electric power chip |
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| CN109739710A (en) * | 2019-01-04 | 2019-05-10 | 华大半导体有限公司 | A kind of method that undervoltage detection circuit is under-voltage with detection |
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