CN201000520Y - LCD device capable of compensating stray capacity - Google Patents

Abstract

The utility model discloses a liquid crystal display device which can compensate a parasitic capacitance. The utility model comprises a gate electrode electrically connected with a gate line, and a source electrode and a drain electrode connected with a data line, wherein the source electrode appears a branch structure, and is separated by a channel and distributes at the both sides of the drain electrode. When a first metal layer and a second metal layer happen a relative moving during the manufacture procedure, the parasitic capacitances of the gate electrode-drain electrode and the gate electrode-source electrode remain unchanged, thus the problem of the scene display changing caused by the parasitic capacitance changing is avoided.

Description

But the liquid crystal indicator of compensate for parasitic capacitance

Technical field

The utility model relates to a kind of liquid crystal indicator, but particularly relates to a kind of liquid crystal indicator of compensate for parasitic capacitance.

Background technology

(liquid crystal display is a kind of flat-panel screens that is widely used most at present LCD) to LCD, has low-power consumption, external form is thin, in light weight and feature such as low driving voltage.Generally speaking, the viewing area of LCD comprises a plurality of subpixel area, each subpixel area is generally two gate line (gate line, claim sweep trace again) intersect defined rectangle or other shape area with two data lines (data line), be provided with thin film transistor (TFT) (TFT) and pixel electrode in it, thin film transistor (TFT) serves as on-off element.Form active matrix liquid crystal display by TFT is set in pixel, be fit to the liquid crystal display cells of big picture, high resolving power, many gray scales.

But along with the increase of display element picture, the raising of resolution, its picture can occur flicker inevitably, show uneven bad phenomenon such as (mura).The structural representation of traditional active matrix liquid crystal display that shown in Figure 1 is, with reference to figure 1, be provided with TFT10 and pixel electrode 20 in the pixel region that gate line 111 and data line 121 intersect, TFT10 is by grid 11, source electrode 12 and drain electrode 13 constitute, grid 11 is formed on the first metal layer (M1), source electrode 12 and drain electrode 13 are separated by raceway groove 14 and are formed on second metal level (M2), grid 11 and source electrode 12, between the drain electrode 13 semiconductor layer 30 is arranged, drain electrode 13 is connected with pixel electrode 20 by contact hole 131, dotted line is represented the situation that the first metal layer and second metal level overlap and are offset when making among the figure, and solid line is the situation of the skew that do not overlap.When the first metal layer and the second metal level generation relativity shift and since grid 11 with drain 12, the area that intersects of source electrode 13 changes, thereby cause draining-variation of grid stray capacitance Cgd and gate-to-source stray capacitance Cgs.Different Cgd can cause feedthrough

$\mathrm{\Δ}{V}_P=\frac{\mathrm{Cgd}}{\mathrm{Cgd}+C_{\mathrm{LC}}+\mathrm{Cs}}\mathrm{\ΔV}$ Different (C in the formula _LCBe the electric capacity that liquid crystal cell produces, Cs is a memory capacitance, and Δ V is the variation of voltage on the gate electrode), connect with pixel capacitance and memory capacitance owing to it again, thereby cause the pixel voltage difference, show inequality thereby produce.And for Cgs, because it links to each other with data line, it is uneven to cause data line RC to postpone, thereby also can produce demonstration inequality and film flicker phenomenon.The dotted line of Fig. 1 is depicted as the situation that the relative M2 of M1 is offset when making left; Make the juxtaposition area of gate electrode and drain electrode become big, the juxtaposition area of gate electrode and source electrode diminishes, thereby causes Cgd to diminish, and Cgs becomes big.Especially along with the increase of the picture of display element, need the graphical element of multiexposure, multiple exposure, thereby increased the probability of generating plane bias internal, caused the probability of variation of the stray capacitance of the grid of TFT and drain electrode, source electrode to increase, distributing in the face that can cause glimmering is that image evenness worsens.

The picture that produces for the variation that solves the stray capacitance that M1 and M2 relativity shift cause in this manufacturing process shows problem.China publication CN 1556437A provide a kind of LCD with capacitance compensation structure, by designing the variation that special collocation structure comes balance Cgd, though the LCD of this structure has solved the variation issue of stray capacitance Cgd, but still there are the following problems: the one, and this structure does not compensate the variation of stray capacitance Cgs, and the demonstration inequality and the film flicker phenomenon that cause thus still exist; The 2nd, the reduction that special collocation structure can cause aperture opening ratio is set, thereby causes the brightness of liquid crystal display to reduce.

Summary of the invention

The technical matters that the utility model solves provides and does not a kind ofly increase that extra collocation structure just can compensate Cgd that manufacturing process causes and variation, the picture of Cgs shows the liquid crystal indicator even, that the product yield is high.

But the utility model is achieved in that the liquid crystal indicator of compensate for parasitic capacitance and includes the gate electrode that is electrically connected with gate line, the source electrode, the drain electrode that are electrically connected with data line, wherein said source electrode is bifurcation structure, separates and is symmetrically distributed in the drain electrode both sides by raceway groove.

Described source electrode can be arranged to U type structure.

Based on above-mentioned design, but the liquid crystal indicator of compensate for parasitic capacitance of the present utility model is owing to be arranged to bifurcation structure to the source electrode, and separate by double channel and to be symmetrically distributed in electrode both sides, source, at this moment, agreing in the error of making, when relativity shift took place for metal1 and metal2, the width that the overlapping area of drain electrode and gate electrodes intersect is drain electrode multiply by the width of gate electrode, the area that intersects remains unchanged, thereby has avoided changing the demonstration inequality that causes because of Cgd.And realize self compensation by the source electrode bifurcation structure of symmetry for the variation of Cgs stray capacitance, when metal1 and metal2 relativity shift, if the source electrode of a side diminishes with the area that intersects of gate electrode, then the source electrode of opposite side and gate electrode intersects the corresponding increase of area, total intersection area remains constant, thereby also avoided changing the demonstration inequality that causes because of Cgs, and do not increase extra collocation structure, can not influence the aperture opening ratio and the brightness of liquid crystal indicator, reach picture and show evenly, raising product yield.

In order further to understand feature of the present utility model and technology contents, see also following about detailed description of the present utility model and accompanying drawing.Yet accompanying drawing is only for reference and aid illustration usefulness, does not constitute restriction of the present utility model.

Description of drawings

Fig. 1 is the planar structure synoptic diagram of the pixel region of traditional active matrix liquid crystal display, and wherein dotted line represents that M1 and M2 make the situation of the skew that overlaps, solid line represent the not overlap situation of skew;

Fig. 2 is the floor map of the pixel region of the utility model one embodiment;

Fig. 3 is that M1 and M2 make the synoptic diagram when the overlapping skew in the left and right sides takes place, and wherein dotted line represents that M1 and M2 make the situation of the skew that overlaps, solid line represent the not overlap situation of skew;

Fig. 4 is that M1 and M2 make the synoptic diagram when overlapping up and down skew takes place, and wherein dotted line represents that M1 and M2 make the situation of the skew that overlaps, solid line represent the not overlap situation of skew;

Fig. 5 is the floor map of the pixel region of another embodiment of the utility model.

Among the figure:

10. thin film transistor (TFT) (TFT) 11. grids 12. source electrodes

14. raceway grooves 13. drain

111. gate line 121. data lines 131. contact holes

20. pixel electrode 30. semiconductor layers

40. thin film transistor (TFT) (TFT) 41. gate electrodes 42. source electrodes

43. drain electrode 44. raceway grooves 45. raceway grooves

411. gate line 421. data lines 4 31. contact holes

50. pixel electrode 60. semiconductor layers

Embodiment

The utility model is described in further detail below in conjunction with accompanying drawing and exemplary embodiments.

Embodiment one

Fig. 2 is the floor map of the pixel region of present embodiment.

With reference to figure 2, but the liquid crystal indicator of compensate for parasitic capacitance includes the gate electrode 41 that is electrically connected with gate line 411, the source electrode 42 that is electrically connected with data line 421, drain electrode 43, wherein said source electrode 42 is bifurcation structure, separates and is symmetrically distributed in drain electrode 43 both sides by raceway groove 44 and 45.Be provided with TFT40 and pixel electrode 50 in the pixel region that gate line 411 and data line 421 intersect, TFT40 is by gate electrode 41, source electrode 42 and drain electrode 43 constitute, gate electrode 41 is formed on the first metal layer (not illustrating among the figure), source electrode 42 and drain electrode 43 are formed on second metal level (not illustrating among the figure), source electrode 42 is arranged to U type structure, separate by raceway groove 44 and 45 and to be symmetrically distributed in drain electrode 43 both sides, source electrode 42 both sides of U type structure are parallel with data line 421, U type bottom extension on one side along source electrode 42 is electrically connected with data line 421, gate electrode 41 and source electrode 42, have insulation course (not illustrating among the figure) and semiconductor layer 60 between the drain electrode 43, drain electrode 43 is connected with pixel electrode 50 by contact hole 431.

Fig. 3 is that M1 and M2 make the synoptic diagram when the overlapping skew in the left and right sides takes place, and wherein dotted line represents that M1 and M2 make the situation of the skew that overlaps, solid line represent the not overlap situation of skew.

With reference to Fig. 3, when M1 and the overlapping skew in the M2 making generation left and right sides, because the both sides of drain electrode 43 are raceway groove 44 and 45, the intersection area of drain electrode 43 and gate electrode 41 all is width that the width of drain electrode 43 multiply by gate electrode 41, in the permissible error of making, the area that intersects remains constant, has therefore avoided because picture demonstration inequality and the flicker problem that the variation of stray capacitance Cgd causes.

Again because source electrode 42 is symmetrically distributed in the left and right sides of drain electrode 43, when M1 and the overlapping skew in the M2 making generation left and right sides, if the intersection area of the source electrode 42 on the left side and gate electrode 41 diminishes, the then corresponding increase of intersection area of You Bian source electrode 42 and gate electrode 41, in like manner, if the intersection area of the source electrode 42 on the right and gate electrode 41 diminishes, the then corresponding increase of intersection area of the source electrode 42 on the left side and gate electrode 41, therefore the intersection total area of source electrode 42 and gate electrode 41 remains unchanged, and has also avoided showing inequality and flicker problem because of stray capacitance Cgs changes the picture that causes.

Fig. 4 is that M1 and M2 make the synoptic diagram when overlapping up and down skew takes place, and wherein dotted line represents that M1 and M2 make the situation of the skew that overlaps, solid line represent the not overlap situation of skew.

With reference to Fig. 4, when M1 and M2 make when overlapping skew up and down takes place, in the scope that process deviation allows, gate electrode 41 all remains unchanged with the area that intersects of source electrode 42, drain electrode 43, thus picture demonstration inequality and the flicker problem of having avoided the variation because of stray capacitance Cgs and Cgd to cause.

In sum, the utility model adopts so structural change of TFT to compensate M1 and M2 relativity shift in the manufacturing process and the variation of the stray capacitance that produces, do not need to increase extra collocation structure, just can reach even that picture shows, improve the product yield.In addition, the utility model can also be under the constant situation of the channel width that keeps TFT and channel length, and the channel width that increases TFT and length help improving the electrical specification of TFT than (W/L).

Embodiment two

Fig. 5 is the floor map of the pixel region of present embodiment.

With reference to Fig. 5, but the liquid crystal indicator of compensate for parasitic capacitance, the both sides up and down of source electrode 42 that wherein are U type structure are vertical with data line 421, and in the both sides of drain electrode 43, the bottom intermediate vertical is extended and is connected with data line 421 by raceway groove 44 and 45 vertical distribution; Catch up with and state the same principle of embodiment, in the error that processing procedure allows, no matter how relative overlapping skew of M1 and M2, source electrode 42, drain electrode 43 and gate electrode 41 to intersect area all constant, the picture of having avoided the variation because of stray capacitance Cgd and Cgs to cause equally shows uneven, flicker problem.

The above only is a preferred embodiment of the present utility model, and all equivalences of being done in scope of the present utility model change and modify, and all should belong to the covering scope of the utility model patent.

Claims (8)

1. but the liquid crystal indicator of a compensate for parasitic capacitance comprises:

The gate electrode that is electrically connected with gate line;

The source electrode that is electrically connected with data line;

Drain electrode;

Wherein said source electrode is bifurcation structure, separates and is symmetrically distributed in the drain electrode both sides by raceway groove.

2. liquid crystal indicator according to claim 1 is characterized in that described source electrode is U type structure.

3. liquid crystal indicator according to claim 2 is characterized in that electrode both sides, described source are parallel with data line, is electrically connected on one side extend with data line the bottom.

4. liquid crystal indicator according to claim 2 is characterized in that electrode both sides, described source are vertical with data line, and intermediate vertical extension in bottom is connected with data line.

5. liquid crystal indicator according to claim 1 is characterized in that described gate electrode is formed on the first metal layer.

6. liquid crystal indicator according to claim 1 is characterized in that described source electrode, drain electrode are formed on second metal level.

7. liquid crystal indicator according to claim 1 is characterized in that having insulation course and semiconductor layer between described gate electrode and source electrode, the drain electrode.

8. liquid crystal indicator according to claim 1 is characterized in that described drain electrode is connected with pixel electrode by contact hole.

Images