CN209912497U

CN209912497U - Digital audio signal's chronogenesis regeneration shaping device

Info

Publication number: CN209912497U
Application number: CN201920406164.2U
Authority: CN
Inventors: 丘发光; 李铭
Original assignee: Shenzhen Yuemei Mobile Science & Technology Co Ltd
Current assignee: Shenzhen Yuemei Mobile Science & Technology Co Ltd
Priority date: 2019-03-27
Filing date: 2019-03-27
Publication date: 2020-01-07
Anticipated expiration: 2029-03-27

Abstract

A timing sequence regeneration shaping device of digital audio signals mainly comprises a receiving unit, a main control unit, a phase locking unit, a timing sequence regeneration unit and a shaping unit. On one hand, the BCK signal and the LRCK signal are obtained by dividing the MCLK signal, so that the time sequence precision of the BCK signal and the LRCK signal is improved, the poor time sequence in the digital audio signal is corrected, the anti-interference capability of the digital audio signal in a complex use environment is improved, and the integrity and the stability of the digital audio signal in the transmission process are finally ensured, so that each frame of quantization information and each sound detail in the digital audio signal are truly restored with high fidelity, and the playback expressive force of a HiFi-level high-fidelity audio decoder is greatly improved; on the other hand, each unit adopts a general circuit structure or an integrated chip, so that the whole circuit structure of the device is simplified, the performance level is outstanding, the application cost is low, and the digital audio demodulation circuit is favorably applied to digital audio demodulation circuits with various formats.

Description

Digital audio signal's chronogenesis regeneration shaping device

Technical Field

The invention relates to the technical field of HiFi-level high-fidelity digital audio decoding, in particular to a timing sequence regeneration shaping device for digital audio signals.

Background

In the research field of High-Fidelity (High-Fidelity) level digital audio decoding technology, extremely High requirements are placed on the clock and time sequence synchronization precision of digital audio signals in a digital audio decoder in the transmission and demodulation process, which is a prerequisite condition for ensuring accurate decoding and accurate playback of the digital audio for High-Fidelity restoration. In the transmission and demodulation process, any flaw can seriously affect the accurate decoding and restoration of the audio signal, such as the signal source itself (in the present era, there are many devices which can be used as digital audio signal sources, such as smart phones, personal computers, tablet computers and the like) and the clock jitter problem caused by interference introduced in the transmission process, the problem of time sequence disorder and even time sequence desynchronization, the traditional digital audio playback basically depends on the physical characteristics of the existing special chip to ensure the integrity of the signal, for example, the traditional method of the digital audio transmission basically adopts the steps of modulating an I2S data stream signal into an SPDIF audio signal for transmission, then demodulating a standard I2S digital audio data stream by an SPDIF demodulation chip again, and the time sequence jitter and loss introduced in the secondary coding and decoding and SPDIF transmission processes are extremely large, thus the strict requirement of a HiFi high-fidelity audio decoder on the signal quality is strictly broken away.

In practical application, the DA chip has very high requirements on the integrity and stability of the signal source, and the higher the required timing accuracy of the digital audio signal, the higher the reducibility. When a special digital audio signal processing device is adopted, problems can be encountered, namely, the use cost is too high, and the universality of a circuit is very low, so that the cost performance of the device is poor on the whole, and even the restoration degree of a digital audio signal is not as good as that of the technical scheme of the application, so that the device is more inconvenient to generalize and apply.

Disclosure of Invention

The invention mainly solves the technical problem of how to improve the time sequence precision of the digital audio signal so as to ensure the integrity and stability of the digital audio signal in the transmission process. In order to solve the above technical problem, the present application provides a timing regeneration shaping device for a digital audio signal, comprising:

a receiving unit for acquiring a digital audio signal, the digital audio signal including a first clock signal and a DATA signal;

the main control unit is connected with the receiving unit and used for determining the response frequency of an MCLK signal according to the frequency characteristic of the first clock signal;

the phase locking unit is connected with the receiving unit and the main control unit and used for locking an oscillator to output the MCLK signal according to the response frequency when the main control unit determines the response frequency of the MCLK signal;

the time sequence regeneration unit is connected with the phase locking unit and the main control unit and is used for carrying out frequency division on the MCLK signal for multiple times when the main control unit determines that the MCLK signal is output by the phase locking unit to obtain a BCK signal and an LRCK signal;

and the shaping unit is connected with the time sequence regeneration unit and is used for passively shaping the waveforms of the MCLK signal, the BCK signal, the LRCK signal and the DATA signal and synchronously matching the shaped signals to obtain the new digital audio signal.

The main control unit controls the receiving unit to select to receive an I2S audio signal or an SPDIF audio signal; when the digital audio signal is an SPDIF audio signal, the receiving unit demodulates the I2S audio signal, and uses a frame clock signal or a bit clock signal in the I2S audio signal as the first clock signal.

The main control unit judges a preset frequency range in which the first clock signal is located according to the frequency of the first clock signal, and determines that the response frequency of the MCLK signal is 22.5792MHz, 24.576MHz, 45.1584MHz or 49.152MHz according to the preset frequency range;

the phase locking unit comprises a plurality of oscillators, and when the main control unit determines the response frequency of the MCLK signal, one of the oscillators is locked to generate a crystal oscillator signal corresponding to the response frequency to be output as the MCLK signal.

The main control unit comprises an MUTE port, and the MUTE port is used for being connected with a MUTE control end of external equipment; and the main control unit controls the external equipment to MUTE within a preset time through the MUTE port when determining the response frequency of the MCLK signal so as to avoid the popping condition caused by the MCLK signal in the step-out process.

The time sequence regeneration unit receives the MCLK signal, frequency-divides the MCLK signal for three times to obtain the BCK signal, and frequency-divides the MCLK signal for nine times to obtain the LRCK signal.

The phase locking unit further comprises a phase discriminator, the phase discriminator compares the frequency of the first clock signal output by the receiving unit with the frequency of the LRCK signal output by the time sequence regeneration unit, and frequency adjustment is performed on a locked oscillator through triggered pulse control voltage, so that the frequency of a crystal oscillator signal generated by the oscillator is consistent with the response frequency.

The shaping unit comprises a plurality of paths of passive shaping channels; and each passive shaping channel respectively carries out passive shaping on the waveforms of the MCLK signal, the BCK signal, the LRCK signal and the DATA signal, synchronously matches the shaped signals to obtain the new digital audio signal, and outputs the new digital audio signal.

The time sequence regeneration shaping device also comprises a DA converter, wherein the DA converter is connected with the shaping unit and is used for decoding the new digital audio signal output by the shaping unit to obtain an analog audio signal.

The beneficial effect of this application is:

the timing regeneration shaping device for the digital audio signal mainly comprises a receiving unit, a main control unit, a phase locking unit, a timing regeneration unit and a shaping unit, wherein the receiving unit is used for acquiring the digital audio signal, the main control unit is used for determining the response frequency of an MCLK signal according to the frequency characteristic of a first clock signal, the phase locking unit is used for locking an oscillator to output the MCLK signal according to the response frequency when the main control unit determines the response frequency of the MCLK signal, the timing regeneration unit is used for carrying out frequency division on the MCLK signal for multiple times when the main control unit determines that the phase locking unit outputs the MCLK signal to obtain an LRCK signal and an LRCK signal, and the shaping unit is used for carrying out passive shaping on the waveforms of the MCLK signal, the BCK signal, the LRCK signal and the DATA signal and carrying out synchronous matching on each shaped signal to obtain a new digital audio signal. In the first aspect, since the response frequency of the MCLK signal is determined according to the frequency of the first clock signal, the timing accuracy of the MCLK signal is greatly improved, and it is possible to correct a poor timing in the digital audio signal based on the MCLK signal; in the second aspect, the BCK signal and the LRCK signal are obtained by dividing the MCLK signal, so that the time sequence precision of the BCK signal and the LRCK signal is improved, the poor time sequence in the digital audio signal is corrected, the anti-interference capability of the digital audio signal in a complex use environment is improved, and the integrity and the stability of the digital audio signal in the transmission process are finally ensured, so that each frame of quantization information and each sound detail in the digital audio signal are truly restored with high fidelity, and the playback expressive force of the HIFI high-fidelity audio decoder is greatly improved; in a third aspect, each unit in the timing regeneration shaping device claimed in the present application adopts a general circuit structure or an integrated chip, so that the overall circuit structure of the device is simplified, the quality of the digital audio signal can be improved to the performance level of a dedicated digital audio signal processing device, and the application cost can be reduced, so that the device can be completely applied to digital audio demodulation circuits with various formats; in the fourth aspect, the phase-locked loop function of the phase-locked unit is fully utilized to accurately follow the clock frequency, and the timing sequence regeneration unit is utilized to improve the synchronization characteristic of the signal timing sequence, so that the digital audio signal itself and the timing sequence jitter caused in the transmission process are reduced by tracking and regenerating the timing sequence of the digital audio signal, the jitter or step-out phenomenon of the digital audio signal caused by the defects of the signal source and the transmission loss or interference is avoided, the decoding error rate of a subsequent decoding chip is greatly reduced, the frequency stability precision can be maintained at 1ps, the stability range reaches 25ppm to 1600ppm, the integrity of the audio signal is further improved, and the essence of the digital audio signal is fully and truly restored to the maximum extent. In the fifth aspect, the timing regeneration shaping device can be applied to the input of audio signals in low standard PCM format, or in high code rate DSD format, and can be applied to the output circuit of ADC analog-to-digital conversion in reverse to improve the timing accuracy, and can be applied to the processing of various digital audio signals.

Drawings

Fig. 1 is an overall configuration diagram of a timing regeneration shaping apparatus;

FIG. 2 is a circuit diagram of a timing regeneration shaping device according to an embodiment;

FIG. 3 is a circuit diagram of a receiving unit;

FIG. 4 is a circuit diagram of a phase lock unit;

FIG. 5 is a circuit diagram of a timing regeneration unit;

fig. 6 is a circuit schematic diagram of the shaping unit.

Detailed Description

The present invention will be described in further detail with reference to the following detailed description and accompanying drawings. Wherein like elements in different embodiments are numbered with like associated elements. In the following description, numerous details are set forth in order to provide a better understanding of the present application. However, those skilled in the art will readily recognize that some of the features may be omitted or replaced with other elements, materials, methods in different instances. In some instances, certain operations related to the present application have not been shown or described in detail in order to avoid obscuring the core of the present application from excessive description, and it is not necessary for those skilled in the art to describe these operations in detail, so that they may be fully understood from the description in the specification and the general knowledge in the art.

Furthermore, the features, operations, or characteristics described in the specification may be combined in any suitable manner to form various embodiments. Also, the various steps or actions in the method descriptions may be transposed or transposed in order, as will be apparent to one of ordinary skill in the art. Thus, the various sequences in the specification and drawings are for the purpose of describing certain embodiments only and are not intended to imply a required sequence unless otherwise indicated where such sequence must be followed.

The numbering of the components as such, e.g., "first", "second", etc., is used herein only to distinguish the objects as described, and does not have any sequential or technical meaning. The term "connected" and "coupled" when used in this application, unless otherwise indicated, includes both direct and indirect connections (couplings).

For clear understanding of the technical aspects of the present application, some technical terms will be described herein.

The I2S audio signal refers to an audio digital signal adopting an I2S (Inter-IC Sound Bus) Bus standard, where the I2S Bus standard is a Bus standard established by philips for audio data transmission between digital audio devices, and defines both a hardware interface specification and an audio digital signal format. The I2S audio signal typically includes four primary signals, an MCLK signal (i.e., a master clock signal or a system clock signal), an SCLK signal (i.e., a bit clock signal or a serial clock signal), and an LRCK signal (i.e., a frame clock signal). The MCLK signal is a reference signal of a system, and in order to enable better synchronization among the systems, the frequency of the MCLK signal is 256 times or 384 times of the sampling frequency; the LRCK signal is used to switch between left and right channel data, an LRCK of "1" indicates that left channel data is being transmitted, and an LRCK of "0" indicates that right channel data is being transmitted, and usually, the frequency of the LRCK signal is equal to the sampling frequency; each pulse of the BCK signal corresponds to each bit of data of the digital audio, and generally, the frequency of the BCK signal is 2 × sampling frequency × number of sampling bits; the DATA signal is serial DATA, typically audio DATA represented by two's complement.

The SPDIF audio signal refers to an audio Digital signal using SPDIF (Sony/Philips Digital Interface) audio Interface standard, and the S/PDIF audio Interface standard is customized by IEC61937 standard and is often used to transmit compressed audio signals, that is, the SPDIF audio signal can be regarded as a compressed modulation signal. The SPDIF audio signal may transmit various types of signals such as PCM, AC-3, DTS, or channel digital audio signals. The SPDIF digital signal may be transmitted by a coaxial cable or by an optical fiber. The SPDIF audio signal is divided into an output (SPDIF OUT) and an input (SPDIF in), and most sound card chips can support SPDIF OUT at present.

A phase-locked loop (PLL), which is a phase-locked loop, is a typical feedback control circuit, and uses an externally input reference signal to control the frequency and phase of an internal oscillation signal of the loop, so as to realize automatic tracking of an output signal frequency to an input signal frequency, and is generally used in a closed-loop tracking circuit. The phase-locked loop mainly comprises a VCO (voltage controlled oscillator) and a PLL IC (phase-locked loop integrated circuit), wherein the voltage controlled oscillator provides a signal, one part of the signal is used as an output, the other part of the signal is compared with a local oscillator signal generated by the PLL IC through frequency division, in order to keep the frequency unchanged, the phase difference is required to be unchanged, if the phase difference is changed, the voltage of a voltage output end of the PLL IC is changed, the VCO is controlled until the phase difference is recovered, and the purpose of phase locking is achieved. Therefore, a common second-order phase-locked loop (2nd PLL) is used to assist the PLL to reduce the jitter of the main clock, so as to achieve the purpose of consistent crystal oscillator frequency.

The technical solution of the present application will be described below by examples.

Referring to fig. 1, the present application provides a timing regeneration shaping device for digital audio signals, which includes a receiving unit 11, a main control unit 12, a phase-locking unit 13, a timing regeneration unit 14, and a shaping unit 15, which are respectively described below.

The receiving unit 11 is used for obtaining a digital audio signal, where the digital audio signal should include the first clock signal and the DATA signal, and the receiving unit 11 may parse the received digital audio signal to obtain the first clock signal and the DATA signal and output the two signals.

The main control unit 12 is connected to the receiving unit 11, and is configured to determine a response frequency of an MCLK signal according to a frequency characteristic of the first clock signal output by the receiving unit 11.

The phase locking unit 13 is connected to the receiving unit 11 and the main control unit 12, and is configured to lock an oscillator to output an MCLK signal according to a response frequency when the main control unit 12 determines the response frequency of the MCLK signal.

The timing regeneration unit 14 is connected to the phase locking unit 13 and the main control unit 12, and configured to perform frequency division on the MCLK signal multiple times to obtain a BCK signal and an LRCK signal when the main control unit 12 determines that the MCLK signal is output by the phase locking unit 13.

The shaping unit 15 is connected to the timing regeneration unit 14, and is configured to perform passive shaping on waveforms of the MCLK signal, the BCK signal, the LRCK signal, and the DATA signal to obtain respective shaping signals; the shaping unit 15 is further configured to perform synchronization matching on each shaped signal to obtain a new digital audio signal.

In the present embodiment, the main control unit 12 controls the reception unit 11 to select reception of the I2S audio signal or the SPDIF audio signal. Specifically, when the received digital audio signal is an SPDIF audio signal, the receiving unit 11 demodulates to obtain an I2S audio signal, and selects a frame clock signal or a bit clock signal in the I2S audio signal as the first clock signal.

It should be noted that the receiving unit 11 may receive an unmodulated I2S audio signal, may receive a modulated SPDIF audio signal, and if the signal is an SPDIF audio signal, it needs to be demodulated to obtain an I2S audio signal. Further, preferably, when the I2S audio signal is in PCM format, the receiving unit 11 parses out the frame clock signal in the I2S audio signal as the first clock signal; when the I2S audio signal is in the DSD format, the receiving unit 11 parses out the bit clock signal in the I2S audio signal as the first clock signal. It will be understood by those skilled in the art that whether the frame clock signal or the bit clock signal is used as the first clock signal, it is determined as the reference signal to generate a new MCLK signal, and the MCLK signal is divided into a new LRCK signal and a new BCK signal, so that the new MCLK signal, the LRCK signal and the BCK signal are used to replace the main clock signal, the frame clock signal and the bit clock signal in the original digital audio signal, respectively, to synthesize a completely synchronized regenerated new I2S audio signal, i.e. the synchronization is matched to obtain the new digital audio signal.

In an embodiment, please refer to fig. 2-6, which take the frame clock signal (LRCK) in the received digital audio signal as the first clock signal as an example to describe the specific circuit structure and operation principle of the timing regeneration shaping apparatus in detail.

Referring to fig. 2, the receiving unit 11 can receive the I2S audio signal and the SPDIF audio signal through the I2S port and the SPDIF port at the same time, the main control unit 12 controls one audio signal path switched by the receiving unit 11 through the I2C-1 port, so that the receiving unit 11 demodulates the audio signal path to obtain the DATA signal, the MCLK signal, the BCK signal and the LRCK signal, and outputs the DATA signal, the MCLK signal, the BCK signal and the LRCK signal through the corresponding ports.

In one embodiment, see fig. 3, the receiving unit 11 includes a signal switching and demodulating circuit, the main control unit 12 sends a selection signal through the I2C-1 port to control the signal switching and analyzing circuit to switch, selects one of the I2S audio signal and the SPDIF audio signal to demodulate, thereby obtaining the DATA signal and the LRCK signal (i.e., the frame clock signal) in the signal, and discards the demodulated main clock signal and the bit clock signal. Then, the signal switching and demodulating circuit may output the demodulated DATA signal and LRCK signal through the DATA port and the LRCK port, respectively. It should be noted that the signal switching and demodulating circuit in the present embodiment may adopt the prior art, such as an ADG413 chip, and therefore, the detailed description is not repeated here.

Referring to fig. 2, the main control unit 12 obtains the first clock signal (here, the LRCK signal) from the receiving unit 11 through the LRCK-IN port, and then the main control unit 12 determines the preset frequency range of the first clock signal according to the frequency of the first clock signal, and determines the response frequency of an MCLK signal to be 22.5792MHz, 24.576MHz, 45.1584MHz, or 49.152MHz according to the preset frequency range.

Referring to fig. 2, the phase-locking unit 13 includes a plurality of oscillators, which are respectively represented by Y1, Y2, Y3, and Y4, the crystal frequencies are respectively 22.5792MHz, 24.576MHz, 45.1584MHz, or 49.152MHz, the EN1 port, the EN2 port, the EN3 port, and the EN4 port of the main control unit 12 are respectively connected to the oscillators, and when the main control unit 12 determines the response frequency of the MCLK signal, the main control unit 12 sends an enable signal through the corresponding port to enable the corresponding oscillator, so that the phase-locking unit 13 locks one of the oscillators to generate a crystal signal corresponding to the response frequency to output as the regenerated MCLK signal. It should be noted that the oscillator in this embodiment may be a voltage-controlled oscillator, and may also be another type of oscillator, which is not limited herein.

Referring to fig. 2 and 5, phase locking unit 13 outputs the MCLK signal generated by the locked oscillator to the MCLK-IN port of timing regeneration unit 14 through the MCLK-OUT port, and main control unit 12 transmits the frequency division signal to timing regeneration unit 14 through the I2C-2 port to select a frequency division point. Then, the timing regeneration unit 14 receives the MCLK signal and the frequency-divided signal, divides the MCLK signal three times to obtain a BCK signal, and divides the MCLK signal nine times to obtain an LRCK signal, wherein the LRCK signal and the BCK signal are respectively output to the shaping unit 15 through an LRCK port and a BCK port, the MCLK signal is output through a filter resistor R, and the LRCK signal is also fed back to the phase-locking unit 13 through an LRCK-II port. It should be noted that the timing regeneration unit 14 in this embodiment may adopt an SR5340 chip, or may adopt other integrated circuits with frequency division function, which is not limited herein, and since the frequency division function belongs to the prior art, the operation principle of the timing regeneration unit is not described in detail herein.

Further, the phase locking unit 13 further includes a phase detector (not shown in the figure), which compares the frequency of the first clock signal input through the LRCK-I port with the frequency of the LRCK signal fed back through the LRCK-II port, and adjusts the frequency of the locked oscillator through the triggered pulse control voltage, so that the frequency of the crystal oscillator signal generated by the oscillator is consistent with the response frequency determined by the control unit 12.

It should be noted that, in the present embodiment, the phase locking unit 13 forms a Phase Locked Loop (PLL) by the oscillator, the phase detector, the first clock signal input through the LRCK-I port, and the LRCK signal fed back through the LRCK-II port, so that the crystal frequency of the oscillator can be accurately locked to the operating frequency band.

Further, referring to fig. 2, the main control unit 12 includes a MUTE port, which is used for connecting with a MUTE control terminal of the external device; then, the main control unit 12 controls the external device to MUTE for a preset time (e.g., 0.5s) through the MUTE port when determining the response frequency of the MCLK signal, so as to avoid a popping situation caused by the MCLK signal during the step-out. Specifically, in the process of controlling the phase-locking unit 13 to lock one of the oscillators by the main control unit 12, a short time for re-locking the frequency is provided, which often causes a short MCLK step-out phenomenon in the time, thereby causing a timing disorder, even an explosion situation, so that the control unit 12 can output a MUTE control signal to the analog amplifier circuit MUTE controller after decoding and outputting through the MUTE port and start the analog amplifier circuit MUTE controller before controlling the phase-locking unit 13 to lock the oscillator, complete the crystal frequency locking and frequency division of the oscillator in the MUTE process, and then turn off the MUTE, and usually the MUTE process is maintained for 0.5 seconds.

In a specific embodiment, as shown in fig. 4, the phase detector of the phase locking unit 13 adopts a 74HC4046 chip (may also adopt an SR5340 chip or an LMK00804 chip), which is respectively connected to the LRCK-I port and the LRCK-II port through two pins to respectively receive the input first clock signal and the fed back LRCK signal, and the frequency comparison result is output to the electronic switch through a resistor R2; the oscillators Y1-Y4 are all voltage-controlled oscillator chips, OE ports of the oscillators are respectively connected with EN1-EN4 ports of the main control unit 12, VO ports of the oscillators are respectively connected with output ports of the electronic switches, and a plurality of input ports of the electronic switches are respectively connected with OE ports of the oscillators. Thus, a phase-locked circuit is formed, and the phase discriminator continuously transmits the frequency comparison result (such as frequency difference) to the electronic switch, so that the electronic switch performs frequency adjustment on the enabled oscillator according to the frequency comparison result, and the enabled oscillator stably works in a corresponding frequency band.

It should be noted that the phase-locking unit 14 may also adopt a dedicated voltage-controlled phase-locked loop chip, and may select a voltage-controlled oscillator (VCXO) and a phase-locked loop chip with different precision levels according to the precision requirement of the product, so that the apparatus is more flexible and convenient in the application process.

Referring to fig. 6, the shaping unit 15 includes multiple passive shaping channels, each passive shaping channel performs passive shaping on waveforms of the MCLK signal, the BCK signal, the LRCK signal, and the DATA signal, respectively, to obtain respective corresponding shaping signals, so as to perform synchronous matching on each shaping signal to obtain a new digital audio signal, thereby implementing that the shaping unit 15 outputs the new digital audio signal. The passive shaping channel of the MCLK signal can be composed of a filter resistor R, the respective passive shaping channels of the DATA signal, the BCK signal and the LRCK signal can be composed of an ultra-high-speed switch diode and a resistor arranged in parallel, each passive shaping channel adopts a passive device, the influence of factors such as background noise of the active device can be avoided, waveform noise in each path of signal can be effectively eliminated, a better shaping effect is achieved, and the identification degree of the signal can be ensured. The shaping unit 14 automatically forms a new digital audio signal with excellent synchronization characteristics when synchronously outputting the MCLK signal, the BCK signal, the LRCK signal and the DATA signal, and the new digital audio signal obtained in this implementation is still an I2S DATA stream composed of the MCLK signal, the BCK signal, the LRCK signal and the DATA signal, but the I2S DATA stream has the characteristics of high precision, high stability, high fidelity, low noise and integrity, so that the audio decoding processing of subsequent decoded signals is facilitated, and each detail of the audio signal is really restored.

Further, referring to fig. 6, the timing regeneration shaping apparatus further includes a DA converter connected to the shaping unit 15, and the DA converter can decode the new digital audio signal output by the shaping unit 15 to obtain an analog audio signal, so that the analog audio signal can be transmitted through an audio cable or played through a sound playing device. Specifically, the DA converter employs a conventional digital-to-analog conversion chip, which is not limited herein.

Further, the timing sequence regeneration shaping device also comprises a control panel, and the control panel is connected with the main control unit 12, so that the functions of input switching of digital audio signals, frequency division and frequency point setting and the like are realized, and the use effect of man-machine interaction is achieved.

The receiving unit 11, the main control unit 12, the phase locking unit 13, the timing regeneration unit 14, and the shaping unit 15 disclosed in this embodiment may all adopt an existing processing chip to implement their respective functions, wherein the main control unit 1212 plays a role in controlling other units, and may adopt an existing control means or a control means appearing in the future, which is not limited herein.

When the main control unit 12 adopts the existing control means, the specific process can be described as follows: the main control unit 12 controls the receiving unit 11 to switch to obtain a path of digital audio signal, so that the receiving unit 11 demodulates the path of digital audio signal to obtain a DATA signal and a first clock signal; the main control unit 12 determines the response frequency of the new MCLK signal according to the frequency of the first clock signal (for example, the response frequencies corresponding to the frequencies of the first clock signal, such as 44.1KHz, 705KHz, 768KHz, are 22.5792MHz, 24.576MHz, 45.1584MHz, and 49.152MHz, respectively) to enable the response oscillator in the phase-locked unit 13 to start; the main control unit 12 controls the timing regeneration unit 14 to perform frequency division processing, so that the phase locking unit 14 locks the crystal oscillator frequency of the oscillator through a phase-locked loop; the shaping unit 15 automatically receives the MCLK signal, the BCK signal, the LRCK signal, and the DATA signal, thereby shaping and synchronously matching to obtain a new digital audio signal. The control means is simple, most functions are automatically realized by the existing circuit structure or the processing chip, and the control logic provided by the main control unit is simple and can be realized without creative labor of technicians.

The present invention has been described in terms of specific examples, which are provided to aid understanding of the invention and are not intended to be limiting. For a person skilled in the art to which the invention pertains, several simple deductions, modifications or substitutions may be made according to the idea of the invention.

Claims

1. An apparatus for shaping a digital audio signal for timing regeneration, comprising:

and the shaping unit is connected with the time sequence regeneration unit and is used for passively shaping the waveforms of the MCLK signal, the BCK signal, the LRCK signal and the DATA signal and synchronously matching the shaped signals to obtain a new digital audio signal.

2. The timing reproduction shaping apparatus of claim 1, wherein the main control unit controls the receiving unit to select to receive an I2S audio signal or an SPDIF audio signal; when the digital audio signal is an SPDIF audio signal, the receiving unit demodulates the I2S audio signal, and uses a frame clock signal or a bit clock signal in the I2S audio signal as the first clock signal.

3. The timing regeneration shaping device of claim 2,

4. The timing regeneration shaping device of claim 3, wherein the master unit comprises a MUTE port, the MUTE port being configured to connect to a MUTE control terminal of an external device; and the main control unit controls the external equipment to MUTE within a preset time through the MUTE port when determining the response frequency of the MCLK signal so as to avoid the popping condition caused by the MCLK signal in the step-out process.

5. The timing regeneration shaping device of claim 3, wherein the timing regeneration unit receives the MCLK signal, divides the MCLK signal three times to obtain the BCK signal, and divides the MCLK signal nine times to obtain the LRCK signal.

6. The timing regeneration shaping device according to claim 3, wherein the phase locking unit further comprises a phase detector, the phase detector compares the frequency of the first clock signal output by the receiving unit with the frequency of the LRCK signal output by the timing regeneration unit, and adjusts the frequency of the locked oscillator according to the triggered pulse control voltage, so that the frequency of the crystal oscillator signal generated by the oscillator is consistent with the response frequency.

7. The timing regeneration shaping device of any one of claims 1-6, wherein the shaping unit comprises multiple passive shaping channels;

and each passive shaping channel respectively carries out passive shaping on the waveforms of the MCLK signal, the BCK signal, the LRCK signal and the DATA signal, synchronously matches the shaped signals to obtain the new digital audio signal, and outputs the new digital audio signal.

8. The apparatus for shaping timing regeneration of claim 7, further comprising a DA converter connected to the shaping unit for decoding the new digital audio signal output by the shaping unit to obtain an analog audio signal.