CN209881742U - Programmable gain amplifying circuit, chip and electronic equipment - Google Patents
Programmable gain amplifying circuit, chip and electronic equipment Download PDFInfo
- Publication number
- CN209881742U CN209881742U CN201922070540.8U CN201922070540U CN209881742U CN 209881742 U CN209881742 U CN 209881742U CN 201922070540 U CN201922070540 U CN 201922070540U CN 209881742 U CN209881742 U CN 209881742U
- Authority
- CN
- China
- Prior art keywords
- resistor
- resistance
- selection
- operational amplifier
- module
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
Landscapes
- Amplifiers (AREA)
Abstract
The embodiment of the utility model provides a programmable gain amplifier circuit, chip and electronic equipment, wherein, programmable gain amplifier circuit includes first adjusting module, second adjusting module and programmable resistance module; the first adjusting module comprises a first operational amplifier, and the second adjusting module comprises a second operational amplifier; the programmable resistance module comprises a first selection end, a first connection end, a second selection end, a second connection end and a plurality of series resistors connected between the first connection end and the second connection end, the first selection end is connected to the inverting input end of the first operational amplifier and at least one series resistor, the first connection end is connected to the output end of the first operational amplifier, the second selection end is connected to the inverting input end of the second operational amplifier and at least one series resistor, the second connection end is connected to the output end of the second operational amplifier, and the total resistance value of the plurality of series resistors is unchanged. The utility model discloses gain linearity can be improved, the system distortion is reduced.
Description
Technical Field
The utility model relates to the field of electronic technology, concretely relates to gain amplifier circuit and chip able to programme.
Background
At present, a programmable gain amplifier usually changes a programmable resistor structure therein to realize programmable gain, for example, the programmable resistor switches different resistors through a switch to obtain different gains. However, under the configuration of different gains, the resistance value of the programmable resistor changes, which often causes the load nonlinearity between the output ends of a plurality of operational amplifiers in the programmable gain amplifier, and increases the system distortion.
SUMMERY OF THE UTILITY MODEL
In view of the above problems, the present invention provides a programmable gain amplifier circuit and a chip, which can improve the linearity of the programmable gain amplifier circuit and reduce the system distortion.
The embodiment of the utility model provides an adopt following technical scheme to realize:
a programmable gain amplifying circuit comprises a first adjusting module, a second adjusting module and a programmable resistance module; the first adjusting module comprises a first operational amplifier, and the second adjusting module comprises a second operational amplifier; the programmable resistance module comprises a first selection end, a first connection end, a second selection end, a second connection end and a plurality of series resistors connected between the first connection end and the second connection end, wherein the first selection end is connected to the inverting input end of the first operational amplifier and at least one of the series resistors, the first connection end is connected to the output end of the first operational amplifier, the second selection end is connected to the inverting input end of the second operational amplifier and at least one of the series resistors, the second connection end is connected to the output end of the second operational amplifier, and the total resistance value of the plurality of series resistors is unchanged.
Optionally, the first adjusting module further includes a first resistor, one end of the first resistor is connected to the first output end of the first operational amplifier, and the other end of the first resistor is connected to the first connection end of the programmable resistor module; the second adjusting module further comprises a second resistor, one end of the second resistor is connected to the second output end of the second operational amplifier, and the other end of the second resistor is connected to the second connecting end of the programmable resistor module.
Optionally, the programmable resistance module includes a first resistance selection module, a second resistance selection module, and a reference resistance, where the reference resistance is one of the series resistances, and the first resistance selection module and the second resistance selection module each include at least one of the series resistances; the first resistance selection module is respectively connected with the first connection end, the first selection end and the first end of the reference resistor of the first operational amplifier, and the resistance value of the first resistance selection module between the first connection end and the first selection end is variable; the second resistor selection module is respectively connected with the second connecting end, the second selection end and the second end of the reference resistor, and the resistance value of the second resistor selection module between the second connecting end and the second selection end is variable.
Optionally, the first resistance selection module includes a plurality of first switches and at least one third resistance, the second resistance selection module includes a plurality of second switches and at least one fourth resistance, the number of the third resistances is the same as the number of the fourth resistances, and the third resistance and the fourth resistance are each one of the series resistances; the third resistor is connected between the first resistor and the reference resistor, the at least one third resistor, the first resistor and the reference resistor form a first resistor string, and in the first resistor string, a connection node between every two resistors is connected to the first selection end through the first switch; the at least one fourth resistor is connected between the second resistor and the reference resistor, the at least one fourth resistor, the second resistor and the reference resistor form a second resistor string, and in the second resistor string, a connection node between every two resistors is connected to the second selection end through the second switch.
Optionally, the plurality of first switches and the plurality of second switches are symmetrical around the reference resistor, wherein the switch states of each pair of first and second switches in symmetrical relation to each other are synchronized.
Optionally, the at least one third resistor and the at least one fourth resistor are symmetrical with respect to the reference resistor as a center, the third resistor and the fourth resistor in each pair of symmetrical relationships have the same resistance, and the first resistor and the second resistor have the same resistance.
Optionally, the resistance values of any two third resistors are the same; the resistance values of any two fourth resistors are the same.
Optionally, the resistance value of the reference resistor is the same as the resistance values of the third resistor and the fourth resistor.
The embodiment of the present invention further provides a chip, which includes the programmable gain amplifier circuit as mentioned above.
Compared with the prior art, the programmable gain amplifying circuit and the chip provided by the embodiments of the present invention include a first adjusting module, a second adjusting module and a programmable resistor module, wherein the first adjusting module includes a first operational amplifier, the second adjusting module includes a second operational amplifier, the programmable resistor module includes a first selecting terminal, a first connecting terminal, a second selecting terminal, a second connecting terminal, and a plurality of series resistors connected between the first connecting terminal and the second connecting terminal, the first selecting terminal is connected to the inverting input terminal of the first operational amplifier and at least one series resistor, the first connecting terminal is connected to the output terminal of the first operational amplifier, the second selecting terminal is connected to the inverting input terminal of the second operational amplifier and at least one series resistor, the second connecting terminal is connected to the output terminal of the second operational amplifier, wherein the total resistance value of the plurality of series resistors is unchanged. Therefore, the programmable gain can be realized through the programmable resistance module, the total resistance value of the programmable resistance module depends on the total resistance values of the plurality of series resistors, and the total resistance value of the programmable resistance module is unchanged under the condition that the total resistance values of the plurality of series resistors are unchanged, so that the problem of load nonlinearity of the first operational amplifier and the second operational amplifier due to resistance value change under different gain configurations is avoided, the linearity of the programmable gain amplification circuit is improved, and system distortion is reduced.
These and other aspects of the invention will be apparent from and elucidated with reference to the embodiments described hereinafter.
Drawings
In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the drawings needed to be used in the description of the embodiments will be briefly described below, and it is obvious that the drawings in the following description are only some embodiments of the present invention, and it is obvious for those skilled in the art to obtain other drawings without creative efforts.
Fig. 1 shows a block diagram of a programmable gain amplifier circuit according to an embodiment of the present invention.
Fig. 2 shows a block diagram of a programmable gain amplifier circuit according to another embodiment of the present invention.
Fig. 3 is a schematic diagram of a programmable gain amplifier circuit according to another embodiment of the present invention.
Fig. 4 shows a block diagram of a chip provided in an embodiment of the present invention.
Detailed Description
Reference will now be made in detail to embodiments of the present invention, examples of which are illustrated in the accompanying drawings, wherein like reference numerals refer to the same or similar elements or elements having the same or similar function throughout. The embodiments described below with reference to the accompanying drawings are exemplary only for the purpose of explaining the present invention, and should not be construed as limiting the present invention.
In order to make the technical field person understand the scheme of the present invention better, the following will combine the drawings in the embodiments of the present invention to perform clear and complete description on the technical scheme in the embodiments of the present invention. It is to be understood that the embodiments described are only some embodiments of the invention, and not all embodiments. Based on the embodiments in the present invention, all other embodiments obtained by the skilled in the art without creative work belong to the protection scope of the present invention.
As shown in fig. 1, fig. 1 schematically illustrates a programmable gain amplifier circuit 100 provided in an embodiment of the present invention, where the programmable gain amplifier circuit 100 includes a first adjusting module 110, a second adjusting module 120, and a programmable resistance module 130. The first adjusting module 110 includes a first operational amplifier 111, the second adjusting module 120 includes a second operational amplifier 121, and the programmable resistance module 130 includes a first selection terminal 1311, a first connection terminal 1312, a second selection terminal 1321, a second connection terminal 1322, and a plurality of series resistors 133 connected between the first connection terminal 1312 and the second connection terminal 1322. It should be noted that the plurality of series resistors 133 includes a plurality of series resistors connected in series with each other, and each series resistor may be a single resistor or a resistor string.
Specifically, the first selection terminal 1311 is connected to the inverting input terminal of the first operational amplifier 111 and the at least one series resistor, the first connection terminal 1312 is connected to the output terminal of the first operational amplifier 111, the second selection terminal 1321 is connected to the inverting input terminal of the second operational amplifier 121 and the at least one series resistor, and the second connection terminal 1322 is connected to the output terminal of the second operational amplifier 121. Therefore, at least one series resistor may be connected between the first selection terminal 1311 and the first connection terminal 1312 and between the second selection terminal 1321 and the second connection terminal 1322, and the remaining series resistors of the plurality of series resistors 133 except the series resistor connected between the first selection terminal 1311 and the first connection terminal 1312 and the series resistor connected between the second selection terminal 1321 and the second connection terminal 1322 are referred to as gain resistors, so that the gain of the programmable gain amplifier circuit 100 may be determined by the resistances of the plurality of series resistors 133 and the gain resistors, and thus, when the number of the series resistors connected between the first selection terminal 1311 and the first connection terminal 1312 and between the second selection terminal 1321 and the second connection terminal is different, the programmable gain amplifier circuit 1322 may achieve different gains. At this time, under the configuration of different gains, since the total resistance of the programmable resistance module 130 is not changed under the condition that the total resistance of the plurality of series resistors 133 is not changed, the total resistance between the output terminal of the first operational amplifier 111 and the output terminal of the second operational amplifier 121, i.e., the operational amplifier (OP) load, is not changed, the problem of load nonlinearity of the first operational amplifier 111 and the second operational amplifier 121 due to the change of the resistance under the configuration of different gains is avoided, the linearity of the programmable gain amplification circuit is improved, and the system distortion is reduced.
In some embodiments, no MOS switch may be used in the series path connected between the output terminal of the first operational amplifier 111 and the output terminal of the second operational amplifier 121, so that the gain is not affected by the resistance of the MOS switch, and the gain accuracy is also improved.
As shown in fig. 2, fig. 2 schematically illustrates another programmable gain amplifying circuit 200 according to an embodiment of the present invention. In this embodiment, the programmable gain amplifier circuit 200 includes the first adjusting module 110, the second adjusting module 120, and the programmable resistance module 130, wherein the first adjusting module 110 further includes a first resistor R1, and the second adjusting module 120 further includes a second resistor R2. Specifically, one end of the first resistor R1 is connected to the output end of the first operational amplifier 111, and the other end of the first resistor R1 is connected to the first connection end 1312 of the programmable resistance module 130; one end of the second resistor R2 is connected to the output end of the second operational amplifier 121, and the other end of the second resistor R2 is connected to the second connection terminal 1322 of the programmable resistor module 130.
In this embodiment, the programmable resistance module 130 includes a first resistance selection module 131, a second resistance selection module 132, and a reference resistance R0. The reference resistor R0 is one of the series resistors 133, and each of the first resistor selection module 131 and the second resistor selection module 132 includes at least one of the series resistors. That is, the series resistor in the first resistor selection module 131, the reference resistor R0, and the series resistor in the second resistor selection module 132 together constitute the plurality of series resistors connected between the first connection terminal and the second connection terminal.
Specifically, the first resistor selection module 131 is respectively connected to the first connection end 1312, the first selection end 1311 and the first end of the reference resistor R0, and the resistance value of the first resistor selection module 131 between the first connection end 1312 and the first selection end 1311 is variable; the second resistor selection module 132 is connected to the second connection terminal 1322, the second selection terminal 1321 and the second terminal of the reference resistor R0, and the resistance of the second resistor selection module 132 between the second connection terminal 1322 and the second selection terminal 1321 is variable.
As an implementation manner, the first selection terminal 1311 may be controlled to be connected to all or part of or 0 series resistors in the selectable first resistor selection module 131, and the resistance value of the first resistor selection module 131 between the first selection terminal 1311 and the first connection terminal 1312 may be adjusted by adjusting the number of series resistors in the first resistor selection module 131 connected to the first selection terminal 1311. For example, the resistance value of the first resistance selection module 131 between the first selection terminal 1311 and the first connection terminal 1312 increases as the number of series resistances connected to the first selection terminal 1311 increases and decreases as the number of series resistances decreases. Accordingly, the second selection terminal 1321 may be controlled to be connected to all or a part of or 0 series resistors in the optional second resistor module 132, and the resistance value of the second resistor selection module 132 between the second selection terminal 1321 and the second connection terminal 1322 may be adjusted by adjusting the number of series resistors in the second resistor selection module 132 connected to the second selection terminal 1321. For example, the organization of the second resistance selection module 132 between the second selection terminal 1321 and the second connection terminal 1322 increases as the number of series resistances connected to the second selection terminal 1321 increases and decreases as the number of series resistances decreases.
In order to keep the total resistance between the first operational amplifier 111 and the second operational amplifier 121 constant, the series resistance between the first connection terminal 1312 and the first terminal of the reference resistor R0 of the first resistor selection module 131 is fixed, and the series resistance between the second connection terminal 1322 and the second terminal of the reference resistor R0 of the second resistor selection module 132 is fixed.
Further, in one embodiment, when the number of series resistors decreases in the first and second resistor selection modules 131 and 132, the number of series resistors connected between the inverting input terminal and the output terminal of the first operational amplifier 111 decreases, the number of series resistors connected between the inverting input terminal and the output terminal of the second operational amplifier 121 decreases, and accordingly, the number of series resistors connected between the inverting input terminal and the reference resistor of the first operational amplifier 111, which are not connected between the inverting input terminal and the output terminal of the first operational amplifier 111, increases, and the number of series resistors connected between the inverting input terminal and the reference resistor of the second operational amplifier 121, which are not connected between the inverting input terminal and the output terminal of the second operational amplifier 121, increases, among the plurality of series resistors 133. Therefore, when the resistance values of the first resistance selection module 131 and the second resistance selection module 132 are changed, the programmable gain amplification circuit 200 can achieve different gains, and since the load between the first operational amplifier 111 and the second operational amplifier 121 of the programmable gain amplification circuit 200 is always the sum of the resistance values of the first resistor R1, the second resistor R2 and the plurality of series resistors 133, the programmable gain amplification circuit 200 can achieve better linearity under different gain configurations.
In some embodiments, the resistance value R of the first resistor R1_1And the resistance R of the second resistor R2_2Are identical, i.e. R1=R2At this time, the resistance R of the first resistor selection module 131131And the resistance R of the second resistor selection module 132132Are identical, i.e. R131= R132。
At this time, as an embodiment, the first resistor selection module 131 and the second resistor selection module 132 include the same number of series resistors, and the resistance value of each series resistor is the same; as another embodiment, the first resistor selection module 131 and the second resistor selection module 132 include the number of series resistors and the resistance value of each series resistor are not identical, so that R is not identical131=R132。
Thus, it is recordedWherein R is133Is the total series resistance value of the plurality of series resistors 133. Will not be connected between the inverting input terminal and the output terminal of the first operational amplifier 111 but will be connected to the inverting input terminal and the base of the first operational amplifier 111The resistance of the series resistor between the first ends of the quasi-resistors is recorded asThe resistance value of a series resistor which is not connected between the inverting input terminal and the output terminal of the second operational amplifier 121 but connected between the inverting input terminal of the second operational amplifier 121 and the reference resistor is described asThe resistance value of the reference resistor R0 is denoted as R0Then R isBCharacterization of、And R0And (4) summing. For convenience, R is shown belowBIs a gain resistor, and the resistance value of the gain resistorThen the gain of the programmable gain amplifier circuit 200 can be determined by the following equation:
wherein GAIN represents the GAIN, and based on the formula (1), the GAIN GAIN and the GAIN resistor R of the programmable GAIN amplifier circuit 200BResistance value R ofBHas a linear relation and good linearity.
In some embodiments, the gain resistor R is made by changing the resistance values of the first resistor selection module 131 and the second resistor selection module 132BResistance value R ofBAccording to、、When the binary value is decreased, the programmable gain amplifying circuit 200 can obtain gains of 8, 16 and 32 which are changed in binary value increasing manner, so that good linearity is realized, and the adjustable range of the PGA gain is expanded without changing the resistance loads of the first operational amplifier 111 and the second operational amplifier 121 and increasing the distortion of the PGA system.
Further, in some embodiments, the first resistance selection module 131 includes a plurality of first switches and at least one third resistance, the second resistance selection module 132 includes a plurality of second switches and at least one fourth resistance, the number of the third resistances is the same as that of the fourth resistances, and each of the third resistances and each of the fourth resistances are respectively one of the plurality of series resistances 133, that is, at least one of the third resistances, the reference resistance and at least one of the fourth resistances connected in series in sequence constitute the plurality of series resistances 133. The first resistance selection module 131 may realize different resistances between the first selection terminal 1311 and the first connection terminal 1312 by controlling the turn-on number or the turn-off number of the plurality of first switches, and similarly, the second resistance selection module 132 may realize different resistances between the second selection terminal 1321 and the second connection terminal 1322 by controlling the turn-on number or the turn-off number of the plurality of second switches. Therefore, the gain resistor R can be made to have a larger gain by adjusting the on/off number of the plurality of first switches and the plurality of second switchesBResistance value R ofBVaried to achieve different gains. The number of the first switches may be 2 or any number more than 2, and the number of the third resistors may be 1 or any number more than 1, and it is understood that different numbers may achieve different gains and different linear changes.
Taking the example that the first resistor selection module 131 includes 3 first switches and two third resistors as an example, please refer to fig. 3, in which fig. 3 schematically illustrates another programmable gain amplifier circuit 300 according to an embodiment of the present invention. In this embodiment, the programmable gain amplifying circuit 300 includes the first adjusting module 110, the second adjusting module 120, the programmable resistance module 130, the first resistance selecting module 131, and the second resistance selecting module 132, and further, in this embodiment, the first resistance selecting module 131 includes a plurality of first switches and at least one third resistance, the second resistance selecting module includes a plurality of second switches and at least one fourth resistance, the number of the third resistances is the same as that of the fourth resistances, and the third resistance and the fourth resistance are respectively one of the plurality of series resistances 133.
At least one third resistor is connected between the first resistor R1 and the reference resistor R0, at least one third resistor in the first resistor selection module 131, the first resistor R1 and the reference resistor R0 form a first resistor string, and in the first resistor string, a connection node between every two resistors is connected to the first selection terminal 1311 through the first switch. At least one fourth resistor is connected between the second resistor R2 and the reference resistor R0, the at least one fourth resistor, the second resistor R2 and the reference resistor R0 form a second resistor string, and a connection node between every two resistors in the second resistor string is connected to the second selection terminal 1321 through a second switch. Thus, by closing the different first and second switches, a different number of third resistors can be connected between the inverting input terminal and the output terminal of the first operational amplifier 111, and a different number of fourth resistors can be connected between the inverting input terminal and the output terminal of the second operational amplifier 121, that is, the resistance value of the first resistor selection module 131 can be determined by the switching states of the plurality of first switches, and the resistance value of the second resistor selection module 132 can be determined by the switching states of the plurality of second switches.
In some embodiments, the first switch and the second switch may employ a field effect transistor or a triode, for example, a MOS transistor is employed for the first switch and the second switch. In one embodiment, the first switch and the second switch are NMOS transistors, gates of the NMOS transistors are connected to the driving unit, drains of the NMOS transistors are connected to an inverting input terminal of the operational amplifier, and sources of the NMOS transistors are connected to an output terminal of the operational amplifier. In another embodiment, the first switch and the second switch are PMOS transistors, gates of the PMOS transistors are connected to the driving unit, drains of the PMOS transistors can be connected to the inverting input terminal of the operational amplifier, and sources of the PMOS transistors can be connected to the output terminal of the operational amplifier. The driving unit may be a switch driving circuit receiving digital input, or may be a decoder-driver, and the like, which is not limited herein. Because the Programmable resistance adopted in the current Programmable Gain Amplifier (PGA) often sets the MOS transistor between the output ends of two Operational amplifiers (OPs), which causes the load nonlinearity between the two OP output ends, it is difficult to ensure the good linearity of the PGA, and the PGA system distortion will be increased, therefore, the present embodiment can be implemented by placing the switches in the programmable resistance module 130 between the plurality of series resistors 133 and the inverting input terminal, rather than in the plurality of series resistors 133, such that MOS switches are not used in the plurality of series resistors 133 in the programmable resistance module 130, the load between the input terminal of the first operational amplifier 111 and the input terminal of the second operational amplifier 121, i.e. the OP load, can be made independent of the resistance value of the MOS switch, therefore, the gain of the programmable gain amplifying circuit 200 is not influenced by the resistance value of the MOS switch, and the gain accuracy is improved.
As an embodiment, each of the first switch and the second switch may be connected to a switch driving circuit receiving a digital quantity input, and the switch corresponding to the number corresponding to the input number may be controlled to be closed by the digital quantity input, for example, the number 2 is input, and the switch a2 and the switch B2 in fig. 3 may be closed to gate 1 third resistor of the first resistor selection module 131 and 1 fourth resistor of the second resistor selection module 132; as another example of inputting the number 3, the switch a3 and the switch B3 in fig. 3 may be closed to gate the 2 third resistances of the first resistance selection module 131 and the 2 fourth resistances of the second resistance selection module 132.
As another embodiment, each of the first switch and the second switch may be connected to the decoding-driver, and the corresponding first switch and the corresponding second switch may be controlled to be closed by the encoded number input to the decoding-driver, so as to gate the third resistor of the first resistor selection module 131 and the fourth resistor of the second resistor selection module 132.
Further, the plurality of first switches and the plurality of second switches are symmetrical about the reference resistor R0, wherein the switching states of each pair of first and second switches in symmetrical relation to each other are synchronized. Taking fig. 3 as an example, in one embodiment, the first resistance selection module 131 and the second resistance selection module 132 respectively include three switches and two resistances, that is, the first resistance selection module 131 includes 3 first switches and two third resistances, and the second resistance selection module 132 includes 3 second switches and two fourth resistances. As shown in fig. 3, the three first switches are a switch a1, a switch a2, and a switch A3, the three second switches are a switch B1, a switch B2, and a switch B3, the two third resistors are a resistor R31 and a resistor R32, and the two fourth resistors are a resistor R41 and a resistor R42, respectively. The switch states of the switch a1 and the switch B1, which are symmetrical about the reference resistor R0, are synchronized, and similarly, the switch states of the switch a2 and the switch B2 are synchronized, and the switch states of the switch A3 and the switch B3 are synchronized. It will be understood that the switching states of the two switches are synchronized, meaning that both switches are closed or open simultaneously.
In one example, if the switches a2 and B2 are closed simultaneously, and the resistor connected between the first connection terminal 1312 and the first selection terminal 1311 in the first resistor selection module 131 is the resistor R31, the resistance R of the first resistor selection module 131 between the first connection terminal 1312 and the first selection terminal 1311 is equal to the resistance R131Equal to the resistance R of the resistor R3131. Similarly, the resistor connected between the second connection end 1322 and the second selection end 1321 in the second resistor selection module 132 is a resistor R41, and the resistance R of the second resistor selection module 132 between the second connection end 1322 and the second selection end 1321 is a resistor R132Equal to the resistance R of the resistor R4141And as shown in fig. 3, when the switches a2 and B2 are closed, the resistor R32 is connected between the first selection terminal 1311 and the reference resistor R0, but not between the first selection terminal 1311 and the first connection terminal 1312, i.e., the first selection terminal 1311 and the first connection terminal 1312 are connectedThe resistor R42 is connected between the second selection terminal 1321 and the reference resistor R0, but not between the second selection terminal 1321 and the second connection terminal 1322, i.e.At this time, the gain resistor RBIncluding resistor R32, reference resistor R0 and resistor R42, the resistance of gain resistor。
In another example, if the switches a3 and B3 are closed simultaneously, the resistor connected between the first connection terminal 1312 and the first selection terminal 1311 in the first resistor selection module 131 includes a resistor R31 and a resistor R32, and the resistance R of the first resistor selection module 131 between the first connection terminal 1312 and the first selection terminal 1311 is equal to the resistance R of the first resistor selection module 131131Equal to the sum of the resistances of resistor R31 and resistor R32. Similarly, the resistors of the second resistor selection module 132 include a resistor R41 and a resistor R42, and the resistance R of the second resistor selection module 132 between the second connection 1322 and the second selection 1321 is132Equal to the sum of the resistances of the resistor R41 and the resistor R42, and when the switches A3 and B3 are closed as shown in fig. 3, the resistor R31 and the resistor R32 are not connected between the first selection terminal 1311 and the reference resistor R0, but are connected between the first selection terminal 1311 and the first connection terminal 1312, that is, are connected between the first selection terminal 1311 and the first connection terminal 1312The resistor R41 and the resistor R42 are not connected between the second selection terminal 1321 and the reference resistor R0, but are connected between the second selection terminal 1321 and the second connection terminal 1322, i.e.At this time, the gain resistor RBIncluding reference resistor R0, the gain resistor has resistance value。
In some embodiments, the at least one third resistor and the at least one fourth resistor are symmetrical about the reference resistor R0, the third resistor and the fourth resistor have the same resistance value and the first resistor R1 and the second resistor R2 have the same resistance value. For exampleAnd is and。
further, in some embodiments, the resistance values of any two third resistors are the same, and the resistance values of any two fourth resistors are the same. At this time, the resistance of each third resistor and the resistance of each fourth resistor are the same, i.e. taking fig. 3 as an example,。
further, in some embodiments, the reference resistor R0 has the same resistance as the third and fourth resistors. At this time, the resistance of each third resistor and the resistance of each fourth resistor are the same, i.e. taking fig. 3 as an example,at this time, the resistance values of the plurality of series resistorsAnd if selected through the first resistor selection module 131A third resistor, the resistance value of the gain resistor. The gain of the programmable gain amplifier circuit 300 can now be determined by the following equation:
wherein, the resistance value R of the gain resistorBLess than the total series resistance R of the plurality of series resistors R133133I.e. by，Based on equation (2) above, the gain achievable by the programmable gain amplifier circuit 300 is based on the number of resistors gatedIs changed, good linearity is achieved. Specifically, the operation principle of the present embodiment will be described with this as an example. By controlling the switching states of the first switch and the second switch, a pair of symmetrical first switch and second switch centered on the reference resistor R0 are closed at the same time, and the first resistor selection module 131 and the second resistor selection module 132 respectively gate the same number x of resistors, at this time, there are resistors of the same number xA third resistor connected between the first selection terminal 1311 and the first connection terminal 1312, havingA fourth resistor connected between the second selection terminal 1321 and the second connection terminal 1322And equation (2) above, the GAIN of the programmable GAIN amplifier circuit 300 may be determined.
In some embodiments, the gain resistance R may be based onBAccording to、、Binary decrement, determining the number of resistors gated by the first and second resistor selection modules 131 and 132According toThe pair of first switch and second switch is turned on, so that the programmable gain amplifying circuit 200 obtains gains of 8, 16 and 32 which are in binary incremental change, good linearity is achieved, and the PGA gain adjustable range is expanded under the conditions that the resistance loads of the first operational amplifier 111 and the second operational amplifier 121 are not changed and the distortion of the PGA system is not increased.
As shown in fig. 4, the embodiment of the present invention further provides a chip 10, where the chip 10 is provided with the programmable gain amplifying circuit.
The chip 10 includes an input interface 11 and an output interface 12, where the input interface 11 is configured to receive a signal to be modulated, and the output interface 12 is configured to output the modulated signal. In one embodiment, the input interface 11 is connected to the non-inverting input of the first operational amplifier 111 and the non-inverting input of the second operational amplifier 121, and the output interface 12 is connected to the output of the first operational amplifier 111 and the output of the second operational amplifier 121. Therefore, a signal to be modulated can be received through the input interface 11, and is input to the programmable gain amplification circuit through the non-inverting input terminal of the first operational amplifier 111 and the non-inverting input terminal of the second operational amplifier 121, and the modulated signal output through the output terminal of the first operational amplifier 111 and the output terminal of the second operational amplifier 121 in the programmable gain amplification circuit is output based on the output interface 12.
The embodiment of the utility model provides a chip 10 is still provided, chip 10 is provided with above-mentioned programmable gain amplifier circuit, through the appointed quantity series resistance in a plurality of series resistance 133 of first select end 1311 and first link 1312 joinable, the same reason, through the appointed quantity series resistance in a plurality of series resistance 133 of second select end 1321 and second link 1322 joinable, make between the inverting input end and the output of first operational amplifier 111, connect the same quantity series resistance between the inverting input end and the output of second operational amplifier respectively, thereby when the quantity of the series resistance who connects changes, programmable gain amplifier circuit 10 can realize different gains. At this time, under the configuration of different gains, the total resistance of the programmable resistance module 130 is always the total resistance of the plurality of series resistors 133 in series, that is, the total resistance is not changed. Therefore, in the programmable gain amplifier circuit 10 provided in this embodiment, under different gain configurations, the total resistance of the programmable resistance module 130 is not changed, so that the problem of load nonlinearity of the first operational amplifier 111 and the second operational amplifier 121 due to resistance change under different gain configurations is avoided, the linearity of the programmable gain amplifier circuit is improved, and system distortion is reduced.
In some embodiments, no MOS switch is used in the series path connected between the output terminal of the first operational amplifier 111 and the output terminal of the second operational amplifier 121, so that the gain is not affected by the resistance of the MOS switch, and the gain accuracy is also improved.
In summary, in the programmable gain amplifier circuit and the chip of the embodiment of the present invention, the programmable gain amplifier circuit includes a first adjusting module, a second adjusting module and a programmable resistance module, wherein the first adjusting module comprises a first operational amplifier, the second adjusting module comprises a second operational amplifier, the programmable resistance module comprises a first selection end, a first connection end, a second selection end, a second connection end and a plurality of series resistors connected between the first connection end and the second connection end, the first selection end is connected to the inverting input end of the first operational amplifier, the first connection end is connected to the output end of the first operational amplifier and at least one series resistor, the second selection end is connected to the inverting input end of the second operational amplifier, and the second connection end is connected to the output end of the second operational amplifier and at least one series resistor. Therefore, the programmable gain can be realized through the programmable resistance module, the total resistance value of the programmable resistance module is unchanged and is always the total resistance value of the plurality of series resistors, so that the problem of load nonlinearity of the first operational amplifier and the second operational amplifier due to resistance value change under different gain configurations is avoided, the linearity of the programmable gain amplifying circuit is improved, and system distortion is reduced.
In an embodiment, the present invention further provides an electronic device, wherein the chip 10 or the programmable gain amplifier circuit according to any of the above embodiments is disposed in the electronic device. The electronic equipment can be electronic scales such as a weight scale and a body fat scale, or intelligent wearing products such as a bracelet, a watch and intelligent underwear, or household appliances such as a refrigerator, a floor sweeping robot, an air conditioner, a television and an intelligent closestool, or terminal equipment such as a mobile phone, a tablet personal computer, a notebook computer, a desktop computer and an upper computer, or internet of things equipment, or an earphone, an electronic cigarette, a mobile power supply and the like, and the type of the electronic equipment is not limited in the embodiment.
The above description is only a preferred embodiment of the present invention, and the present invention is not limited to the above description, and although the present invention has been disclosed by the preferred embodiment, it is not limited to the present invention, and any person skilled in the art can make modifications or changes equivalent to the equivalent embodiments by utilizing the above disclosed technical contents without departing from the technical scope of the present invention, but all the modifications, changes and changes of the technical spirit of the present invention made to the above embodiments are also within the scope of the technical solution of the present invention.
Claims (10)
1. A programmable gain amplifying circuit is characterized by comprising a first adjusting module, a second adjusting module and a programmable resistance module;
the first adjusting module comprises a first operational amplifier, and the second adjusting module comprises a second operational amplifier;
the programmable resistance module comprises a first selection end, a first connection end, a second selection end, a second connection end and a plurality of series resistors connected between the first connection end and the second connection end, wherein the first selection end is connected to the inverting input end of the first operational amplifier and at least one of the series resistors, the first connection end is connected to the output end of the first operational amplifier, the second selection end is connected to the inverting input end of the second operational amplifier and at least one of the series resistors, the second connection end is connected to the output end of the second operational amplifier, and the total resistance value of the plurality of series resistors is unchanged.
2. The programmable gain amplifier circuit according to claim 1, wherein the first adjusting module further comprises a first resistor, one end of the first resistor is connected to the output terminal of the first operational amplifier, and the other end of the first resistor is connected to the first connection terminal of the programmable resistor module;
the second adjusting module further comprises a second resistor, one end of the second resistor is connected to the output end of the second operational amplifier, and the other end of the second resistor is connected to the second connecting end of the programmable resistor module.
3. The programmable gain amplification circuit of claim 1, wherein the programmable resistance module comprises a first resistance selection module, a second resistance selection module, and a reference resistance, wherein the reference resistance is one of the series resistances, and wherein the first resistance selection module and the second resistance selection module each comprise at least one of the series resistances;
the first resistor selection module is respectively connected with the first connection end, the first selection end and the first end of the reference resistor, and the resistance value of the first resistor selection module between the first connection end and the first selection end is variable;
the second resistor selection module is respectively connected with the second connecting end, the second selection end and the second end of the reference resistor, and the resistance value of the second resistor selection module between the second connecting end and the second selection end is variable.
4. The programmable gain amplifying circuit according to claim 3, wherein the first resistance selection module comprises a plurality of first switches and at least one third resistance, the second resistance selection module comprises a plurality of second switches and at least one fourth resistance, the number of the third resistances is the same as the number of the fourth resistances, and the third resistance and the fourth resistance are each one of the series resistances;
the at least one third resistor is connected between the first resistor and the reference resistor, the at least one third resistor, the first resistor and the reference resistor form a first resistor string, and in the first resistor string, a connection node between every two resistors is connected to the first selection end through the first switch;
the at least one fourth resistor is connected between the second resistor and the reference resistor, the at least one fourth resistor, the second resistor and the reference resistor form a second resistor string, and in the second resistor string, a connection node between every two resistors is connected to the second selection end through the second switch.
5. The programmable gain amplification circuit of claim 4, wherein the plurality of first switches and the plurality of second switches are symmetrical about the reference resistance, wherein the switching states of each pair of first and second switches in symmetrical relationship to each other are synchronized.
6. The programmable gain amplifier circuit according to any of claims 2 to 5, wherein the at least one third resistor and the at least one fourth resistor are symmetrical with respect to the reference resistor as a center, each pair of the third resistor and the fourth resistor having a symmetrical relationship with each other has the same resistance, and the first resistor and the second resistor have the same resistance.
7. The programmable gain amplification circuit of claim 6, wherein any two of the third resistors have the same resistance; the resistance values of any two fourth resistors are the same.
8. The programmable gain amplifier circuit according to claim 7, wherein the reference resistor has the same resistance as the third resistor and the fourth resistor.
9. A chip comprising a programmable gain amplification circuit as claimed in any one of claims 1 to 8.
10. An electronic device comprising the chip of claim 9.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201922070540.8U CN209881742U (en) | 2019-11-27 | 2019-11-27 | Programmable gain amplifying circuit, chip and electronic equipment |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201922070540.8U CN209881742U (en) | 2019-11-27 | 2019-11-27 | Programmable gain amplifying circuit, chip and electronic equipment |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN209881742U true CN209881742U (en) | 2019-12-31 |
Family
ID=68949604
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201922070540.8U Active CN209881742U (en) | 2019-11-27 | 2019-11-27 | Programmable gain amplifying circuit, chip and electronic equipment |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN209881742U (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN114221627A (en) * | 2021-12-20 | 2022-03-22 | 上海迦美信芯通讯技术有限公司 | Circuit for improving linearity of multi-gain-level low noise amplifier by adopting load-controllable array |
-
2019
- 2019-11-27 CN CN201922070540.8U patent/CN209881742U/en active Active
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN114221627A (en) * | 2021-12-20 | 2022-03-22 | 上海迦美信芯通讯技术有限公司 | Circuit for improving linearity of multi-gain-level low noise amplifier by adopting load-controllable array |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US7088180B2 (en) | Programmable gain current amplifier | |
| EP1794882B1 (en) | Programmable low noise amplifier and method | |
| CN101420208B (en) | Variable gain amplifier including series-coupled cascode amplifiers | |
| TW200934111A (en) | Programmable gain circuit | |
| JP2003198290A (en) | Exponential function generator and variable gain amplifier using the same | |
| US6570447B2 (en) | Programmable logarithmic gain adjustment for open-loop amplifiers | |
| US6316997B1 (en) | CMOS amplifiers with multiple gain setting control | |
| US7498877B2 (en) | Power amplifier with automatic switching function | |
| US9692378B2 (en) | Programmable gain amplifier with analog gain trim using interpolation | |
| CN108664077A (en) | Current conveyor circuit, corresponding unit and method | |
| CN209881742U (en) | Programmable gain amplifying circuit, chip and electronic equipment | |
| TWI517566B (en) | Adjustable impedance circuit and impedance setting method | |
| JP2004266316A (en) | Variable gain voltage/current converting circuit, and filter circuit using the same | |
| JP2011254408A (en) | Power amplifier module and portable information terminal | |
| JPH0440020A (en) | D/a converter | |
| US20030160599A1 (en) | Controllable Current Source Assembly | |
| TWI288528B (en) | Impedance matching circuit | |
| JPH07254830A (en) | Electronic volume control circuit | |
| JPS6282704A (en) | Amplifier circuit | |
| CN102055421A (en) | Differential to single-end amplifier with gain control | |
| CN101958715B (en) | Audio digital-to-analog converter | |
| CN211786149U (en) | Detection device | |
| JPS60236509A (en) | Differential variable amplifier circuit | |
| JP4527266B2 (en) | Variable gain amplifier | |
| Tadić et al. | A low-voltage CMOS voltage-controlled resistor with wide resistance dynamic range |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| GR01 | Patent grant | ||
| GR01 | Patent grant |