CN209765366U - Band gap reference circuit with adjusting circuit - Google Patents
Band gap reference circuit with adjusting circuit Download PDFInfo
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- CN209765366U CN209765366U CN201920774611.XU CN201920774611U CN209765366U CN 209765366 U CN209765366 U CN 209765366U CN 201920774611 U CN201920774611 U CN 201920774611U CN 209765366 U CN209765366 U CN 209765366U
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- 230000001105 regulatory effect Effects 0.000 claims abstract description 15
- 101710170231 Antimicrobial peptide 2 Proteins 0.000 claims description 16
- 238000009966 trimming Methods 0.000 claims description 15
- 230000006854 communication Effects 0.000 claims description 7
- 230000002457 bidirectional effect Effects 0.000 claims description 3
- 238000004088 simulation Methods 0.000 abstract 1
- 238000010586 diagram Methods 0.000 description 10
- 230000001276 controlling effect Effects 0.000 description 3
- 239000004065 semiconductor Substances 0.000 description 2
- 230000009286 beneficial effect Effects 0.000 description 1
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Abstract
The utility model discloses a band gap reference circuit with regulating circuit, including reference voltage output vref24, still include band gap reference voltage source Bandgap, first integrated operational amplifier circuit AMP1 and regulating circuit, band gap reference voltage source Bandgap and first integrated operational amplifier circuit AMP 1's one end all links to each other with simulation power end AVDD, and the other end all links to each other with signal ground VSS for provide the electric energy for it. The utility model discloses a set up adjusting circuit, and adjusting circuit includes receiver I2C receiver and resistance series control circuit, receives the inside I2C control signal of chip through receiver I2C receiver, finally converts level control signal to, can select different resistance partial pressure points through the switch-on of control triode and turn-off, can realize providing accurate adjustable reference voltage's function for MCU (singlechip or main control chip).
Description
Technical Field
The utility model relates to a reference circuit technical field specifically is a band gap reference circuit with adjusting circuit.
Background
Today's society is highly developed with integrated circuits, and more mobile electronic products are affecting and changing people's lives. These electronic devices all require a power management system to ensure the stability of the battery supply voltage in the product, and a bandgap reference circuit is usually used in the power management system to provide an accurate and stable reference voltage. However, the reference voltage at the output end of the bandgap reference circuit is greatly influenced by the change of the ambient temperature.
Therefore, the main problem of improving the accuracy of the output reference voltage of the bandgap reference circuit is how to improve the temperature suppression thereof, i.e. how to implement a temperature-independent structure, but since the semiconductor has almost no temperature-independent parameters in reality, the current solution is generally to find some parameters with positive temperature coefficient and negative temperature coefficient, and by proper combination, the temperature-independent quantity can be obtained. However, this not only does not eliminate the temperature effect very precisely, but also requires a more complex circuit topology and a larger circuit area.
SUMMERY OF THE UTILITY MODEL
An object of the utility model is to provide a band gap reference circuit with regulating circuit, through setting up regulating circuit, and regulating circuit includes receiver I2C receiver and resistance series regulation circuit, receive the inside I2C control signal of chip through receiver I2C receiver, finally convert the level control signal into, switch-on and turn-off by this level control signal control triode can select different resistance partial pressure points, realized providing accurate adjustable reference voltage's function for MCU (singlechip or main control chip).
In order to achieve the above object, the utility model provides a following technical scheme: a band gap reference circuit with an adjusting circuit comprises a reference voltage output end vref24, a band gap reference voltage source Bandgap, a first integrated operational amplifier circuit AMP1 and an adjusting circuit, wherein one end of the band gap reference voltage source Bandgap and one end of the first integrated operational amplifier circuit AMP1 are connected with an analog power supply end AVDD, and the other end of the band gap reference voltage source Bandgap and one end of the first integrated operational amplifier circuit AMP1 are connected with a signal ground VSS and are used for providing electric energy for the analog power supply end AVDD; the output end of the Bandgap reference voltage source Bandgap is connected with the non-inverting input end of the first integrated operational amplifier circuit AMP1, and is used for providing non-inverting input voltage for the first integrated operational amplifier circuit AMP1, and the inverting input end of the first integrated operational amplifier circuit AMP1 is connected with the output end of the first integrated operational amplifier circuit AMP1 through an adjusting circuit, so as to form a first negative feedback loop, which is used for adjusting the magnitude of the output voltage of the first integrated operational amplifier circuit AMP 1; the other end of the adjusting circuit is connected with a signal ground VSS through a resistor R1, the adjusting circuit comprises a receiver I2C receiver, a decoder I2C decoder, an adjusting unit Trimming block and a resistor series adjusting circuit, and the output end of the first integrated operational amplifier AMP1 is a reference voltage output end vref 24; the output end of the band-gap reference voltage source Bandgap is connected with the bias current input end of the first integrated operational amplifier circuit AMP1 and is used for providing bias current for the first integrated operational amplifier circuit AMP 1; the Trimming block comprises a fuse cell module.
Preferably, the Bandgap reference voltage source Bandgap includes a first bias current output terminal pbias1, a second bias current output terminal pbias2, a third bias current output terminal pbias _ trim, and a fourth bias current output terminal pbias _ short, and the first bias current output terminal pbias1, the second bias current output terminal pbias2, the third bias current output terminal pbias _ trim, and the fourth bias current output terminal pbias _ short are all connected to the bias current input terminal of the first integrated operational amplifier circuit AMP 1.
preferably, the Bandgap reference voltage source Bandgap includes a 1.2V reference voltage output terminal vbg12, and the 1.2V reference voltage output terminal vbg12 is connected to the non-inverting input terminal of the first integrated operational amplifier circuit AMP 1.
Preferably, the Bandgap reference voltage source Bandgap comprises a second integrated operational amplifier circuit AMP2, and a non-inverting input terminal of the second integrated operational amplifier circuit AMP2 is connected to an output terminal of the second integrated operational amplifier circuit AMP2 through a resistor R7 to form a positive feedback loop for adjusting a voltage at the non-inverting input terminal of the second integrated operational amplifier circuit AMP 2; the inverting input end of the second integrated operational amplifier circuit AMP2 is connected with the output end of the second integrated operational amplifier circuit AMP2 through a resistor R8 to form a second negative feedback loop, and the second negative feedback loop is used for adjusting the voltage of the inverting input end of the second integrated operational amplifier circuit AMP 2; the output end of the second integrated operational amplifier circuit AMP2 is a 1.2V reference voltage output end vbg 12.
Preferably, the adjusting circuit comprises a receiver I2C receiver, an input end of the receiver I2C receiver is connected with an I2C bus, and the I2C bus comprises two bidirectional I/O communication lines, namely a serial data line SDA and a serial clock line SCL.
Preferably, the output terminal of the receiver I2C receiver is connected to a decoder I2C decoder, and the decoder I2C decoder is configured to convert the I2C control signal into a logic control signal, where the logic control signal includes five digital signals, i.e., trmdata0, trmdata1, trmdata2, trmdata3, and trmdata 4.
Preferably, an output terminal of the decoder I2C decoder is connected to an input terminal of the adjusting unit trim block, and is configured to convert the logic control signal into a level control signal, where the level control signal includes five level control signals trmout0, trmout1, trmout2, trmout3, and trmout 4.
Preferably, the output end of the adjusting unit Trimming block is connected with the input end of the resistor series adjusting circuit, and is used for adjusting the magnitude of the series resistance value of the resistor series adjusting circuit; the resistor series regulating circuit comprises a triode Q0, a triode Q1, a triode Q2, a triode Q3, a triode Q4, a resistor R0, a resistor R1, a resistor R2, a resistor R3 and a resistor R4, wherein the resistor R4 is connected with the reverse input end of the first integrated operational amplifier AMP1 through a series resistor R5.
Preferably, a resistor R0 is connected in parallel between the collector and the emitter of the transistor Q0, a resistor R1 is connected in parallel between the collector and the emitter of the transistor Q1, a resistor R2 is connected in parallel between the collector and the emitter of the transistor Q2, a resistor R3 is connected in parallel between the collector and the emitter of the transistor Q3, and a resistor R4 is connected in parallel between the collector and the emitter of the transistor Q4.
Preferably, the inverting input terminal of the first integrated operational amplifier circuit AMP1 is connected to the signal ground VSS through a resistor R6.
Compared with the prior art, the beneficial effects of the utility model are that: the utility model provides a band gap reference circuit with regulating circuit, including band gap reference voltage source Bandgap, first integrated operational amplifier circuit AMP1 and regulating circuit, regulating circuit includes receiver I2C receiver, decoder I2C decoder, adjusting unit Trimming block and resistance series circuit, wherein, receiver I2C receiver is used for receiving the inside I2C control signal of chip (wherein, receiver I2C receiver's input links to each other with I2C bus, any IC chip is supported to the I2C bus, the I2C bus includes two-way I/O communication lines of serial data line SDA and serial clock line SCL, I2C pin function through the configuration correspondence can realize I2C data two-way communication function for SDA line and serial clock line SCL); the decoder I2C decoder is used for converting an I2C control signal into a logic control signal, the adjusting unit Trimming block is used for converting the logic control signal into a level control signal, and the size of the series resistance value of the resistor series adjusting circuit is adjusted by controlling the on and off of the triode through the level control signal, so that different resistor voltage division points are selected. Therefore, the I2C control signal is transmitted through an I2C bus according to the change of the ambient temperature, and then the voltage at the vref24 point of the reference voltage output end of the band gap reference circuit is finely adjusted (the adjustment range is 2.4V +/-50 mv) by selecting different resistor voltage division points, so that the function of providing accurate and adjustable reference voltage for an MCU (single chip microcomputer or main control chip) by adapting to the change of the ambient temperature is achieved.
Drawings
Fig. 1 is a schematic circuit diagram of a bandgap reference circuit with an adjusting circuit according to the present invention;
Fig. 2 is a schematic circuit diagram of a Bandgap reference voltage source Bandgap in a Bandgap reference circuit with an adjusting circuit according to the present invention;
fig. 3 is a circuit connection diagram of the inside of the adjusting circuit in the bandgap reference circuit with the adjusting circuit according to the present invention;
Fig. 4 is a schematic circuit diagram of an adjusting unit Trimming block in the bandgap reference circuit with an adjusting circuit of the present invention;
Fig. 5 is a schematic circuit diagram of a fusecell module in a bandgap reference circuit with an adjusting circuit according to the present invention;
fig. 6 is a schematic circuit diagram of a resistor series regulating circuit in a bandgap reference circuit with an adjusting circuit according to the present invention.
Detailed Description
The technical solutions in the embodiments of the present invention will be described clearly and completely with reference to the accompanying drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only some embodiments of the present invention, not all embodiments. Based on the embodiments in the present invention, all other embodiments obtained by a person skilled in the art without creative work belong to the protection scope of the present invention.
Referring to fig. 1-6, the present invention provides an embodiment: a band gap reference circuit with an adjusting circuit comprises a reference voltage output end vref24, a band gap reference voltage source Bandgap, a first integrated operational amplifier circuit AMP1 and an adjusting circuit, wherein one end of the band gap reference voltage source Bandgap and one end of the first integrated operational amplifier circuit AMP1 are connected with an analog power supply end AVDD, and the other end of the band gap reference voltage source Bandgap and one end of the first integrated operational amplifier circuit AMP1 are connected with a signal ground VSS and are used for providing electric energy for the analog power supply end AVDD; the output end of the Bandgap reference voltage source Bandgap is connected with the non-inverting input end of the first integrated operational amplifier circuit AMP1, and is used for providing non-inverting input voltage for the first integrated operational amplifier circuit AMP1, and the inverting input end of the first integrated operational amplifier circuit AMP1 is connected with the output end of the first integrated operational amplifier circuit AMP1 through an adjusting circuit, so as to form a first negative feedback loop, which is used for adjusting the magnitude of the output voltage of the first integrated operational amplifier circuit AMP 1; the other end of the adjusting circuit is connected with a signal ground VSS through a resistor R1, the adjusting circuit comprises a receiver I2C receiver, a decoder I2C decoder, an adjusting unit Trimming block and a resistor series adjusting circuit, and the output end of the first integrated operational amplifier AMP1 is a reference voltage output end vref 24; the output end of the band-gap reference voltage source Bandgap is connected with the bias current input end of the first integrated operational amplifier circuit AMP1 and is used for providing bias current for the first integrated operational amplifier circuit AMP 1; the Trimming block comprises a fuse cell module.
Fig. 5 is a schematic circuit diagram of a fusecell module in a bandgap reference circuit with an adjusting circuit according to the present invention; in this embodiment, the Trimming block includes five fusecell blocks with the same circuit structure, which are respectively used to convert the logic control signal trmdata0 into the level control signal trmout0, convert the logic control signal trmdata1 into the level control signal trmout1, convert the logic control signal trmdata2 into the level control signal trmout2, convert the logic control signal trmdata3 into the level control signal trmout3, and convert the logic control signal trmdata4 into the level control signal trmout 4.
preferably, the Bandgap reference voltage source Bandgap includes a first bias current output terminal pbias1, a second bias current output terminal pbias2, a third bias current output terminal pbias _ trim, and a fourth bias current output terminal pbias _ short, and the first bias current output terminal pbias1, the second bias current output terminal pbias2, the third bias current output terminal pbias _ trim, and the fourth bias current output terminal pbias _ short are all connected to the bias current input terminal of the first integrated operational amplifier circuit AMP 1.
Preferably, the Bandgap reference voltage source Bandgap includes a 1.2V reference voltage output terminal vbg12, and the 1.2V reference voltage output terminal vbg12 is connected to the non-inverting input terminal of the first integrated operational amplifier circuit AMP 1.
Preferably, the Bandgap reference voltage source Bandgap comprises a second integrated operational amplifier circuit AMP2, and a non-inverting input terminal of the second integrated operational amplifier circuit AMP2 is connected to an output terminal of the second integrated operational amplifier circuit AMP2 through a resistor R7 to form a positive feedback loop for adjusting a voltage at the non-inverting input terminal of the second integrated operational amplifier circuit AMP 2; the inverting input end of the second integrated operational amplifier circuit AMP2 is connected with the output end of the second integrated operational amplifier circuit AMP2 through a resistor R8 to form a second negative feedback loop, and the second negative feedback loop is used for adjusting the voltage of the inverting input end of the second integrated operational amplifier circuit AMP 2; the output end of the second integrated operational amplifier circuit AMP2 is a 1.2V reference voltage output end vbg 12.
As shown in fig. 2, a circuit schematic diagram of a Bandgap reference voltage source Bandgap in a Bandgap reference circuit is shown, a power supply is connected to an analog power supply terminal avdd and a signal ground vss, and then, after passing through an operation circuit with a second integrated operational amplifier circuit AMP2 as a core, on one hand, an output bias current is connected to a bias current input terminal of the first integrated operational amplifier circuit AMP1, and on the other hand, an output 1.2V reference voltage is connected to a non-inverting input terminal of the first integrated operational amplifier circuit AMP 1.
FIG. 3 is a circuit diagram of the internal circuit of the adjusting circuit; the adjusting circuit comprises a receiver I2C receiver, the input end of the receiver I2C receiver is connected with an I2C bus, and the I2C bus comprises two bidirectional I/O communication lines of a serial data line SDA and a serial clock line SCL.
The I2C bus supports any IC chip, and the I2C data bidirectional communication function can be realized by configuring the corresponding I2C pin functions as SDA and SCL.
Preferably, the output terminal of the receiver I2C receiver is connected to a decoder I2C decoder, and the decoder I2C decoder is configured to convert the I2C control signal into a logic control signal, where the logic control signal includes five digital signals, i.e., trmdata0, trmdata1, trmdata2, trmdata3, and trmdata 4.
Preferably, an output terminal of the decoder I2C decoder is connected to an input terminal of the adjusting unit trim block, and is configured to convert the logic control signal into a level control signal, where the level control signal includes five level control signals trmout0, trmout1, trmout2, trmout3, and trmout 4.
Preferably, the output end of the adjusting unit Trimming block is connected with the input end of the resistor series adjusting circuit, and is used for adjusting the magnitude of the series resistance value of the resistor series adjusting circuit; the resistor series regulating circuit comprises a triode Q0, a triode Q1, a triode Q2, a triode Q3, a triode Q4, a resistor R0, a resistor R1, a resistor R2, a resistor R3 and a resistor R4, wherein the resistor R4 is connected with the reverse input end of the first integrated operational amplifier AMP1 through a series resistor R5.
Preferably, a resistor R0 is connected in parallel between the collector and the emitter of the transistor Q0, a resistor R1 is connected in parallel between the collector and the emitter of the transistor Q1, a resistor R2 is connected in parallel between the collector and the emitter of the transistor Q2, a resistor R3 is connected in parallel between the collector and the emitter of the transistor Q3, and a resistor R4 is connected in parallel between the collector and the emitter of the transistor Q4.
Preferably, the inverting input terminal of the first integrated operational amplifier circuit AMP1 is connected to the signal ground VSS through a resistor R6.
Fig. 6 shows a schematic circuit diagram of a resistor series regulator circuit, in which five level control signals trmout0, trmout1, trmout2, trmout3 and trmout4 are respectively connected to the bases of a transistor Q0, a transistor Q1, a transistor Q2, a transistor Q3 and a transistor Q4, and are used to control the on/off of the transistors by controlling the levels of the bases, so as to control the selection of different resistor voltage division points, thereby implementing a fine adjustment of the voltage at the reference voltage output terminal vref24 point of the bandgap reference circuit, and achieving a function of providing an accurate and adjustable reference voltage for an MCU (single chip microcomputer or main control chip).
The working principle is as follows: the utility model relates to a band gap reference circuit with regulating circuit, including band gap reference voltage source Bandgap, first integrated operational amplifier circuit AMP1 and regulating circuit, regulating circuit includes receiver I2C receiver, decoder I2C decoder, adjusting unit Trimming block and resistance series circuit, wherein, receiver I2C receiver is used for receiving the inside I2C control signal of chip (wherein, receiver I2C receiver's input links to each other with I2C bus, any IC chip is supported to I2C bus, I2C bus includes two-way I/O communication lines of serial data line SDA and serial clock line SCL, I2C pin function serial data line SDA and serial clock line SCL through the configuration correspondence can realize I2C data two-way communication function); the decoder I2C decoder is used for converting an I2C control signal into a logic control signal, the adjusting unit Trimming block is used for converting the logic control signal into a level control signal, and the size of the series resistance value of the resistor series adjusting circuit is adjusted by controlling the on and off of the triode through the level control signal, so that different resistor voltage division points are selected. Therefore, the I2C control signal is transmitted through an I2C bus according to the change of the ambient temperature, and then the micro-adjustment of the output voltage of the reference voltage output end vref24 of the band gap reference circuit is realized through the selection of different resistor voltage division points, so that the function of providing accurate and adjustable reference voltage for an MCU (single chip microcomputer or main control chip) is achieved.
In reality, a semiconductor has almost no temperature-independent parameter, so that the reference voltage at the output end of the band gap reference circuit is greatly influenced by the change of the ambient temperature, the band gap reference circuit with the adjusting circuit realizes the function of adjusting the reference voltage output end vref24 of the band gap reference circuit according to the change of the ambient temperature, and the adjusting range is 2.4V +/-50 mv.
In terms of hardware, the I2C bus only needs one data line and two clock lines, the bus interface is already integrated in a chip, and a special interface circuit is not needed, so that the I2C bus simplifies PCB wiring of a hardware circuit.
It is obvious to a person skilled in the art that the invention is not restricted to details of the above-described exemplary embodiments, but that it can be implemented in other specific forms without departing from the spirit or essential characteristics of the invention. The present embodiments are therefore to be considered in all respects as illustrative and not restrictive, the scope of the invention being indicated by the appended claims rather than by the foregoing description, and all changes which come within the meaning and range of equivalency of the claims are therefore intended to be embraced therein. Any reference sign in a claim should not be construed as limiting the claim concerned.
Claims (10)
1. A band gap reference circuit with an adjusting circuit comprises a reference voltage output end vref24, and is characterized by further comprising a band gap reference voltage source Bandgap, a first integrated operational amplifier circuit AMP1 and an adjusting circuit, wherein one end of the band gap reference voltage source Bandgap and one end of the first integrated operational amplifier circuit AMP1 are both connected with an analog power supply end AVDD, and the other end of the band gap reference voltage source Bandgap and one end of the first integrated operational amplifier circuit AMP1 are both connected with a signal ground VSS and are used for providing electric energy for the analog power supply end AVDD; the output end of the Bandgap reference voltage source Bandgap is connected with the non-inverting input end of the first integrated operational amplifier circuit AMP1, and is used for providing non-inverting input voltage for the first integrated operational amplifier circuit AMP1, and the inverting input end of the first integrated operational amplifier circuit AMP1 is connected with the output end of the first integrated operational amplifier circuit AMP1 through an adjusting circuit, so as to form a first negative feedback loop, which is used for adjusting the magnitude of the output voltage of the first integrated operational amplifier circuit AMP 1; the other end of the adjusting circuit is connected with a signal ground VSS through a resistor R1, the adjusting circuit comprises a receiver I2C receiver, a decoder I2C decoder, an adjusting unit Trimming block and a resistor series adjusting circuit, and the output end of the first integrated operational amplifier AMP1 is a reference voltage output end vref 24; the output end of the band-gap reference voltage source Bandgap is connected with the bias current input end of the first integrated operational amplifier circuit AMP1 and is used for providing bias current for the first integrated operational amplifier circuit AMP 1; the Trimming block comprises a fuse cell module.
2. The bandgap reference circuit with adjustment circuit of claim 1, wherein: the band gap reference voltage source Bandgap comprises a first bias current output terminal pbias1, a second bias current output terminal pbias2, a third bias current output terminal pbias _ trim and a fourth bias current output terminal pbias _ short, wherein the first bias current output terminal pbias1, the second bias current output terminal pbias2, the third bias current output terminal pbias _ trim and the fourth bias current output terminal pbias _ short are all connected with a bias current input terminal of the first integrated operational amplifier circuit AMP 1.
3. The bandgap reference circuit with adjustment circuit of claim 1, wherein: the Bandgap reference voltage source Bandgap comprises a 1.2V reference voltage output terminal vbg12, and the 1.2V reference voltage output terminal vbg12 is connected to the non-inverting input terminal of the first integrated operational amplifier circuit AMP 1.
4. The bandgap reference circuit with adjustment circuit of claim 1, wherein: the Bandgap reference voltage source Bandgap comprises a second integrated operational amplifier (AMP 2), wherein the non-inverting input end of the second integrated operational amplifier (AMP 2) is connected with the output end of the second integrated operational amplifier (AMP 2) through a resistor (R7) to form a positive feedback loop, and the positive feedback loop is used for adjusting the non-inverting input end voltage of the second integrated operational amplifier (AMP 2); the inverting input end of the second integrated operational amplifier circuit AMP2 is connected with the output end of the second integrated operational amplifier circuit AMP2 through a resistor R8 to form a second negative feedback loop, and the second negative feedback loop is used for adjusting the voltage of the inverting input end of the second integrated operational amplifier circuit AMP 2; the output end of the second integrated operational amplifier circuit AMP2 is a 1.2V reference voltage output end vbg 12.
5. The bandgap reference circuit with adjustment circuit of claim 1, wherein: the adjusting circuit comprises a receiver I2C receiver, the input end of the receiver I2C receiver is connected with an I2C bus, and the I2C bus comprises two bidirectional I/O communication lines of a serial data line SDA and a serial clock line SCL.
6. The bandgap reference circuit with adjustment circuit of claim 1, wherein: the output end of the receiver I2C receiver is connected with a decoder I2C decoder, the decoder I2C decoder is used for converting an I2C control signal into a logic control signal, and the logic control signal comprises five paths of digital signals including trmdata0, trmdata1, trmdata2, trmdata3 and trmdata 4.
7. The bandgap reference circuit with adjustment circuit of claim 1, wherein: the output terminal of the decoder I2C decoder is connected to the input terminal of the adjusting unit trim block, and is configured to convert the logic control signal into a level control signal, where the level control signal includes five level control signals trmout0, trmout1, trmout2, trmout3, and trmout 4.
8. The bandgap reference circuit with adjustment circuit of claim 1, wherein: the output end of the Trimming block of the adjusting unit is connected with the input end of the resistor series adjusting circuit and is used for adjusting the magnitude of the series resistance value of the resistor series adjusting circuit; the resistor series regulating circuit comprises a triode Q0, a triode Q1, a triode Q2, a triode Q3, a triode Q4, a resistor R0, a resistor R1, a resistor R2, a resistor R3 and a resistor R4, wherein the resistor R4 is connected with the reverse input end of the first integrated operational amplifier AMP1 through a series resistor R5.
9. The bandgap reference circuit with adjustment circuit of claim 8, wherein: a resistor R0 is connected in parallel between the collector and the emitter of the triode Q0, a resistor R1 is connected in parallel between the collector and the emitter of the triode Q1, a resistor R2 is connected in parallel between the collector and the emitter of the triode Q2, a resistor R3 is connected in parallel between the collector and the emitter of the triode Q3, and a resistor R4 is connected in parallel between the collector and the emitter of the triode Q4.
10. the bandgap reference circuit with adjustment circuit of claim 1, wherein: the inverting input terminal of the first integrated operational amplifier circuit AMP1 is connected to a signal ground VSS through a resistor R6.
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201920774611.XU CN209765366U (en) | 2019-05-27 | 2019-05-27 | Band gap reference circuit with adjusting circuit |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201920774611.XU CN209765366U (en) | 2019-05-27 | 2019-05-27 | Band gap reference circuit with adjusting circuit |
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| CN209765366U true CN209765366U (en) | 2019-12-10 |
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN111398655A (en) * | 2020-03-08 | 2020-07-10 | 苏州浪潮智能科技有限公司 | Input current detection circuit and method |
| CN111800138A (en) * | 2020-07-27 | 2020-10-20 | 中国科学院声学研究所 | Electric trimming reference voltage analog-to-digital conversion device |
-
2019
- 2019-05-27 CN CN201920774611.XU patent/CN209765366U/en not_active Expired - Fee Related
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN111398655A (en) * | 2020-03-08 | 2020-07-10 | 苏州浪潮智能科技有限公司 | Input current detection circuit and method |
| CN111398655B (en) * | 2020-03-08 | 2022-12-09 | 苏州浪潮智能科技有限公司 | Input current detection circuit and method |
| CN111800138A (en) * | 2020-07-27 | 2020-10-20 | 中国科学院声学研究所 | Electric trimming reference voltage analog-to-digital conversion device |
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Granted publication date: 20191210 |