CN209071319U - Silicon perforation interconnection structure - Google Patents
Silicon perforation interconnection structure Download PDFInfo
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- CN209071319U CN209071319U CN201821762014.7U CN201821762014U CN209071319U CN 209071319 U CN209071319 U CN 209071319U CN 201821762014 U CN201821762014 U CN 201821762014U CN 209071319 U CN209071319 U CN 209071319U
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/07—Structure, shape, material or disposition of the bonding areas after the connecting process
- H01L2224/08—Structure, shape, material or disposition of the bonding areas after the connecting process of an individual bonding area
- H01L2224/081—Disposition
- H01L2224/0812—Disposition the bonding area connecting directly to another bonding area, i.e. connectorless bonding, e.g. bumpless bonding
- H01L2224/08135—Disposition the bonding area connecting directly to another bonding area, i.e. connectorless bonding, e.g. bumpless bonding the bonding area connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
- H01L2224/08145—Disposition the bonding area connecting directly to another bonding area, i.e. connectorless bonding, e.g. bumpless bonding the bonding area connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
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Abstract
The utility model relates to technical field of semiconductors, propose a kind of silicon perforation interconnection structure, may include substrates multilayer and connecting wire；Multiple silicon perforations are provided on each layer matrix of substrates multilayer, and successively stacked offset setting is connected to silicon perforation part to each layer matrix；Connecting wire is set in silicon perforation, to be connected to the corresponding circuits on substrates multilayer.The utility model is shifted to install using matrix, so that the silicon perforation dislocation on each layer matrix connects to reach the demand of silicon perforation (TSV) wire jumper, can be made without using RDL；The silicon perforation interconnection structure yield is preferable, can reduce production time-consuming and production cost.
Description
Technical field
The utility model relates to technical field of semiconductors more particularly to a kind of silicon perforation interconnection structures.
Background technique
When saving efficiency online in valuable arrangement space or increase, silicon perforation (TSV is often used
Through Silicon Vias).Silicon perforation is a kind of vertical conduction through-hole, can be completely through the base made by silicon materials
Plate or wafer.
Silicon perforation displacement in the prior art is formed by metal wire coiling, and RDL (Re-Distribution is generally used
Layer reroutes layer) reach.
But its fabrication schedule is excessively complicated, time-consuming is made too long, cost is too high, yield is low.
Therefore, it is necessary to study a kind of new silicon perforation interconnection structures.
The above- mentioned information of the background technology part utility model are only used for reinforcing the understanding to the background of the utility model,
Therefore it may include the information not constituted to the prior art known to persons of ordinary skill in the art.
Utility model content
The purpose of the utility model is to overcome the above-mentioned prior art be made it is time-consuming too long, cost is too high, yield is low
Deficiency provides a kind of benign silicon perforation interconnection structure that is preferable, can reducing production time-consuming and production cost.
The additional aspect and advantage of the utility model will be set forth in part in the description, and partly will be from retouching
It is apparent from stating, or the practice acquistion of the utility model can be passed through.
According to one aspect of the disclosure, a kind of silicon perforation interconnection structure, comprising:
Substrates multilayer, is provided with multiple silicon perforations in each layer described matrix, and each layer described matrix successively stacked offset
Setting is connected to the silicon perforation part；
Connecting wire is set in the silicon perforation, with the corresponding circuits being connected in multilayer described matrix.
In a kind of exemplary embodiment of the disclosure, described matrix is one of wafer, chip.
In a kind of exemplary embodiment of the disclosure, the silicon perforation interconnection structure further include:
Misplace alignment mark, is set in each layer described matrix.
In a kind of exemplary embodiment of the disclosure, the dislocation alignment mark is set as two.
Spacing and adjacent two layers in a kind of exemplary embodiment of the disclosure, between two dislocation alignment marks
The dislocation distance of described matrix is identical.
In a kind of exemplary embodiment of the disclosure, the dislocation distance is more than or equal to 10 μm and is less than or equal to 60 μm.
In a kind of exemplary embodiment of the disclosure, the silicon perforation interconnection structure further include:
Substrate matrix is provided with multiple connection conductors, and the substrate matrix is shifted to install with multilayer described matrix to be made
The connection conductor connection corresponding with the connecting wire.
In a kind of exemplary embodiment of the disclosure, the substrate matrix is wafer or chip.
In a kind of exemplary embodiment of the disclosure, the silicon perforation interconnection structure further include:
Slide glass, set on the one side of the separate described matrix of the substrate matrix.
As shown from the above technical solution, the utility model has at least one of following advantages and good effect:
The silicon perforation interconnection structure of the utility model, may include substrates multilayer and connecting wire；It is all provided on each layer matrix
Multiple silicon perforations are equipped with, and successively stacked offset setting is connected to silicon perforation part to each layer matrix；Connecting wire is set to silicon perforation
It is interior, to be connected to the corresponding circuits on substrates multilayer.On the one hand, the utility model shifting to install using matrix, so that each layer base
Silicon perforation dislocation on body connects to reach the demand of silicon perforation (TSV) wire jumper, can be made without using RDL, improve and partly lead
Speed is made in body device, on the other hand, due to not being made using RDL, reduces multiple RDL yellow light, output semiconductor devices
Yield it is higher, while reducing that production is time-consuming and production cost.
Detailed description of the invention
Its example embodiment is described in detail by referring to accompanying drawing, above and other feature and advantage of the utility model will
It becomes readily apparent from.
Fig. 1 is the schematic diagram of silicon perforation interconnection structure in the related technology；
Fig. 2 is the schematic diagram of silicon perforation interconnection structure in a kind of embodiment of the utility model；
Fig. 3 is the schematic diagram of silicon perforation interconnection structure in the utility model another embodiment；
Fig. 4 is the structural schematic diagram of substrate matrix in Fig. 2；
Fig. 5 is the structural schematic diagram of matrix；
Fig. 6 is that structural schematic diagram after carrier is formed on the basis of Fig. 5；
Fig. 7 is that mill sells structural schematic diagram after silicon substrate on the basis of Fig. 6；
Fig. 8 is the schematic diagram of the utility model dislocation alignment mark；
Fig. 9 is the structure chart after the utility model matrix is connect with substrate matrix；
Figure 10 is the structural schematic diagram removed after carrier on the basis of Fig. 8；
Figure 11 is the flow diagram of silicon perforation interconnection structure preparation method；
Figure 12 is the flow diagram of another silicon perforation interconnection structure preparation method；
Figure 13 is the schematic diagram of silicon perforation interconnection structure after slide glass is arranged；
Figure 14 be matrix be chip when, the schematic diagram of silicon perforation interconnection structure.
The reference numerals are as follows for main element in figure:
1, layer is rerouted；2, silicon perforation；3, conductor is connected；4, first material layer；5, substrate；6, substrate matrix；7, matrix；
701, chip；8, roof carrier；9, the first dislocation alignment mark；10, the second dislocation alignment mark；11, connecting wire；12, it carries
Piece；N, dislocation distance；M, spacing.
Specific embodiment
Example embodiment is described more fully with reference to the drawings.However, example embodiment can be with a variety of shapes
Formula is implemented, and is not understood as limited to embodiment set forth herein；On the contrary, thesing embodiments are provided so that this is practical new
Type will be full and complete, and the design of example embodiment is comprehensively communicated to those skilled in the art.It is identical in figure
Appended drawing reference indicates same or similar structure, thus the detailed description that will omit them.
The schematic diagram of silicon perforation interconnection structure in the related technology shown in referring to Fig.1, silicon perforation is displaced in the related art
It is to be formed by wire coiling, generally requires RDL (rerouting layer 1) and reach, manufacturing process is complex, the time needed
With regard to more, and higher cost, yield are lower.
The utility model provides a kind of silicon perforation interconnection structure, shows referring to Fig. 2 the utility model silicon perforation interconnection structure
It is intended to, silicon perforation interconnection structure may include substrates multilayer 7 and substrate matrix 6；Multiple silicon perforations are provided on each layer matrix 7
2, and each layer matrix 7 successively shift to install make silicon perforation 2 dislocation connection；Connecting wire 11 is set in silicon perforation 2, to be connected to multilayer
Corresponding circuits on matrix.
In this example embodiment, the material of connecting wire 11 may include the relevant episodes such as copper, polysilicon and tungsten metal
At circuit conductive material；Silicon perforation 2 (TSV) outer layer insulation material may include that the integrated circuit related with same such as silica, silicon nitride are exhausted
Edge material.
In this example embodiment, referring to Fig. 4 and Fig. 5, silicon perforation interconnection structure may include substrate matrix 6 and matrix
7, substrate matrix 6 may include substrate 5 and first material layer 4, and 4 upper surface of first material layer is provided with multiple connection conductors 3, base
The material of plate can be silicon, i.e. substrate 5 is silicon substrate；In another embodiment, the material of substrate can also be semiconductor or
Person's insulator；Such as glass.It is not specifically limited in this example embodiment.
In this example embodiment, referring to Fig. 4, matrix 7 may include substrate 5, first material layer 4, connection 3 and of conductor
Multiple silicon perforations 2；Substrate 5 can be silicon substrate；The silicon perforation 2 runs through matrix 7.
In this example embodiment, referring to shown in Fig. 4 and Fig. 5, matrix 7 can be upper layer wafer, on every layer of matrix 7
Multiple connection conductors 3 can be set, multiple connection conductors 3 on matrix can be divided into two regions, left area and right side
Region.Left area is set there are four conductor 3 is connected, and four connection conductors 3 are uniformly distributed, and right area also is provided with four connections and leads
Body 3, four connection conductors 3 are uniformly distributed.Interval in each region between two neighboring connection conductor 3 is identical, two regions
Between there are a biggish intervals.In another example embodiment, 3 quantity of connection conductor in each region can be three
It is a, five or more.It is not particularly limited in this example embodiment.
Referring to Fig. 5, connection conductor 3 is formed in first material layer 4, and not prominent and first material layer 4.Silicon perforation 2 with
Connection conductor 3, which can be, to be vertically arranged, corresponding, and connecting wire 11 is also to be vertically arranged with conductor 3 is connect, so that each layer
Matrix 7, which successively shifts to install, makes the dislocation connection of silicon perforation 2.Certainly, silicon perforation 2 can also be arranged with conductor 3 is connect with out of plumb, it
It wants to achieve the purpose that so that each layer matrix 7, which successively shifts to install, makes the dislocation connection of silicon perforation 2, in this example embodiment party
It is not specifically limited in formula.
In a kind of example embodiment, referring to shown in Fig. 8, the schematic diagram of the utility model dislocation alignment mark, silicon is worn
Hole interconnection structure can also include dislocation alignment mark, and the same position of each layer matrix 7 is arranged in, and dislocation alignment mark can be set
It is set to two, the first dislocation alignment mark 9 misplaces alignment mark 10 with second；Also it can be set more, in the present embodiment
It is not specifically limited.In another embodiment, a dislocation alignment mark can be only set, be arranged apart from matrix side one
Determine at dislocation distance, when carrying out dislocation bonding, it is only necessary to be aligned the side of another matrix i.e. with the dislocation alignment mark
It can.In a further embodiment, it can also be not provided with dislocation alignment mark, calculating is utilized when substrates multilayer carries out dislocation bonding
Machine controls, and makes to generate certain dislocation distance N between substrates multilayer.
Spacing M and adjacent two referring to shown in Fig. 8, between the first dislocation alignment mark 9 and the second dislocation alignment mark 10
Layer matrix 7 dislocation distance N it is identical, in this way positioning when only need by the dislocation of two neighboring matrix 7 to chase after label dislocation pair
It is neat, for example, the first dislocation alignment mark 9 of matrix 7 is aligned with the second dislocation alignment mark 10 of substrate matrix 6.Setting
Dislocation alignment mark can make more accurate when carrying out the bonding of substrates multilayer 7.
In this example embodiment, dislocation distance N can be more than or equal to 10 μm and be less than or equal to 60 μm；Corresponding first
The spacing M between alignment mark 9 and the second dislocation alignment mark 10 that misplaces can also be more than or equal to 10 μm and be less than or equal to 60 μm.
In this example embodiment, referring to shown in Fig. 8, the first dislocation alignment mark 9 can be cross-shaped structure, and second
Dislocation alignment mark 10 is also possible to cross-shaped structure, and the shape of two dislocation alignment marks can be triangle, is carrying out pair
Corresponding angle mutual dislocation is aligned on time；Certainly, misplace alignment mark shape can also be rectangle, pentagon or
Hexagon etc., is not specifically limited in the present embodiment.
In this example embodiment, referring to shown in Fig. 2, silicon perforation interconnection structure can be made of four layers of matrix, can also
To be made of more layers matrix, the number of plies of matrix is not specifically limited in the present embodiment, and each layer matrix shifts to install, dislocation
Mode can be successively deviates to the right identical dislocation distance N from bottom to top.Allow 2 phase of silicon perforation on each layer matrix 7
Mutually dislocation connection, while the connecting wire 11 being set in silicon perforation 2 can also be dislocated and connected to each other.In each 7 first material of layer matrix
The bed of material 4 is equipped with connection conductor 3.Connection conductor 3 can make the circuit connection between each layer matrix 7 relatively reliable.
Referring to shown in Fig. 2, silicon perforation 2 is opened up on the substrates multilayer 7 after above-mentioned bonding bonding, from above-mentioned connection conductor 3
Central location opens up silicon perforation 2, runs through substrates multilayer 7.It is silicon perforation 2 through one layer of matrix 7, partial region silicon in partial region
Perforation 2 runs through substrates multilayer 7 through two layers of matrix 7, also partial region silicon perforation 2.For example, in Tu2Zhong top layer close to most
Silicon perforation 2 of right side run through one layer of matrix 7.Every layer of 7 leftmost side of matrix has a connection conductor 4 not and set on silicon perforation 2
Interior connecting wire 11 connects, and such structure can play preferable heat spreading function to a certain extent.
Certainly, in another embodiment, referring to Fig. 3, dislocation mode may be set to be or so offset is alternate, for example,
Second layer matrix counter substrate matrix 6 deviates to the right, and third layer matrix deviates to the left relative to second layer matrix, i.e., odd-level is mutual
Alignment, even level are also mutually aligned.Form the silicon perforation 2 for running through substrates multilayer 7.On the one hand, occurring compared with substrates multilayer 7 being to account for
With less area；On the other hand, using vertically setting up, stable structure is not easy to collapse.
Referring to Fig.1 shown in 3, silicon perforation displacement structure can also include slide glass 12, form substrate matrix 6 on slide glass 12,
Matrix 7 is formed on substrate matrix 6；The material of slide glass 12 can be semiconductor or insulator；Such as glass, silicon plate etc..
Base in another example embodiment of the utility model, referring to Fig.1 shown in 4, in the silicon perforation interconnection structure
Body 7 can also be chip 701；Chip 701 is formed on substrate matrix 6；Successively stacked offset is set chip 701 with substrate matrix 6
It sets to form silicon perforation interconnection structure.Chip 701 may include substrate 5, first material layer 4, connection conductor 3 and silicon perforation 2；Substrate
5, first material layer 4, connection conductor 3 and silicon perforation 2 is described above that detaileds description has been carried out, therefore go out no longer go to live in the household of one's in-laws on getting married at this time
It states.
Certainly, in the present embodiment, silicon perforation interconnection structure also may include slide glass 12, form substrate base on slide glass 12
Body 6 forms chip 701 on substrate matrix 6；The material of slide glass 12 can be semiconductor or insulator；Such as glass, silicon plate
Deng.
Further, the utility model additionally provides a kind of preparation method corresponding to above-mentioned silicon perforation interconnection structure；Ginseng
According to shown in Figure 11, which be may comprise steps of:
Step S110, provides substrates multilayer, and multiple silicon perforations 2 are formed in each layer described matrix.
Step S120 forms connecting wire 11 in the silicon perforation 2.
Step S130 successively misplaces multilayer described matrix bonding, keeps the dislocation of connecting wire 11 connection more to be connected to
Corresponding circuits in layer described matrix.
Each step of the preparation method of the silicon perforation interconnection structure is described in detail below:
In step s 110, substrates multilayer is provided, forms multiple silicon perforations in each layer described matrix.
In the step s 120, connecting wire 11 is formed in the silicon perforation 2.
In this example embodiment, connecting wire 11 is set in silicon perforation 2 referring to Fig. 5, and by silicon perforation 2 and conducting wire
Bonding, the material of connecting wire 11 may include the integrated circuit related with same conductive material such as copper and tungsten metal.
Referring to Fig. 5, matrix 7 may include substrate 5, first material layer 4, connection conductor 3 and multiple silicon perforations 2；Substrate 5 can
To be silicon substrate, which runs through matrix.
In step s 130, multilayer described matrix is successively misplaced bonding, makes the dislocation of connecting wire 11 connection to connect
Corresponding circuits in logical multilayer described matrix.
Firstly, roof carrier 8 is formed on matrix 7 by bonding pattern, referring to shown in Fig. 6 to prevent subsequent
It is relatively thin and generate warpage to carry out matrix when matrix grinding, above-mentioned bonding pattern is interim bonding.
Then, referring to shown in Fig. 7, the back side of substrate 5 carries out being thinned to the exposing of connecting wire 11 so that it is described above not
The silicon perforation opened completely is completely open-minded.Matrix 7 and substrate matrix 6Chip bonding (piece welding) or Hybrid bonding
(hybrid bonded), and it is aligned the first dislocation alignment mark 9 of matrix with the second dislocation alignment mark of substrate matrix 6, so that
The connection conductor 3 that the connecting wire 11 that matrix 7 is equipped with can be equipped with substrate matrix 6 is connect.
Finally, roof carrier 8 is carried out to tear bonding open, exposes and connects conductor 3 at the top of matrix 7 referring to shown in Fig. 9.Tear bonding open
Method there is chemistry to tear bonding open, machinery tears bonding open, UV tear open bonding etc..
In this example embodiment, referring to shown in Fig. 2, repeatedly implements the step in above-described embodiment, can be formed more
2 structure of silicon perforation of layer structure, 2 structure of silicon perforation can be made of four layers of matrix, be also possible to be made of two layers or three layers, also
It can be and be made of more layers matrix, is not specifically limited in the present embodiment.
In this example embodiment, each layer matrix 7 is shifted to install, and dislocation mode can be from bottom to top successively to right avertence
Move identical dislocation distance N.Silicon perforation 2 on each layer matrix 7 is dislocated and connected to each other, while being set in silicon perforation 2
Connecting wire 11 can also be dislocated and connected to each other.Connection conductor 3 is equipped in each 7 upper surface of layer matrix.Connecting conductor 3 can be with
So that the circuit connection between each layer matrix 7 is safer.
Certainly, in another embodiment, referring to Fig. 3, dislocation mode may be set to be or so offset is alternate, for example,
Second layer matrix counter substrate matrix 6 deviates to the right, and third layer matrix deviates to the left relative to second layer matrix, i.e., odd-level is mutual
Alignment, even level are also mutually aligned.Design is occurring being to occupy less area compared with substrates multilayer 7 in this way, vertically sets up, is not easy down
It collapses, stable structure.
In a kind of example embodiment, referring to shown in Fig. 8, the schematic diagram of the utility model dislocation alignment mark, silicon is worn
2 structure of hole can also include dislocation alignment mark, and the same position of each layer matrix 7 is arranged in, and dislocation alignment mark can be set
It is two, the first dislocation alignment mark 9 and the second dislocation alignment mark 10；Also it can be set more, in the present embodiment not
It is specifically limited.In another embodiment, a dislocation alignment mark can be only set, be arranged certain apart from matrix side
At dislocation distance N, when carrying out dislocation bonding, it is only necessary to be aligned the side of another matrix i.e. with the dislocation alignment mark
It can.In a further embodiment, it can also be not provided with dislocation alignment mark, calculating is utilized when substrates multilayer carries out dislocation bonding
Machine controls, and makes to generate certain dislocation distance between substrates multilayer.
In this example embodiment, referring to shown in Fig. 8, the first dislocation alignment mark 9 can be cross-shaped structure, and second
Dislocation alignment mark 10 is also possible to cross-shaped structure；The shape of two dislocation alignment marks is also possible to triangle, is carrying out
Corresponding angle mutual dislocation is aligned when alignment；Certainly, misplace alignment mark shape can also be rectangle, pentagon or
Person's hexagon etc., is not specifically limited in the present embodiment.In this example embodiment, first dislocation alignment mark 9 with
Spacing M between second dislocation alignment mark 10 is identical as the dislocation distance N of adjacent two layers matrix 7, only needs in positioning in this way
By the dislocation of two neighboring matrix 7 to label dislocation alignment is chased after, for example, the first dislocation alignment mark 9 and lining of matrix 7
Second dislocation alignment mark 10 of base body 6 is aligned.Setting dislocation can alignment mark to carry out the bonding of substrates multilayer 7
Shi Gengjia is accurate.
Dislocation distance N can be more than or equal to 10 μm and be less than or equal to 60 μm；Corresponding first dislocation alignment mark 9 and second
Spacing M between dislocation alignment mark 10 can also be more than or equal to 10 μm and be less than or equal to 60 μm.
Referring to shown in Fig. 4 and Fig. 5, multiple connection conductors 3 are provided on matrix 7, connection conductor 3 is formed in first material layer
In 4, and not prominent and first material layer 4.Multiple connection conductors 3 on matrix can be divided into two regions, left area and the right side
Side region.Left area is set there are four conductor 3 is connected, and four connection conductors 3 are uniformly distributed, and right area also is provided with four connections
Conductor 3, four connection conductors 3 are uniformly distributed.Interval in each region between two neighboring connection conductor 3 is identical, Liang Gequ
There are a biggish intervals between domain.In another example embodiment, 3 quantity of connection conductor in each region can be three
It is a, five or more.It is not particularly limited in this example embodiment.
Matrix 7 and substrate matrix 6Chip bonding (piece welding) or Hybrid bonding (hybrid bonded), and make base
First dislocation alignment mark 9 of body 7 is aligned with the second dislocation alignment mark of substrate matrix 6, so that the connection that matrix 7 is equipped with
The connection conductor 3 that conducting wire 11 can be equipped with substrate matrix 6 is connect.
Referring to Fig.1 shown in 3, silicon perforation displacement structure can also include slide glass 12, and substrate base is formed first on slide glass 12
Body 6 forms matrix 7 on substrate matrix 6；The material of slide glass 12 can be semiconductor or insulator；Such as glass, silicon plate
Deng.Described above have been carried out of method that matrix 7 is formed on substrate matrix 6 is discussed in detail, and therefore, details are not described herein again.
Base in another example embodiment of the utility model, referring to Fig.1 shown in 4, in the silicon perforation interconnection structure
Body 7 can also be chip 701；Chip 701 is formed on substrate matrix 6；Successively stacked offset is set chip 701 with substrate matrix 6
It sets to form silicon perforation interconnection structure.Chip 701 may include substrate 5, first material layer 4, connection conductor 3 and silicon perforation 2；Substrate
5, first material layer 4, connection conductor 3 and silicon perforation 2 is described above that detaileds description has been carried out, therefore go out no longer go to live in the household of one's in-laws on getting married at this time
It states.
Certainly, in the present embodiment, silicon perforation interconnection structure also may include slide glass 12, form substrate base on slide glass 12
Body 6 forms chip 701 on substrate matrix 6；The material of slide glass 12 can be semiconductor or insulator；Such as glass, silicon plate
Deng.
In this example embodiment, it is first to complete (TSV) plasma etching of silicon perforation 2 and fill out copper wiring, reuses
Substrates multilayer 7 is bonded to together by Chip bonding (piece welding) or Hybrid bonding (hybrid bonded).In another reality
It applies in mode, silicon perforation interconnection structure preparation process is also possible to first be bonded multi-disc matrix 7, then carry out silicon perforation 2 (TSV) etc.
Ion(ic) etching and fill out copper wiring.Therefore the preparation method of another silicon perforation interconnection structure can be proposed.Illustrate another kind below
The preparation method of silicon perforation interconnection structure.Referring to Fig.1 shown in 2, which be may comprise steps of:
Step S210, provides substrates multilayer, and multilayer described matrix is successively misplaced bonding.
Step S220, forms multiple silicon perforations 2 in multilayer described matrix, and the silicon perforation 2 runs through one layer of matrix, two layers
Matrix or substrates multilayer.
Step S230, forms connecting wire 11 in the silicon perforation 2, and the connecting wire 11 is connected to multilayer described matrix
On corresponding circuits.
Each step of the preparation method of the silicon perforation interconnection structure is described in detail below.
In step S210, substrates multilayer is provided, multilayer described matrix is successively misplaced bonding.
In this example embodiment, which further includes substrate matrix 6；Referring to Fig. 3, substrate matrix 6
It may include substrate 5 and first material layer 4, multiple connection conductors 3 be provided in first material layer 4.
In this example embodiment, substrates multilayer 7 can be multilayer upper layer wafer, in another embodiment, multilayer
Matrix can also be that multilayer chiop 701 or multilayer chiop 701 are mixed with upper layer wafer.Connection conductor 3 is equipped on each layer matrix 7
Referring to shown in Fig. 3, the multiple connection conductors 3 being arranged on matrix 7 can be divided into two region left areas and right area, every
Interval in a region between two neighboring connection conductor 3 is identical, and there are a biggish intervals between two regions.
In this example embodiment, substrates multilayer 7 is formed into offset laminar structure by above-mentioned dislocation alignment mark, and
It is bonded, and is bonded connection with above-mentioned substrate matrix 6.So that the dislocation of connection conductor 3 on substrates multilayer 7 is neat to its.Dislocation
Mode can be successively deviates to the right identical dislocation distance N from bottom to top.
Certainly, in another embodiment, dislocation mode may be set to be left and right offset it is alternate, for example, second layer phase
First layer is deviated to the right, third layer deviates to the left relative to the second layer, i.e., odd-level is mutually aligned, and even level is also mutually aligned.
Design is occurring being to occupy less area compared with substrates multilayer 7 in this way, vertically sets up, is not easy to collapse, stable structure.
Step S220, forms multiple silicon perforations 2 in multilayer described matrix, and the silicon perforation 2 runs through one layer of matrix, two layers
Matrix or substrates multilayer.
In this example embodiment, referring to shown in Fig. 2, silicon perforation 2 is opened up on the substrates multilayer 7 after above-mentioned bonding,
Silicon perforation 2 is opened up from above-mentioned 3 central location of connection conductor, runs through substrates multilayer 7.It is silicon perforation 2 through one layer in partial region
Matrix 7, partial region silicon perforation 2 run through substrates multilayer 7 through two layers of matrix 7, also partial region silicon perforation 2.Such as in Fig. 2
One layer of matrix 7 is run through close to silicon perforation 2 of the rightmost side in middle top layer.There is a connection conductor 4 in every layer of matrix leftmost side not
It is connect with the connecting wire 11 being set in silicon perforation 2, such structure can play preferable heat spreading function to a certain extent.
Step S230, forms connecting wire 11 in the silicon perforation 2, and the connecting wire 11 is connected to multilayer described matrix
On corresponding circuits.
In this example embodiment, connecting wire 11 is set in the silicon perforation 2 of above-mentioned formation, so that multilayer circuit
Circuit communication.
Referring to Fig.1 shown in 3, silicon perforation displacement structure can also include slide glass 12, and substrate base is formed first on slide glass 12
Body 6 forms matrix 7 on substrate matrix 6；The material of slide glass 12 can be semiconductor or insulator；Such as glass, silicon plate
Deng.Described above have been carried out of method that matrix 7 is formed on substrate matrix 6 is discussed in detail, and therefore, details are not described herein again.
Base in another example embodiment of the utility model, referring to Fig.1 shown in 4, in the silicon perforation interconnection structure
Body 7 can also be chip 701；Chip 701 is formed on substrate matrix 6；Successively stacked offset is set chip 701 with substrate matrix 6
It sets to form silicon perforation interconnection structure.Chip 701 may include substrate 5, first material layer 4, connection conductor 3 and silicon perforation 2；Substrate
5, first material layer 4, connection conductor 3 and silicon perforation 2 is described above that detaileds description has been carried out, therefore go out no longer go to live in the household of one's in-laws on getting married at this time
It states.
Certainly, in the present embodiment, silicon perforation interconnection structure also may include slide glass 12, form substrate base on slide glass 12
Body 6 forms chip 701 on substrate matrix 6；The material of slide glass 12 can be semiconductor or insulator；Such as glass, silicon plate
Deng.
Above-mentioned described feature, structure or characteristic can be incorporated in one or more embodiment party in any suitable manner
In formula, if possible, it is characterized in discussed in each embodiment interchangeable.In the above description, it provides many specific thin
Section fully understands the embodiments of the present invention to provide.It will be appreciated, however, by one skilled in the art that can be real
The technical solution of the utility model is trampled without one or more in the specific detail, or others side can be used
Method, component, material etc..In other cases, known features, material or operation are not shown in detail or describe to avoid fuzzy sheet
The various aspects of utility model.
Although the term of relativity, such as "upper" "lower" is used to describe a component of icon for another in this specification
The relativeness of one component, but these terms are in this manual merely for convenient, for example, with reference to the accompanying drawings described in show
The direction of example.It is appreciated that, if making it turn upside down the device overturning of icon, the component described in "upper" will
As the component in "lower".Term of other relativities, such as "high" " low " "top" "bottom" etc. also make have similar meaning.When certain
Structure is at other structures "upper", it is possible to refer to that certain structural integrity is formed in other structures, or refer to that certain structure " direct " is set
It sets in other structures, or refers to that certain structure is arranged in other structures by the way that another structure is " indirect ".
In this specification, term "one", " one ", "the", " described " and "at least one" indicating there are one or
Multiple element/component parts/etc.；Term "comprising", " comprising " and " having " are to indicate the open meaning being included
And refer to the element in addition to listing/component part/also may be present other than waiting other element/component part/etc.；Term " the
One ", " second " and " third " etc. only use as label, are not the quantity limitations to its object.
It should be appreciated that the utility model be not limited in its application to this specification proposition component detailed construction and
Arrangement.The utility model can have other embodiments, and can realize and execute in many ways.Aforementioned change
Shape form and modification are fallen in the scope of the utility model.It should be appreciated that this specification utility model and restriction
The utility model extend to text and/or drawings mention or two or more apparent independent features it is all alternative
Combination.All these different combinations constitute multiple alternative aspects of the utility model.Embodiment described in this specification
It illustrates the best mode for becoming known for realizing the utility model, and those skilled in the art will be enable practical new using this
Type.
Claims (9)
1. a kind of silicon perforation interconnection structure characterized by comprising
Substrates multilayer is provided with multiple silicon perforations in each layer described matrix, and successively stacked offset is arranged each layer described matrix
It is connected to the silicon perforation part；
Connecting wire is set in the silicon perforation, with the corresponding circuits being connected in multilayer described matrix.
2. silicon perforation interconnection structure according to claim 1, which is characterized in that described matrix is wafer, one in chip
Kind.
3. silicon perforation interconnection structure according to claim 1, which is characterized in that the silicon perforation interconnection structure further include:
Misplace alignment mark, is set in each layer described matrix.
4. silicon perforation interconnection structure according to claim 3, which is characterized in that the dislocation alignment mark is set as two
It is a.
5. silicon perforation interconnection structure according to claim 4, which is characterized in that between two dislocation alignment marks
Spacing is identical as the dislocation distance of adjacent two layers described matrix.
6. silicon perforation interconnection structure according to claim 5, which is characterized in that the dislocation distance be more than or equal to 10 μm and
Less than or equal to 60 μm.
7. silicon perforation interconnection structure according to claim 1, which is characterized in that the silicon perforation interconnection structure further include:
Substrate matrix, is provided with multiple connection conductors, the substrate matrix and multilayer described matrix shift to install make it is described
Connect conductor connection corresponding with the connecting wire.
8. silicon perforation interconnection structure according to claim 7, which is characterized in that the substrate matrix is wafer or chip.
9. silicon perforation interconnection structure according to claim 8, which is characterized in that the silicon perforation interconnection structure further include:
Slide glass, set on the one side of the separate described matrix of the substrate matrix.
Priority Applications (3)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201821762014.7U CN209071319U (en) | 2018-10-29 | 2018-10-29 | Silicon perforation interconnection structure |
| PCT/CN2019/113643 WO2020088396A1 (en) | 2018-10-29 | 2019-10-28 | Through-silicon via interconnection structure and methods for fabricating same |
| US17/234,554 US11876078B2 (en) | 2018-10-29 | 2021-04-19 | Through-silicon via interconnection structure and methods for fabricating same |
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| Application Number | Priority Date | Filing Date | Title |
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| CN201821762014.7U CN209071319U (en) | 2018-10-29 | 2018-10-29 | Silicon perforation interconnection structure |
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| CN209071319U true CN209071319U (en) | 2019-07-05 |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2020088396A1 (en) * | 2018-10-29 | 2020-05-07 | Changxin Memory Technologies, Inc. | Through-silicon via interconnection structure and methods for fabricating same |
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2018
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2020088396A1 (en) * | 2018-10-29 | 2020-05-07 | Changxin Memory Technologies, Inc. | Through-silicon via interconnection structure and methods for fabricating same |
| US11876078B2 (en) | 2018-10-29 | 2024-01-16 | Changxin Memory Technologies, Inc. | Through-silicon via interconnection structure and methods for fabricating same |
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