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CN206532771U - 散热型半导体器件 - Google Patents

散热型半导体器件 Download PDF

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CN206532771U
CN206532771U CN201720164410.9U CN201720164410U CN206532771U CN 206532771 U CN206532771 U CN 206532771U CN 201720164410 U CN201720164410 U CN 201720164410U CN 206532771 U CN206532771 U CN 206532771U
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chip
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张春尧
彭兴义
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Jiangsu Salt Core Microelectronics Co Ltd
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    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321Disposition
    • H01L2224/32151Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32245Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805Shape
    • H01L2224/4809Loop shape
    • H01L2224/48091Arched
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481Disposition
    • H01L2224/48151Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
    • H01L2224/48248Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item the bond pad being disposed in a recess of the surface of the item
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
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    • H01L2224/73Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
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    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/8338Bonding interfaces outside the semiconductor or solid-state body
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    • H01ELECTRIC ELEMENTS
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    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181Encapsulation

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Abstract

本实用新型公开一种散热型半导体器件,其环氧树脂包覆体包覆于芯片、金属焊盘、若干个左侧引脚、若干个右侧引脚上,所述金属焊盘、左侧引脚和右侧引脚各自的下表面裸露出环氧树脂包覆体的底部;所述芯片上表面的左侧区和右侧区分别开有若干个左圆凹槽、若干个右圆凹槽,所述左圆凹槽和右圆凹槽各自底部均具有管脚区,所述左侧引脚和右侧引脚各自的内侧端上表面分别开有第一圆凹槽和第二圆凹槽;金属焊盘上表面沿边缘开有一闭合的环形储膏槽,此环形储膏槽的截面形状为倒梯形,此环形储膏槽位于芯片正下方并靠近芯片的边缘区域。本实用新型有效避免了导热绝缘胶外溢而引起的短路故障,提高了产品成品率,使得加工生产更为简单方便,提高了集成芯片的稳定性和可靠性。

Description

散热型半导体器件
技术领域
本实用新型涉及一种芯片封装结构,涉及半导体技术领域。
背景技术
近几十年来,芯片封装技术一直随着集成电路技术的发展而发展。封装结构是指半导体集成电路芯片用的外壳,其不仅起着安装、固定、密封、保护芯片及增强电热性能等方面的作用,而且还通过芯片上的接点用导线连接到封装外壳的引脚上,这些引脚又通过印刷电路板上的导线与其它器件相连接。因此,封装结构一般包括用于安装、固定及引线的引线框架,同时还包括用于保护芯片、密封并与引线框架相匹配的封装体。
传统的SOP类的封装结构采用的是全包封设计,没有外露的散热结构,主要通过塑封料散热,而塑封料的导热性能较差导致此种封装的散热性能较差。在功率越来越大、封装尺寸越来越小的需求下,传统的SOP 结构的散热缺点越来越明显。另外,一些芯片产品需要在一个封装结构中封装相互隔离的两粒芯片。
发明内容
本实用新型目的是提供一种散热型半导体器件,该散热型半导体器件有利于将引脚和金属焊盘更加牢固的固定,有效避免了导热绝缘胶外溢而引起的短路故障,提高了产品成品率,使得加工生产更为简单方便,提高了集成芯片的稳定性和可靠性。
为达到上述目的,本实用新型采用的技术方案是:一种散热型半导体器件,包括芯片、金属焊盘、若干个左侧引脚、若干个右侧引脚和环氧树脂包覆体,所述芯片通过绝缘胶层固定于金属焊盘上表面的中央区域,若干个所述左侧引脚并排间隔地设置于芯片的左侧,若干个所述右侧引脚并排间隔地设置于芯片的右侧,所述金属焊盘下部边缘处开有第一缺口槽,所述左侧引脚与金属焊盘相向的内侧端下部开有第二缺口槽,所述右侧引脚与金属焊盘相向的内侧端下部开有第三缺口槽,所述环氧树脂包覆体包覆于芯片、金属焊盘、若干个左侧引脚、若干个右侧引脚上,所述金属焊盘、左侧引脚和右侧引脚各自的下表面裸露出环氧树脂包覆体的底部;
所述芯片上表面的左侧区和右侧区分别开有若干个左圆凹槽、若干个右圆凹槽,所述左圆凹槽和右圆凹槽各自底部均具有管脚区,所述左侧引脚和右侧引脚各自的内侧端上表面分别开有第一圆凹槽和第二圆凹槽,若干根第一金线一端位于左圆凹槽内并通过焊膏与管脚区电连接,此第一金线另一端位于左侧引脚的第一圆凹槽内并通过焊膏电连接,若干根第二金线一端位于右圆凹槽内并通过焊膏与管脚区电连接,此第二金线另一端位于右侧引脚的第二圆凹槽内并通过焊膏电连接;
所述金属焊盘上表面沿边缘开有一闭合的环形储膏槽,此环形储膏槽的截面形状为倒梯形,此环形储膏槽位于芯片正下方并靠近芯片的边缘区域。
上述技术方案中进一步改进的方案如下:
1. 上述方案中,所述左侧引脚、右侧引脚的下表面镀覆有金属镀层。
2. 上述方案中,所述金属镀层为锡层或者镍钯金层。
3. 上述方案中,所述左圆凹槽和右圆凹槽均为半圆形凹槽。
4. 上述方案中,所述金属镀层与左侧引脚或者右侧引脚的厚度比为1:6~12。
5. 上述方案中,所述左侧引脚和右侧引脚的数目均为3~10根。
由于上述技术方案运用,本实用新型与现有技术相比具有下列优点:
1. 本实用新型散热型半导体器件,其金属焊盘下部边缘处开有第一缺口槽,所述左侧引脚与金属焊盘相向的内侧端下部开有第二缺口槽,所述右侧引脚与金属焊盘相向的内侧端下部开有第三缺口槽,有利于将引脚和金属焊盘更加牢固的固定,提高了与PCB之间焊接的可靠性;其次,其芯片通过绝缘胶层固定于金属焊盘上表面的中央区域,金属焊盘、左侧引脚和右侧引脚各自的下表面裸露出环氧树脂包覆体的底部,裸露的金属焊盘,以便芯片在工作时快速传导热量,散热效果好。
2. 本实用新型散热型半导体器件,其芯片上表面的左侧区和右侧区分别开有若干个左圆凹槽、若干个右圆凹槽,所述左圆凹槽和右圆凹槽各自底部均具有管脚区,所述左侧引脚和右侧引脚各自的内侧端上表面分别开有第一圆凹槽和第二圆凹槽,若干根第一金线一端位于左圆凹槽内并通过焊膏与管脚区电连接,此第一金线另一端位于左侧引脚的第一圆凹槽内并通过焊膏电连接,若干根第二金线一端位于右圆凹槽内并通过焊膏与管脚区电连接,此第二金线另一端位于右侧引脚的第二圆凹槽内并通过焊膏电连接,有效避免了、空焊和虚焊的问题,既提高器件的承载电流,也提高了集成芯片的稳定性和可靠性。
3. 本实用新型散热型半导体器件,其金属焊盘上表面沿边缘开有一闭合的环形储膏槽,此环形储膏槽的截面形状为倒梯形,此环形储膏槽位于芯片正下方并靠近芯片的边缘区域,有效避免了导热绝缘胶外溢而引起的短路故障,提高了产品成品率,使得加工生产更为简单方便,提高了集成芯片的稳定性和可靠性;其次,其左侧引脚、右侧引脚的下表面镀覆有金属镀层,既降低了器件与PCB的导电接触电阻,也有利于与PCB之间的焊接强度的提高。
附图说明
附图1为本实用新型散热型半导体器件结构示意图;
附图2为附图1的局部结构示意图。
以上附图中:1、芯片;2、金属焊盘;3、左侧引脚;4、右侧引脚;5、环氧树脂包覆体;6、绝缘胶层;7、第一缺口槽;8、第二缺口槽;9、第三缺口槽;10、左圆凹槽;11、右圆凹槽;12、管脚区;13、第一圆凹槽;14、第二圆凹槽;15、第一金线;16、第二金线;17、金属镀层;18、环形储膏槽。
具体实施方式
下面结合附图及实施例对本实用新型作进一步描述:
实施例1:一种散热型半导体器件,包括芯片1、金属焊盘2、若干个左侧引脚3、若干个右侧引脚4和环氧树脂包覆体5,所述芯片1通过绝缘胶层6固定于金属焊盘2上表面的中央区域,若干个所述左侧引脚3并排间隔地设置于芯片1的左侧,若干个所述右侧引脚4并排间隔地设置于芯片1的右侧,所述金属焊盘2下部边缘处开有第一缺口槽7,所述左侧引脚3与金属焊盘2相向的内侧端下部开有第二缺口槽8,所述右侧引脚4与金属焊盘2相向的内侧端下部开有第三缺口槽9,所述环氧树脂包覆体5包覆于芯片1、金属焊盘2、若干个左侧引脚3、若干个右侧引脚4上,所述金属焊盘2、左侧引脚3和右侧引脚4各自的下表面裸露出环氧树脂包覆体5的底部;
所述芯片1上表面的左侧区和右侧区分别开有若干个左圆凹槽10、若干个右圆凹槽11,所述左圆凹槽10和右圆凹槽11各自底部均具有管脚区12,所述左侧引脚3和右侧引脚4各自的内侧端上表面分别开有第一圆凹槽13和第二圆凹槽14,若干根第一金线15一端位于左圆凹槽10内并通过焊膏与管脚区12电连接,此第一金线15另一端位于左侧引脚3的第一圆凹槽13内并通过焊膏电连接,若干根第二金线16一端位于右圆凹槽11内并通过焊膏与管脚区电连接,此第二金线另一端位于右侧引脚的第二圆凹槽内并通过焊膏电连接;
所述金属焊盘2上表面沿边缘开有一闭合的环形储膏槽18,此环形储膏槽18的截面形状为倒梯形,此环形储膏槽18位于芯片1正下方并靠近芯片1的边缘区域。
上述左侧引脚3、右侧引脚4的下表面镀覆有金属镀层17;上述金属镀层17为锡层或者镍钯金层。
上述金属镀层17与左侧引脚3或者右侧引脚4的厚度比为1:8;上述左侧引脚3和右侧引脚4的数目均为8根。
实施例2:一种散热型半导体器件,包括芯片1、金属焊盘2、若干个左侧引脚3、若干个右侧引脚4和环氧树脂包覆体5,所述芯片1通过绝缘胶层6固定于金属焊盘2上表面的中央区域,若干个所述左侧引脚3并排间隔地设置于芯片1的左侧,若干个所述右侧引脚4并排间隔地设置于芯片1的右侧,所述金属焊盘2下部边缘处开有第一缺口槽7,所述左侧引脚3与金属焊盘2相向的内侧端下部开有第二缺口槽8,所述右侧引脚4与金属焊盘2相向的内侧端下部开有第三缺口槽9,所述环氧树脂包覆体5包覆于芯片1、金属焊盘2、若干个左侧引脚3、若干个右侧引脚4上,所述金属焊盘2、左侧引脚3和右侧引脚4各自的下表面裸露出环氧树脂包覆体5的底部;
所述芯片1上表面的左侧区和右侧区分别开有若干个左圆凹槽10、若干个右圆凹槽11,所述左圆凹槽10和右圆凹槽11各自底部均具有管脚区12,所述左侧引脚3和右侧引脚4各自的内侧端上表面分别开有第一圆凹槽13和第二圆凹槽14,若干根第一金线15一端位于左圆凹槽10内并通过焊膏与管脚区12电连接,此第一金线15另一端位于左侧引脚3的第一圆凹槽13内并通过焊膏电连接,若干根第二金线16一端位于右圆凹槽11内并通过焊膏与管脚区电连接,此第二金线另一端位于右侧引脚的第二圆凹槽内并通过焊膏电连接;
所述金属焊盘2上表面沿边缘开有一闭合的环形储膏槽18,此环形储膏槽18的截面形状为倒梯形,此环形储膏槽18位于芯片1正下方并靠近芯片1的边缘区域。
上述左侧引脚3、右侧引脚4的下表面镀覆有金属镀层17;上述左圆凹槽10和右圆凹槽11均为半圆形凹槽。
上述金属镀层17与左侧引脚3或者右侧引脚4的厚度比为1:10;上述左侧引脚3和右侧引脚4的数目均为4根。
采用上述散热型半导体器件时,其有利于将引脚和金属焊盘更加牢固的固定,提高了与PCB之间焊接的可靠性;其次,其裸露的金属焊盘,以便芯片在工作时快速传导热量,散热效果好;再次有效避免了、空焊和虚焊的问题,既提高器件的承载电流,也提高了集成芯片的稳定性和可靠性。
上述实施例只为说明本实用新型的技术构思及特点,其目的在于让熟悉此项技术的人士能够了解本实用新型的内容并据以实施,并不能以此限制本实用新型的保护范围。凡根据本实用新型精神实质所作的等效变化或修饰,都应涵盖在本实用新型的保护范围之内。

Claims (6)

1.一种散热型半导体器件,其特征在于:包括芯片(1)、金属焊盘(2)、若干个左侧引脚(3)、若干个右侧引脚(4)和环氧树脂包覆体(5),所述芯片(1)通过绝缘胶层(6)固定于金属焊盘(2)上表面的中央区域,若干个所述左侧引脚(3)并排间隔地设置于芯片(1)的左侧,若干个所述右侧引脚(4)并排间隔地设置于芯片(1)的右侧,所述金属焊盘(2)下部边缘处开有第一缺口槽(7),所述左侧引脚(3)与金属焊盘(2)相向的内侧端下部开有第二缺口槽(8),所述右侧引脚(4)与金属焊盘(2)相向的内侧端下部开有第三缺口槽(9),所述环氧树脂包覆体(5)包覆于芯片(1)、金属焊盘(2)、若干个左侧引脚(3)、若干个右侧引脚(4)上,所述金属焊盘(2)、左侧引脚(3)和右侧引脚(4)各自的下表面裸露出环氧树脂包覆体(5)的底部;
所述芯片(1)上表面的左侧区和右侧区分别开有若干个左圆凹槽(10)、若干个右圆凹槽(11),所述左圆凹槽(10)和右圆凹槽(11)各自底部均具有管脚区(12),所述左侧引脚(3)和右侧引脚(4)各自的内侧端上表面分别开有第一圆凹槽(13)和第二圆凹槽(14),若干根第一金线(15)一端位于左圆凹槽(10)内并通过焊膏与管脚区(12)电连接,此第一金线(15)另一端位于左侧引脚(3)的第一圆凹槽(13)内并通过焊膏电连接,若干根第二金线(16)一端位于右圆凹槽(11)内并通过焊膏与管脚区(12)电连接,此第二金线(16)另一端位于右侧引脚(4)的第二圆凹槽(14)内并通过焊膏电连接;
所述金属焊盘(2)上表面沿边缘开有一闭合的环形储膏槽(18),此环形储膏槽(18)的截面形状为倒梯形,此环形储膏槽(18)位于芯片(1)正下方并靠近芯片(1)的边缘区域。
2.根据权利要求1所述的散热型半导体器件,其特征在于:所述左侧引脚(3)、右侧引脚(4)的下表面镀覆有金属镀层(17)。
3.根据权利要求2所述的散热型半导体器件,其特征在于:所述金属镀层(17)为锡层或者镍钯金层。
4.根据权利要求1所述的散热型半导体器件,其特征在于:所述左圆凹槽(10)和右圆凹槽(11)均为半圆形凹槽。
5.根据权利要求2所述的散热型半导体器件,其特征在于:所述金属镀层(17)与左侧引脚(3)或者右侧引脚(4)的厚度比为1:6~12。
6.根据权利要求2所述的散热型半导体器件,其特征在于:所述左侧引脚(3)和右侧引脚(4)的数目均为3~10根。
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Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2022179061A1 (zh) * 2021-02-25 2022-09-01 长鑫存储技术有限公司 半导体结构及半导体结构的制备方法
US11456270B2 (en) 2021-02-25 2022-09-27 Changxin Memory Technologies, Inc. Semiconductor structure and manufacturing method thereof
CN116053239A (zh) * 2023-04-03 2023-05-02 中科华艺(天津)科技有限公司 一种多芯片组件的封装结构

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2022179061A1 (zh) * 2021-02-25 2022-09-01 长鑫存储技术有限公司 半导体结构及半导体结构的制备方法
US11456270B2 (en) 2021-02-25 2022-09-27 Changxin Memory Technologies, Inc. Semiconductor structure and manufacturing method thereof
CN116053239A (zh) * 2023-04-03 2023-05-02 中科华艺(天津)科技有限公司 一种多芯片组件的封装结构

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