CN206370051U - Interface compatibility circuit - Google Patents
Interface compatibility circuit Download PDFInfo
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- CN206370051U CN206370051U CN201621415374.0U CN201621415374U CN206370051U CN 206370051 U CN206370051 U CN 206370051U CN 201621415374 U CN201621415374 U CN 201621415374U CN 206370051 U CN206370051 U CN 206370051U
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- sata
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/38—Information transfer, e.g. on bus
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/38—Information transfer, e.g. on bus
- G06F13/40—Bus structure
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- General Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Techniques For Improving Reliability Of Storages (AREA)
- Memory System Of A Hierarchy Structure (AREA)
Abstract
The utility model is related to a kind of interface compatibility circuit, including SATA connector circuit, the access device type code of mSATA connector circuits, governor circuit logic interfacing and the governor circuit logic interfacing that is stored with and the governor circuit of the mapping table of the mapping table of corresponding access device type, access device type and read-write mode；SATA connector circuit and mSATA connector circuits are connected with governor circuit logic interfacing respectively, and governor circuit logic interfacing is connected with governor circuit；In the mapping table of access device type and read-write mode, the access device type of the mechanical hard disk of SATA interface is corresponding with the read-write mode of order reading, caching write-in；The access device type of the mechanical solid-state hybrid hard disk of SATA interface is read with order, the read-write mode of load balancing write-in is corresponding；The access device type of the solid state hard disc of SATA interface or the solid state hard disc of mSATA interfaces is corresponding with the read-write mode that random read take, load balancing write.
Description
Technical field
The utility model is related to Computer Interface Technology field, more particularly to a kind of interface compatibility circuit.
Background technology
SATA (Serial Advanced Technology Attachment, serial hard disk interface technology) is a kind of electricity
Brain bus, is mainly used as the data transfer between mainboard and a large amount of storage devices (such as hard disk and CD drive), is one to finish
The full novel hard disk interface class for being different from Parallel ATA (Advanced Technology Attachment, hard-disk interface technology)
Type, gains the name due to transmitting data using serial mode.SATA buses use embedded clock signal, possess stronger error correction
Ability, its maximum difference compared with the past is that transmission instruction (being not only data) can be checked, if it find that wrong
Automatic straightening is misunderstood, something which increases the reliability of data transfer, also with simple in construction, support hot plug
Advantage.MSATA interfaces (mini-SATA, miniversion SATA interface) are that one kind of the international interface standard tissue issues of SATA is new
The interface standard of type, the field such as box and printer on tablet PC, mobile phone, machine of the solid state hard disc with mSATA interfaces has
And be widely applied.
At least there are the following problems for prior art：One logic interfacing can not the access of compatible identifying processing SATA interface set
The access device of standby and mSATA interfaces, the access device of access device and mSATA interfaces for SATA interface, separately design,
So space-consuming is big, and occupying system resources, and cost is also high.
Utility model content
Based on this, it is necessary to for logic interfacing in the prior art can not compatible identifying processing SATA interface access
The access device of equipment and mSATA interfaces, the access device of SATA interface and the access device of mSATA interfaces are separately designed, and are accounted for
It is big with space, and occupying system resources, the problem of cost is also high there is provided it is a kind of can compatible identifying processing SATA interface access
The interface compatibility circuit of the access device of equipment and mSATA interfaces.
A kind of interface compatibility circuit, including SATA connector circuit, mSATA connector circuits, governor circuit logic interfacing
And the access device type code for the governor circuit logic interfacing that is stored with and corresponding access device type mapping table,
The governor circuit of the mapping table of access device type and read-write mode, wherein, access device type includes SATA interface
Mechanical hard disk, the mechanical solid-state hybrid hard disk of SATA interface, the solid state hard disc of SATA interface and mSATA interfaces solid-state it is hard
Disk；
SATA connector circuit and mSATA connector circuits are connected with governor circuit logic interfacing respectively, and governor circuit is patrolled
Interface is collected to be connected with governor circuit；
In the mapping table of access device type and read-write mode, the access device type of the mechanical hard disk of SATA interface
The read-write mode that write-in is read, cached with order is corresponding；The access device type of the mechanical solid-state hybrid hard disk of SATA interface with
Order is read, the read-write mode correspondence of load balancing write-in；The solid state hard disc of SATA interface or the solid state hard disc of mSATA interfaces
Access device type is corresponding with the read-write mode that random read take, load balancing write.
Above-mentioned interface compatibility circuit, including SATA connector circuit, mSATA connector circuits, governor circuit logic interfacing
And the access device type code for the governor circuit logic interfacing that is stored with and corresponding access device type mapping table,
The governor circuit of the mapping table of access device type and read-write mode, wherein, access device type includes SATA interface
Mechanical hard disk, the mechanical solid-state hybrid hard disk of SATA interface, the solid state hard disc of SATA interface and mSATA interfaces solid-state it is hard
Disk；SATA connector circuit and mSATA connector circuits are connected with governor circuit logic interfacing respectively, governor circuit logic interfacing
It is connected with governor circuit；In the mapping table of access device type and read-write mode, the access of the mechanical hard disk of SATA interface
Device type is read with order, the read-write mode of caching write-in is corresponding；The access of the mechanical solid-state hybrid hard disk of SATA interface is set
Standby type is read with order, the read-write mode of load balancing write-in is corresponding；The solid state hard disc of SATA interface or consolidating for mSATA interfaces
The access device type of state hard disk is corresponding with the read-write mode that random read take, load balancing write, and the interface compatibility circuit can be simultaneous
Hold the access device of identification SATA interface and the access device of mSATA interfaces, and according to access device type and read-write mode
Mapping table, the different read-write mode of different access device type correspondences, is used to recognize SATA without separated independent design
The access device of interface and for the governor circuit logic interfacing for the access device for recognizing mSATA interfaces, such space-consuming
It is small, and system resource is saved, reduce cost.
Brief description of the drawings
Fig. 1 is the structural representation of interface compatibility circuit in one embodiment；
Fig. 2 is the circuit theory diagrams of the SATA connector circuit in interface compatibility circuit in one embodiment；
Fig. 3 is the circuit theory diagrams of the mSATA connector circuits in interface compatibility circuit in one embodiment.
Embodiment
Hard-disk interface is the connection member between hard disk and host computer system, and effect is passed between hard disk cache and host memory
Transmission of data.From overall angle, hard-disk interface is divided into IDE, and (Integrated Drive Electronics, i.e. electronics is integrated
Driver), SATA (Serial Advanced Technology Attachment, serial hard disk interface technology), SCSI
(Small Computer System Interface, small computer system interface), optical-fibre channel and SAS (Serial
Attached SCSI, Serial Attached SCSI (SAS)) five kinds.Ide interface hard disk is used in household products, and also certain applications are in service
Device；The hard disk of scsi interface is then mainly used in server market, and optical-fibre channel is in high-end server, expensive；
SATA is a kind of newborn hard-disk interface type, is in the market stage of popularization, there is extensive prospect in household application market.
MSATA interfaces (mini-SATA, miniversion SATA interface) are a kind of new the connecing of the international interface standard tissue issues of SATA
Mouth standard, the field such as box and printer on tablet PC, mobile phone, machine of the solid state hard disc with mSATA interfaces has extensively
Application.
Mechanical hard disk is traditional common hard disc, mainly including disc, magnetic head, disc rotating shaft and controlled motor, magnetic head control
Device, data converter, interface, caching etc..Magnetic head can be moved along the radial direction of disc, add the height of thousands of turns per minute of disc
Speed rotation, magnetic head just can be positioned at the read-write operation of the enterprising row data of specified location of disc.Information passes through from magnetic surface
Close magnetic head, is changed polarity mode by electromagnetic current and is write by electromagnetic current on disk, and information can be read by opposite mode
Take, as precision equipment, dust is its formidable enemy, it is necessary to be fully sealed.All discs are incorporated into a rotation in mechanical hard disk
Parallel on axle, between each disc piece, mechanical hard disk has a magnetic head on the storage face of each disc, magnetic head and disc it
Between distance it is also smaller than the diameter of hairline, all magnetic heads are connected on a magnetic head control device, are responsible for each by magnetic head control device
The motion of individual magnetic head.
Solid state hard disc referred to as consolidate disk, and the hard disk that solid state hard disc solid-state electronic storage chip array is made, including control
Unit and memory cell (FLASH chip and dram chip).SSD (Solid State Drives, solid state hard disc) solid state hard disc
Any mechanical part is not present in inside, accordingly even when also not interfered with the case where high-speed mobile is even with tip tilt
Normally use, and the possibility of loss of data can be minimized when colliding and shaking.The storage of solid state hard disc
Medium is divided into two kinds, and one kind is that another is as storage using DRAM as storage medium using flash memory (FLASH chip)
Medium.Solid state hard disc based on flash memory is the primary categories of solid state hard disc, its internal structure very simple, main body in solid state hard disc
It is exactly one piece of PCB (Printed Circuit Board, printed wiring board) plate in fact, and accessory most basic on this block pcb board
It is exactly control chip, cache chip (part low side hard disk is without cache chip) and the flash chip for data storage.Master control core
Piece is the brain of solid state hard disc, and it is load of the rational allocation data on each flash chip that it, which acts on one, second be assume responsibility for
Whole data relay, connection flash chip and outside SATA interface.Ability difference is very big between different master controls, at data
Reason ability, algorithm, to having very big difference in the reading write-in control of flash chip, can directly cause solid-state hard disc product
Gap is up to decades of times in performance.
Hybrid hard disk is regarded as solid state hard disc and is used in mixed way with general mechanical hard disk by many users, in fact hybrid hard disk
It is not the address for being used in mixed way solid state hard disc and traditional mechanical hard disk.Hybrid hard disk is one piece and is based on traditional mechanical hard disk
Be born new hard disk out, except the indispensable disk of mechanical hard disk, motor, magnetic head etc., also built-in nand flash memory particle, should
Particle is stored the data that user often accesses, and can be reached such as the reading performance of SSD solid state hard disc effects.SSHD
(Solid State Hybrid Drive, solid-state hybrid hard disk) is that one kind that magnetic hard-disk and flash memory are integrated together is hard
Disk, is a solution in the middle of magnetic hard-disk and solid state hard disc.
In one embodiment, as shown in figure 1, a kind of interface compatibility circuit, including SATA connector circuit 100, mSATA
The access device type of connector circuit 200, governor circuit logic interfacing 300 and the governor circuit logic interfacing 300 that is stored with
The master control of code and the mapping table of the mapping table of corresponding access device type, access device type and read-write mode
Circuit 400, wherein, the mechanical hard disk of access device type including SATA interface, the mechanical solid-state hybrid hard disk of SATA interface,
The solid state hard disc of SATA interface and the solid state hard disc of mSATA interfaces；
SATA connector circuit 100 and mSATA connector circuits 200 are connected with governor circuit logic interfacing 300 respectively, main
Control circuit logic interface 300 is connected with governor circuit 400；
In the corresponding relation of access device type and read-write mode, the access device type of the mechanical hard disk of SATA interface with
Order is read, the read-write mode correspondence of caching write-in；The access device type of the mechanical solid-state hybrid hard disk of SATA interface with it is suitable
Sequence is read, the read-write mode correspondence of load balancing write-in；The solid state hard disc of SATA interface or the solid state hard disc of mSATA interfaces connect
It is corresponding with the read-write mode that random read take, load balancing write to enter device type.
Specifically, governor circuit is previously stored with the corresponding relation of access device type code and corresponding access device
Table, such as 1 represents mechanical hard disk of the access device type as SATA interface, 2 to represent access device type be SATA interface
Mechanical solid-state hybrid hard disk, 3 represent solid state hard disc of the access device type as SATA interface, 4 represent access device type as
The solid state hard disc of mSATA interfaces, when it is 1 that governor circuit, which receives signal parameter, it is SATA interface to illustrate current input equipment
Mechanical hard disk.Consider in terms of the read-write efficiency and service life two of access device, set with reference to different types of access
The standby characteristic of itself, to make the read-write efficiency to access device higher, service life is longer, access device type and read-write mode
Mapping table in, the access device type of the mechanical hard disk of SATA interface is read with order, the read-write mode of caching write-in
Correspondence；The access device type of the mechanical solid-state hybrid hard disk of SATA interface is read with order, the read-write side of load balancing write-in
Formula correspondence；The access device type of the solid state hard disc of SATA interface or the solid state hard disc of mSATA interfaces and random read take, load are equal
The read-write mode correspondence of weighing apparatus write-in.
SATA connector circuit 100, including SATA connector, the first electric capacity, the second electric capacity, the 3rd electric capacity and the 4th electricity
Hold, one end of the first electric capacity connects the first differential received pin of SATA connector, the other end connection master control electricity of the first electric capacity
The first differential received pin on road；One end of second electric capacity connects the second differential received pin of SATA connector, the second electric capacity
The other end connect governor circuit the second differential received pin；One end of 3rd electric capacity connects the first difference of SATA connector
Pin is sent, the first difference of the other end connection governor circuit of the 3rd electric capacity sends pin；One end connection of 4th electric capacity
Second difference of SATA connector sends pin, and the second difference of the other end connection governor circuit of the 4th electric capacity sends pin.
Interface compatibility circuit also includes first circuit board, SATA connector, the first electric capacity, the second electric capacity, the 3rd electric capacity and the 4th electricity
Appearance is set in turn in first circuit board.Specifically, the first electric capacity, second electric capacity, the 3rd electric capacity and the 4th electric capacity are
10nF electric capacity.More specifically, Fig. 2 is the circuit theory diagrams of SATA connector, wherein, the first electric capacity is C315, the second electricity
Hold for C316, the 3rd electric capacity is C317, the 4th electric capacity is C318.
MSATA connector circuits 200, including mSATA connectors, the 5th electric capacity, the 6th electric capacity, the 7th electric capacity and the 8th
Electric capacity, one end of the 5th electric capacity connects the first differential received pin of the mSATA connectors, the other end connection of the 5th electric capacity
First differential received pin of governor circuit；One end of 6th electric capacity connects the second differential received pin of mSATA connectors, the
The other end of six electric capacity connects the second differential received pin of governor circuit；One end connection mSATA connectors of 7th electric capacity
First difference sends pin, and the first difference of the other end connection governor circuit of the 7th electric capacity sends pin；The one of 8th electric capacity
Second difference of end connection mSATA connectors sends pin, the second difference hair of the other end connection governor circuit of the 8th electric capacity
Send pin.Interface compatibility circuit also include second circuit board, mSATA connectors, the 5th electric capacity, the 6th electric capacity, the 7th electric capacity with
And the 8th electric capacity be set in turn in second circuit board.Specifically, the 5th electric capacity, the 6th electric capacity, the 7th electric capacity and the 8th electric capacity
It is 10nF electric capacity.More specifically, Fig. 3 is the circuit theory diagrams of mSATA connectors, wherein, the 5th electric capacity is C323, the
Six electric capacity are C325, and the 7th electric capacity is C326, and the 8th electric capacity is C327.
Governor circuit 400 includes GL830 main control chips, and GL830 is a high-compatibility, the USB of low cost
(Universal Serial Bus, USB) 2.0 pairs of SATA bridges connect controller.
Above-mentioned interface compatibility circuit, including SATA connector circuit, mSATA connector circuits, governor circuit logic interfacing
And the access device type code for the governor circuit logic interfacing that is stored with and corresponding access device type mapping table,
The governor circuit of the mapping table of access device type and read-write mode, wherein, access device type includes SATA interface
Mechanical hard disk, the mechanical solid-state hybrid hard disk of SATA interface, the solid state hard disc of SATA interface and mSATA interfaces solid-state it is hard
Disk；SATA connector circuit and mSATA connector circuits are connected with governor circuit logic interfacing respectively, governor circuit logic interfacing
It is connected with governor circuit；In the mapping table of access device type and read-write mode, the access of the mechanical hard disk of SATA interface
Device type is read with order, the read-write mode of caching write-in is corresponding；The access of the mechanical solid-state hybrid hard disk of SATA interface is set
Standby type is read with order, the read-write mode of load balancing write-in is corresponding；The solid state hard disc of SATA interface or consolidating for mSATA interfaces
The access device type of state hard disk is corresponding with the read-write mode that random read take, load balancing write, and the interface compatibility circuit can be simultaneous
Hold the access device of identification SATA interface and the access device of mSATA interfaces, and according to access device type and read-write mode
Mapping table, the different read-write mode of different access device type correspondences, is used to recognize SATA without separated independent design
The access device of interface and for the governor circuit logic interfacing for the access device for recognizing mSATA interfaces, such space-consuming
It is small, and system resource is saved, reduce cost.
In one embodiment, in interface compatibility circuit, governor circuit is also included when access device type is SATA interface
Solid state hard disc or mSATA interfaces solid state hard disc when, the solid state hard disc of SATA interface or the solid state hard disc of mSATA interfaces are adjacent
The time parameter setup module that the time interval of read-write data is 0 twice, is had based on solid state hard disc without mechanical structure, read-write number of times
The characteristic of limit, the reading-writing life-span of access device is improved with this.In addition, the governor circuit in interface compatibility circuit also includes obtaining master
The capacity and the access device information acquisition module of cache size of the access device of circuit logic interface are controlled, it is gentle according to amount of capacity
The size of value is deposited, read-write operation frequent degree is determined, capacity is big, and read-write operation is more frequent；Cache size is smaller, and read-write operation is got over
Frequently, to ensure higher read-write efficiency.
Each technical characteristic of embodiment described above can be combined arbitrarily, to make description succinct, not to above-mentioned reality
Apply all possible combination of each technical characteristic in example to be all described, as long as however, the combination of these technical characteristics is not deposited
In contradiction, the scope of this specification record is all considered to be.
Embodiment described above only expresses several embodiments of the present utility model, and it describes more specific and detailed,
But therefore it can not be interpreted as the limitation to utility model patent scope.It should be pointed out that for the common skill of this area
For art personnel, without departing from the concept of the premise utility, various modifications and improvements can be made, these are belonged to
Protection domain of the present utility model.Therefore, the protection domain of the utility model patent should be determined by the appended claims.
Claims (10)
1. a kind of interface compatibility circuit, it is characterised in that including SATA connector circuit, mSATA connector circuits, governor circuit
The access device type code of logic interfacing and the governor circuit logic interfacing that is stored with and corresponding access device type
Mapping table, the governor circuit of the mapping table of the access device type and read-write mode, wherein, the access is set
Standby type include the solid state hard disc of the mechanical hard disk, the mechanical solid-state hybrid hard disk of SATA interface, SATA interface of SATA interface with
And the solid state hard disc of mSATA interfaces；
The SATA connector circuit and the mSATA connector circuits are connected with the governor circuit logic interfacing respectively, institute
Governor circuit logic interfacing is stated to be connected with the governor circuit；
In the mapping table of the access device type and read-write mode, the access device type of the mechanical hard disk of SATA interface
The read-write mode that write-in is read, cached with order is corresponding；The access device type of the mechanical solid-state hybrid hard disk of SATA interface with
Order is read, the read-write mode correspondence of load balancing write-in；The solid state hard disc of SATA interface or the solid state hard disc of mSATA interfaces
Access device type is corresponding with the read-write mode that random read take, load balancing write.
2. interface compatibility circuit according to claim 1, it is characterised in that the SATA connector circuit connects including SATA
Device, the first electric capacity, the second electric capacity, the 3rd electric capacity and the 4th electric capacity are connect, one end of first electric capacity connects the SATA and connected
The first differential received pin of device is connect, the first differential received of the other end connection governor circuit of first electric capacity is drawn
Pin；One end of second electric capacity connects the second differential received pin of the SATA connector, second electric capacity it is another
Second differential received pin of the end connection governor circuit；One end of 3rd electric capacity connects the of the SATA connector
One difference sends pin, and the other end of the 3rd electric capacity connects the first difference transmission pin of the governor circuit；Described
The second difference that one end of four electric capacity connects the SATA connector sends pin, and the other end connection of the 4th electric capacity is described
Second difference of governor circuit sends pin.
3. interface compatibility circuit according to claim 2, it is characterised in that also including first circuit board, the SATA connects
Connect device, first electric capacity, second electric capacity, the 3rd electric capacity and the 4th electric capacity and be set in turn in described first
Circuit board.
4. interface compatibility circuit according to claim 2, it is characterised in that first electric capacity, second electric capacity, institute
State the 3rd electric capacity and the 4th electric capacity be 10nF electric capacity.
5. interface compatibility circuit according to claim 1, it is characterised in that the mSATA connector circuits include mSATA
Connector, the 5th electric capacity, the 6th electric capacity, the 7th electric capacity and the 8th electric capacity, one end of the 5th electric capacity connect the mSATA
First differential received pin of connector, the first differential received of the other end connection governor circuit of the 5th electric capacity is drawn
Pin；One end of 6th electric capacity connects the second differential received pin of the mSATA connectors, the 6th electric capacity it is another
Second differential received pin of the end connection governor circuit；One end of 7th electric capacity connects the mSATA connectors
First difference sends pin, and the other end of the 7th electric capacity connects the first difference transmission pin of the governor circuit；It is described
The second difference that one end of 8th electric capacity connects the mSATA connectors sends pin, the other end connection of the 8th electric capacity
Second difference of the governor circuit sends pin.
6. interface compatibility circuit according to claim 5, it is characterised in that also including second circuit board, the mSATA connects
Connect device, the 5th electric capacity, the 6th electric capacity, the 7th electric capacity and the 8th electric capacity and be set in turn in described second
Circuit board.
7. interface compatibility circuit according to claim 5, it is characterised in that the 5th electric capacity, the 6th electric capacity, institute
State the 7th electric capacity and the 8th electric capacity be 10nF electric capacity.
8. the interface compatibility circuit according to any one in claim 1-7, it is characterised in that the governor circuit includes
GL830 main control chips.
9. the interface compatibility circuit according to any one in claim 1-7, it is characterised in that the governor circuit is also wrapped
Include when the solid state hard disc of solid state hard disc or mSATA interfaces that the access device type is SATA interface, the SATA interface
The time intervals of the adjacent data of read-write twice of the solid state hard disc of solid state hard disc or the mSATA interfaces set for 0 time parameter
Put module.
10. the interface compatibility circuit according to any one in claim 1-7, it is characterised in that the governor circuit is also
Including the capacity and the access device information acquisition module of cache size of the access device for obtaining the governor circuit logic interfacing.
Priority Applications (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201621415374.0U CN206370051U (en) | 2016-12-21 | 2016-12-21 | Interface compatibility circuit |
| PCT/CN2016/113695 WO2018113029A1 (en) | 2016-12-21 | 2016-12-30 | Interface compatible device |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201621415374.0U CN206370051U (en) | 2016-12-21 | 2016-12-21 | Interface compatibility circuit |
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| CN206370051U true CN206370051U (en) | 2017-08-01 |
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| CN201621415374.0U Active CN206370051U (en) | 2016-12-21 | 2016-12-21 | Interface compatibility circuit |
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| WO (1) | WO2018113029A1 (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2018113026A1 (en) * | 2016-12-21 | 2018-06-28 | 广州炒米信息科技有限公司 | Interface compatible circuit |
Families Citing this family (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN111105841A (en) * | 2019-12-30 | 2020-05-05 | 深圳佰维存储科技股份有限公司 | Solid state disk detection equipment, detection method and switching device |
| CN114116568B (en) * | 2021-11-27 | 2023-03-24 | 深圳市锐宝智联信息有限公司 | Method for supporting double SATA hard disks by MINISITA connector |
| CN114925008A (en) * | 2022-03-24 | 2022-08-19 | 南宁磁动电子科技有限公司 | Western data hard disk electronic evidence obtaining tool |
Family Cites Families (5)
| Publication number | Priority date | Publication date | Assignee | Title |
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| CN101295226A (en) * | 2007-04-24 | 2008-10-29 | 梁国恩 | Adapter card of analog hard disk interface |
| CN101751338B (en) * | 2008-12-15 | 2012-03-07 | 中芯国际集成电路制造(上海)有限公司 | Data access control device and data access method |
| CN102521152B (en) * | 2011-11-29 | 2014-12-24 | 华为数字技术（成都）有限公司 | Grading storage method and grading storage system |
| CN205176831U (en) * | 2015-11-02 | 2016-04-20 | 深圳华北工控股份有限公司 | Automatic SATA storage facilities listens switching circuit |
| CN106776412B (en) * | 2016-12-21 | 2018-07-03 | 广州炒米信息科技有限公司 | Interface compatibility circuit |
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2016
- 2016-12-21 CN CN201621415374.0U patent/CN206370051U/en active Active
- 2016-12-30 WO PCT/CN2016/113695 patent/WO2018113029A1/en active Application Filing
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| Publication number | Priority date | Publication date | Assignee | Title |
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| WO2018113026A1 (en) * | 2016-12-21 | 2018-06-28 | 广州炒米信息科技有限公司 | Interface compatible circuit |
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| WO2018113029A1 (en) | 2018-06-28 |
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