CN206194348U

CN206194348U - A temperature collecting module,

Info

Publication number: CN206194348U
Application number: CN201621249419.1U
Authority: CN
Inventors: 皇甫鲁江; 郑灿; 李云飞; 刘利宾
Original assignee: BOE Technology Group Co Ltd
Current assignee: BOE Technology Group Co Ltd
Priority date: 2016-11-18
Filing date: 2016-11-18
Publication date: 2017-05-24
Anticipated expiration: 2026-11-18

Abstract

The utility model provides a temperature collecting module, , this pixel circuit of includes: drive transistor, include with first power cord be connected with the first ploe of receiving a mains voltage, with a nodal connection's grid and with the 2nd nodal connection's second ploe, the first transistor, include with the 2nd nodal connection's first ploe, with a control signal line connection with the grid of receiving a control signal and with a nodal connection's second ploe, first electric capacity, include with a nodal connection's first end and with the 3rd nodal connection's second end, organic light -emitting diode is configured as and is in at the during operation drive transistor's drive is luminous down, and switch error compensation circuit, with first node and/or the 2nd nodal connection is configured as the compensation the switch error of the first transistor. This pixel circuit can reduce or eliminate the switch error of threshold value compensation in -process, improves the homogeneity that display panel shows.

Description

Pixel circuit, display panel and display device

Technical Field

Embodiments of the present disclosure relate to a pixel circuit, a display panel, and a display device.

Background

In the display field, an Organic Light Emitting Diode (OLED) display panel has the characteristics of self-luminescence, high contrast, low energy consumption, wide viewing angle, high response speed, wide use temperature range, simple manufacture and the like, can be used for a flexible panel, and has a wide development prospect.

Due to the characteristics, the Organic Light Emitting Diode (OLED) display panel can be suitable for devices with display functions, such as mobile phones, displays, notebook computers, digital cameras, instruments and meters and the like.

SUMMERY OF THE UTILITY MODEL

An embodiment of the present disclosure provides a pixel circuit including: a driving transistor including a first pole connected to a first power line to receive a first power voltage, a gate connected to a first node, and a second pole connected to a second node; a first transistor including a first pole connected to the second node, a gate connected to a first control signal line to receive a first control signal, and a second pole connected to the first node; a first capacitor including a first terminal connected to the first node and a second terminal connected to a third node; an organic light emitting diode configured to emit light under the driving of the driving transistor in operation; and a switching error compensation circuit connected to the first node and/or the second node, configured to compensate for a switching error of the first transistor.

For example, in the pixel circuit provided by the embodiment of the present disclosure, the switching error compensation circuit includes a first compensation transistor, a first pole and/or a second pole of the first compensation transistor is connected to the first node, and a gate of the first compensation transistor is connected to the light emission control signal line to receive the light emission control signal.

For example, in the pixel circuit provided by the embodiment of the present disclosure, the first compensation transistor and the first transistor are manufactured by the same process.

For example, in the pixel circuit provided by the embodiment of the present disclosure, the switching error compensation circuit includes a compensation capacitor, a first end of the compensation capacitor is connected to the first node, and a second end of the compensation capacitor is connected to the second node.

For example, in the pixel circuit provided by the embodiment of the present disclosure, the switching error compensation circuit includes a second compensation transistor, a first pole of the second compensation transistor is connected to the second node, a second pole of the second compensation transistor is connected to a discharging voltage line to receive the discharging voltage, and a gate of the second compensation transistor is connected to a compensation control signal line to receive a compensation control signal.

For example, the pixel circuit provided by the embodiment of the present disclosure further includes: a data write circuit configured to receive the first control signal and a data signal and write the data signal to the third node according to the first control signal.

For example, in the pixel circuit provided by the embodiment of the present disclosure, the data writing circuit includes a second transistor, a first pole of the second transistor is connected to a data signal line to receive the data signal, a second pole of the second transistor is connected to the third node, and a gate of the second transistor is connected to the first control signal line to receive the first control signal.

For example, the pixel circuit provided by the embodiment of the present disclosure further includes: a first reference voltage writing circuit configured to receive a light emission control signal and a first reference voltage and write the first reference voltage to the third node according to the light emission control signal.

For example, in the pixel circuit provided in the embodiment of the present disclosure, the first reference voltage writing circuit includes a third transistor, a first pole of the third transistor is connected to a first reference voltage line to receive the first reference voltage, a second pole of the third transistor is connected to the third node, and a gate of the third transistor is connected to the light emission control signal line to receive the light emission control signal.

For example, the pixel circuit provided by the embodiment of the present disclosure further includes: and the light emitting control circuit is configured to receive the light emitting control signal and control the organic light emitting diode to emit light according to the light emitting control signal.

For example, in the pixel circuit provided by the embodiment of the present disclosure, the light emission control circuit includes a fourth transistor, a first pole of the fourth transistor is connected to the second node, a second pole of the fourth transistor is connected to the fourth node, a gate of the fourth transistor is connected to the light emission control signal line to receive the light emission control signal, and the organic light emitting diode includes a first pole connected to the fourth node and a second pole connected to a second power line to receive a second power supply voltage.

For example, the pixel circuit provided by the embodiment of the present disclosure further includes a second reference voltage writing circuit configured to receive a second control signal and a second reference voltage and write the second reference voltage to the third node according to the second control signal.

For example, in the pixel circuit provided in the embodiment of the present disclosure, the second reference voltage writing circuit includes a fifth transistor, a first pole of the fifth transistor is connected to a second reference voltage line to receive the second reference voltage, a second pole of the fifth transistor is connected to the third node, and a gate of the fifth transistor is connected to a second control signal line to receive the second control signal.

For example, the pixel circuit provided by the embodiment of the present disclosure further includes a discharge circuit configured to receive a second control signal and a discharge voltage and write the discharge voltage to the first node according to the second control signal.

For example, in the pixel circuit provided by the embodiment of the present disclosure, the discharge circuit includes a sixth transistor, a first pole of the sixth transistor is connected to the first node, a second pole of the sixth transistor is connected to a discharge voltage line to receive the discharge voltage, and a gate of the sixth transistor is connected to a second control signal line to receive the second control signal.

For example, the pixel circuit provided by the embodiment of the present disclosure further includes a second capacitor, wherein a first end of the second capacitor is connected to the first power line to receive the first power voltage, and a second end of the second capacitor is connected to the first node.

Embodiments of the present disclosure further provide a display panel including the pixel circuit provided in any one of the embodiments of the present disclosure.

Embodiments of the present disclosure also provide a display device including the display panel provided in any one of the embodiments of the present disclosure.

For example, the pixel circuit, the display panel and the display device provided by the embodiment of the disclosure can reduce or eliminate the switching error in the threshold compensation process, and improve the display uniformity of the display panel.

Drawings

In order to more clearly illustrate the technical solutions of the embodiments of the present disclosure, the drawings needed to be used in the description of the embodiments or related technologies will be briefly introduced below, and it is obvious that the drawings in the following description only relate to some embodiments of the present disclosure and do not limit the present disclosure.

Fig. 1 is one of schematic diagrams of a pixel circuit provided in an embodiment of the present disclosure;

fig. 2 is a second schematic diagram of a pixel circuit according to an embodiment of the disclosure;

fig. 3 is a third schematic diagram of a pixel circuit according to an embodiment of the disclosure;

FIG. 4 is a fourth schematic diagram of a pixel circuit according to an embodiment of the present disclosure;

fig. 5 is a fifth schematic diagram of a pixel circuit according to an embodiment of the disclosure;

fig. 6 is a sixth schematic diagram of a pixel circuit according to an embodiment of the disclosure;

fig. 7 is a seventh schematic diagram of a pixel circuit according to an embodiment of the disclosure;

fig. 8 is an eighth schematic diagram of a pixel circuit provided by an embodiment of the present disclosure;

fig. 9 is a schematic diagram of a display panel provided by an embodiment of the present disclosure;

fig. 10 is a schematic diagram of a display device provided by an embodiment of the present disclosure;

fig. 11 is one of driving timing diagrams of a pixel circuit according to an embodiment of the disclosure;

fig. 12 is a second driving timing diagram of a pixel circuit according to an embodiment of the disclosure;

fig. 13 is a third driving timing diagram of a pixel circuit according to an embodiment of the disclosure;

FIG. 14 is a state diagram of the shorted switch transistor before the threshold voltage end of charge turns off; and

fig. 15 is a state diagram of the threshold voltage sampling end of charge shorting switching transistor off.

Detailed Description

The technical solutions in the embodiments of the present disclosure will be described more fully hereinafter with reference to the non-limiting exemplary embodiments shown in the accompanying drawings and detailed in the following description, taken in conjunction with the accompanying drawings, which illustrate, more fully, the exemplary embodiments of the present disclosure and their various features and advantageous details. It should be noted that the features illustrated in the drawings are not necessarily drawn to scale. The present disclosure omits descriptions of well-known materials, components, and process techniques so as not to obscure the example embodiments of the present disclosure. The examples given are intended merely to facilitate an understanding of ways in which the example embodiments of the disclosure may be practiced and to further enable those of skill in the art to practice the example embodiments. Thus, these examples should not be construed as limiting the scope of the embodiments of the disclosure.

Unless otherwise specifically defined, technical or scientific terms used herein shall have the ordinary meaning as understood by those of ordinary skill in the art to which this disclosure belongs. The use of "first," "second," and similar terms in this disclosure is not intended to indicate any order, quantity, or importance, but rather is used to distinguish one element from another. Further, in the various embodiments of the present disclosure, the same or similar reference numerals denote the same or similar components.

In an Organic Light-Emitting Diode (OLED) display panel, threshold voltages of driving transistors in respective pixel units may be different from each other due to a manufacturing process, and the threshold voltages of the driving transistors may also be shifted due to, for example, temperature variation. Therefore, the difference in the threshold voltages of the respective driving transistors may also cause display unevenness of the display panel. Therefore, it is necessary to compensate for the threshold voltage of the driving transistor.

The traditional threshold voltage compensation circuit generally comprises a short-circuit switch transistor, the source electrode of the short-circuit switch transistor is connected with the drain electrode of a driving transistor, the grid electrode of the drain electrode of the short-circuit switch transistor is connected, the setting mode is matched with a corresponding driving time sequence, and in the compensation process, the short-circuit driving transistor can short-circuit the driving transistor into a diode connection so as to realize the compensation of the threshold voltage of the driving transistor. However, the effect of the threshold voltage compensation method is not ideal, and one important reason is that during the operation of the threshold voltage compensation circuit, when the short-circuited switching transistor is turned off, a capacitance-held potential error is caused, which is called a switching error (switching-induced error).

The switching error is caused by the fact that an equivalent capacitor (including an electrode overlapping parasitic capacitor and a channel capacitor) exists between the grid electrode and the drain electrode of the short-circuit switching transistor, when the storage capacitor is charged, the potential of the end connected with the grid electrode of the driving transistor is the threshold voltage of the driving transistor, and in the process of turning off the short-circuit switching transistor, charges stored in the equivalent capacitor of the short-circuit switching transistor due to bias voltage and capacity changes are injected into the storage capacitor, so that the threshold voltage signal kept on the storage capacitor generates errors.

Therefore, the non-uniformity of the threshold voltage caused by the switching error is still one of the main reasons for restricting the production yield of the organic light emitting diode display panel, and the switching error needs to be compensated.

For example, the cause of the switching error will be described with reference to fig. 14 and 15. FIG. 14 is a state diagram of the shorted switch transistor before the threshold voltage end of charge turns off; fig. 15 is a state diagram of the threshold voltage sampling end of charge shorting switching transistor off. An equivalent capacitance CTgd0 exists between the gate and the drain of the shorting switching transistor T', including an electrode overlap parasitic capacitance Col and a channel capacitance Cchn. When the charging of the storage capacitor is completed, the potential of the terminal connected to the gate of the driving transistor DT' is the threshold voltage Vth of the driving transistor. During the turn-off of the short-circuit switch transistor T ', the charge stored in the capacitor CTgd0 of the short-circuit switch transistor due to the bias voltage and the capacity change is injected into the storage capacitor C1', resulting in the Vth signal error held on the storage capacitor. Under the condition of not considering the relative capacitance of other transistors, solving a relative charge conservation equation to obtain the grid potential of the driving transistor after the short-circuit switch transistor is switched off as follows:

in the above formula, the 2 nd term and the 3 rd term are both errors generated in the turn-off process of the short-circuit switch transistor, the 2 nd term is related error of a driving transistor Vth, the 3 rd term is related error of a signal Vref-Vdt, wherein Vref is reference voltage, Vdt is voltage of a data signal, and V is_gHIs a high level voltage, V_gLIs a low level voltage. Based on the same operation, the current of the driving transistor DT is as follows:

wherein,μ_nfor the channel mobility of the driving transistor, Cox is the channel capacitance per unit area of the driving transistor, W and L are the channel width and channel length, respectively, of the driving transistor, V_DTgsIs the gate-source voltage of the drive transistor (the difference between the gate voltage and the source voltage of the drive transistor).

Due to the existence of the term related to the threshold voltage Vth of the driving transistor, the display uniformity is still affected by the non-uniform threshold voltage. In the above Vth correlation term, Cgs and Cgs0 are capacitances between the gate and source in the on and threshold states of the driving transistor, respectively, and the difference is usually not significant enough to affect the Vth correlation error. Cgd and Cgd0 are the capacitances between the gate and drain in the on and threshold states of the drive transistor, respectively, and have characteristics similar to the gate-source capacitance. However, since Cgd0 is shorted by the shorted switching transistor in the threshold state and no charge is stored, Cgd may absorb much charge after the shorted switching transistor is turned off, thereby affecting Vth-related error to some extent.

It can be seen that the Vth correlation coefficient of the error is mainly determined by the channel capacitance Cchn of the short-circuit switch transistor and the capacitance Cgd between the gate and the drain of the drive transistor, the physical process is that in the turn-off process, the conducting channel of the short-circuit switch transistor disappears, the corresponding equivalent capacitance is close to 0, and the charge originally existing in the storage capacitor C1' is also partially absorbed by the capacitance such as the capacitance Cgd between the gate and the drain of the drive transistor.

For example, the pixel circuit, the display panel, the display device and the driving method provided by the embodiment of the disclosure can reduce or eliminate the switching error in the threshold compensation process, and improve the display uniformity of the display panel.

An embodiment of the present disclosure provides a pixel circuit including: a driving transistor including a first pole connected to a first power line to receive a first power voltage, a gate connected to a first node, and a second pole connected to a second node; a first transistor including a first electrode connected to the second node, a gate connected to the first control signal line to receive the first control signal, and a second electrode connected to the first node; a first capacitor including a first terminal connected to the first node and a second terminal connected to the third node; an organic light emitting diode configured to emit light under the driving of the driving transistor in operation; and a switching error compensation circuit connected to the first node and/or the second node, configured to compensate for a switching error of the first transistor.

First embodiment

For example, an embodiment of the present disclosure provides a pixel circuit 100, as shown in fig. 1, the pixel circuit 100 includes a driving transistor DT, a first transistor T1, a first capacitor C1, an organic light emitting diode OLED, and a switching error compensation circuit 110. The driving transistor DT includes a first pole connected to the first power line to receive the first power voltage Vdd, a gate connected to the first node N1, and a second pole connected to the second node N2. The first transistor T1 includes a first pole connected to the second node N2, a gate connected to the first control signal line to receive the first control signal Sn, and a second pole connected to the first node N1. The first capacitor C1 includes a first terminal connected to the first node N1 and a second terminal connected to the third node N3. The organic light emitting diode OLED is configured to emit light under the driving of the driving transistor DT in operation. The switching error compensation circuit 110 is connected to the first node N1, and is configured to compensate for a switching error of the first transistor T1.

It should be noted that the transistors used in the embodiments of the present disclosure may be thin film transistors or field effect transistors or other switching devices with the same characteristics. The source and drain of the transistor used herein may be symmetrical in structure, so that there may be no difference in structure between the source and drain. In the embodiments of the present disclosure, in order to distinguish two poles of a transistor except for a gate, one of them is directly described as a first pole, and the other is directly described as a second pole, so that the source and the drain of all or part of the transistors in the embodiments of the present disclosure may be interchanged as necessary. In addition, the transistors can be divided into N-type and P-type transistors according to the characteristic distinction of the transistors, and the embodiments of the present disclosure are all explained by taking the P-type transistor as an example. Based on the description and teaching of the P-type transistor implementation of the present disclosure, a person of ordinary skill in the art can easily conceive of an implementation in which the embodiments of the present disclosure employ an N-type transistor without making creative efforts, and therefore, such implementations are also within the protection scope of the present disclosure.

For example, as shown in fig. 1, the pixel circuit 100 provided by the embodiment of the present disclosure further includes a data writing circuit 120, and the data writing circuit 120 is configured to receive the first control signal Sn and the data signal Vdt and write the data signal Vdt to the third node N3 according to the first control signal Sn.

For example, as shown in fig. 1, the pixel circuit 100 provided by the embodiment of the present disclosure further includes a first reference voltage writing circuit 130, and the first reference voltage writing circuit 130 is configured to receive the emission control signal EM and the first reference voltage Vref1 and write the first reference voltage Vref1 to the third node N3 according to the emission control signal EM.

For example, as shown in fig. 1, the pixel circuit 100 provided by the embodiment of the present disclosure further includes a light emission control circuit 140, and the light emission control circuit 140 is configured to receive the light emission control signal EM and control the organic light emitting diode OLED to emit light according to the light emission control signal EM.

It should be noted that the embodiments of the present disclosure include, but are not limited to, the case where the pixel circuit 100 includes the data writing circuit 120, the first reference voltage writing circuit 130, and the light emission control circuit 140, and may also be other cases, for example, the data writing circuit 120 and the first reference voltage writing circuit 130 are not included, and the data signal line is directly connected to the third node N3, and the writing of the data signal and the first reference voltage is realized by setting the timing and the voltage value of the data signal Vdt.

For example, as shown in fig. 1 and 2, in the pixel circuit 100 provided in the embodiment of the present disclosure, the switching error compensation circuit 110 includes a first compensation transistor TC1, a first pole and a second pole of the first compensation transistor TC1 are connected to the first node N1, and a gate of the first compensation transistor TC1 is connected to the emission control signal line to receive the emission control signal EM.

It should be noted that, the embodiments of the present disclosure include, but are not limited to, the first pole and the second pole of the first compensation transistor TC1 being connected to the first node N1, the first pole of the first compensation transistor TC1 being connected to the first node N1, the second pole being floating, or the second pole of the first compensation transistor TC1 being connected to the first node N1, the first pole being floating.

For example, in the pixel circuit 100 provided in the embodiment of the present disclosure, the first compensation transistor TC1 is made by the same process as the first transistor T1.

For example, since the first compensation transistor TC1 also has an equivalent capacitance, while the first transistor T1 is turned off, the charges released by the equivalent capacitance between the gate and the drain of the first transistor T1 can be fully or partially absorbed by the equivalent capacitance of the first compensation transistor TC1, so as to achieve the purpose of keeping the threshold voltage in the first capacitor C1 accurate and stable. Since the first compensation transistor TC1 and the first transistor T1 are made by the same process, so that the characteristics of the first compensation transistor TC1 and the first transistor T1 are the same or similar, the equivalent capacitance of the first compensation transistor TC1 is the same as or close to the equivalent capacitance of the first transistor T1, and the equivalent capacitance of the first compensation transistor TC1 can accurately absorb the charges released by the equivalent capacitance of the first transistor T1, thereby obtaining a better compensation effect.

For example, the equivalent capacitance of the first compensation transistor TC1 includes Ctcgs and Ctcgd, Ctcgs is the equivalent capacitance between the gate and the source of the first compensation transistor TC1, Ctcgd is the equivalent capacitance between the gate and the drain of the first compensation transistor TC1 (regardless of whether the first pole and the second pole of the first compensation transistor TC1 are connected to the first node N1 at the same time, because there is no other bypass, Ctcgd and Ctcgs of the first compensation transistor may participate in the absorption or discharge of charges together), and the equivalent capacitance of the first transistor T1 includes only the equivalent capacitance C1gd between the gate and the drain of the first transistor T1. When the first transistor T1 is turned on, the total charge amount in the equivalent capacitor C1gs between the gate and the source and the equivalent capacitor C1gd between the gate and the drain is constant, but when the first transistor T1 is turned off, the charge is distributed between C1gd and C1gs according to the circuit bias condition, resulting in the fluctuation of the equivalent capacitors C1gd and C1 gs. For example, the C1gd of the first transistor T1 may be larger than C1 gs.

For example, for the pixel circuit shown in fig. 2, only the first control signal Sn and the emission control signal EM need to be provided, which facilitates the wiring of the circuit and can improve the resolution of the display panel.

For example, as shown in fig. 1 and 2, in the pixel circuit 100 provided in the embodiment of the present disclosure, the data writing circuit 120 includes a second transistor T2, a first pole of the second transistor T2 is connected to the data signal line to receive the data signal Vdt, a second pole of the second transistor T2 is connected to the third node N3, and a gate of the second transistor T2 is connected to the first control signal line to receive the first control signal Sn.

For example, as shown in fig. 1 and 2, in the pixel circuit 100 provided in the embodiment of the present disclosure, the first reference voltage writing circuit 130 includes a third transistor T3, a first pole of the third transistor T3 is connected to a first reference voltage line to receive the first reference voltage Vref1, a second pole of the third transistor T3 is connected to a third node N3, and a gate of the third transistor T3 is connected to a light emission control signal line to receive the light emission control signal EM.

For example, as shown in fig. 1 and 2, in the pixel circuit 100 provided in the embodiment of the present disclosure, the light emission control circuit 140 includes a fourth transistor T4, a first pole of the fourth transistor T4 is connected to the second node N2, a second pole of the fourth transistor T4 is connected to the fourth node N4, a gate of the fourth transistor T4 is connected to the light emission control signal line to receive the light emission control signal EM, and the organic light emitting diode OLED includes a first pole connected to the fourth node N4 and a second pole connected to the second power line to receive the second power supply voltage Vss.

For example, the first power supply voltage Vdd is a high level voltage (e.g., 8V), and the second power supply voltage Vss is a low level voltage (e.g., 0V).

For example, the first electrode of the organic light emitting diode OLED is an anode, and the second electrode is a cathode.

It should be noted that the pixel circuit shown in fig. 2 is only one implementation of the pixel circuit shown in fig. 1, and the embodiments of the present disclosure include, but are not limited to, the implementation shown in fig. 2.

For example, on the basis of the pixel circuit shown in fig. 2, as shown in fig. 3, the pixel circuit 100 provided by the embodiment of the present disclosure further includes a second reference voltage writing circuit 150, and the second reference voltage writing circuit 150 is configured to receive the second control signal Sn-1 and the second reference voltage Vref2 and write the second reference voltage Vref2 to the third node N3 according to the second control signal Sn-1.

For example, as shown in fig. 3, in the pixel circuit 100 provided in the embodiment of the present disclosure, the second reference voltage writing circuit 150 includes a fifth transistor T5, a first pole of the fifth transistor T5 is connected to the second reference voltage line to receive the second reference voltage Vref2, a second pole of the fifth transistor T5 is connected to the third node N3, and a gate of the fifth transistor T5 is connected to the second control signal line to receive the second control signal Sn-1.

For example, the second control signal Sn-1 may be earlier than the first control signal Sn by one line scan time, that is, the second control signal Sn-1 of the pixel circuits of the current line may be implemented by the first control signal Sn of the pixel circuits of the previous line, which may simplify the design of the circuit and facilitate the wiring of the circuit.

For example, the first reference voltage Vref1 and the second reference voltage Vref2 are stable reference voltages, which may be the same voltage or different voltages.

For example, adding the second reference voltage writing circuit 150 to the first reference voltage writing circuit 130 can improve the display quality and prevent the residual signal of the previous frame from affecting the compensation of the current frame.

For example, as shown in fig. 3, the pixel circuit 100 provided by the embodiment of the present disclosure further includes a discharge circuit 160 configured to receive the second control signal Sn-1 and the discharge voltage Vini and write the discharge voltage Vini to the first node N1 according to the second control signal Sn-1.

For example, as shown in fig. 3, in the pixel circuit 100 provided in the embodiment of the present disclosure, the discharging circuit 160 includes a sixth transistor T6, a first pole of the sixth transistor T6 is connected to the first node N1, a second pole of the sixth transistor T6 is connected to the discharging voltage line to receive the discharging voltage Vini, and a gate of the sixth transistor T6 is connected to the second control signal line to receive the second control signal Sn-1.

For example, the discharge voltage Vini is a low level voltage (e.g., 0V).

For example, the first reference voltage Vref1, the second reference voltage Vref2, and the discharging voltage Vini may be the same voltage, which may simplify circuit wiring and improve the resolution of the display panel.

For example, on the basis of fig. 3, as shown in fig. 4, the pixel circuit 100 provided by the embodiment of the present disclosure further includes a second capacitor C2, a first terminal of the second capacitor C2 is connected to the first power line to receive the first power voltage Vdd, and a second terminal of the second capacitor C2 is connected to the first node N1.

For example, the provision of the second capacitor C2 may improve the stability of the pixel circuit 100.

Second embodiment

For example, an embodiment of the present disclosure provides a pixel circuit 100, as shown in fig. 5, the pixel circuit 100 includes a driving transistor DT, a first transistor T1, a first capacitor C1, an organic light emitting diode OLED, and a switching error compensation circuit 110. The driving transistor DT includes a first pole connected to the first power line to receive the first power voltage Vdd, a gate connected to the first node N1, and a second pole connected to the second node N2. The first transistor T1 includes a first pole connected to the second node N2, a gate connected to the first control signal line to receive the first control signal Sn, and a second pole connected to the first node N1. The first capacitor C1 includes a first terminal connected to the first node N1 and a second terminal connected to the third node N3. The organic light emitting diode OLED is configured to emit light under the driving of the driving transistor DT in operation. The switching error compensation circuit 110 is connected to the first node N1 and the second node N2, and configured to compensate for a switching error of the first transistor T1.

For example, as shown in fig. 5, the pixel circuit 100 provided by the embodiment of the present disclosure further includes a data writing circuit 120, and the data writing circuit 120 is configured to receive the first control signal Sn and the data signal Vdt and write the data signal Vdt to the third node N3 according to the first control signal Sn.

For example, as shown in fig. 5, the pixel circuit 100 provided by the embodiment of the present disclosure further includes a first reference voltage writing circuit 130, and the first reference voltage writing circuit 130 is configured to receive the emission control signal EM and the first reference voltage Vref1 and write the first reference voltage Vref1 to the third node N3 according to the emission control signal EM.

For example, as shown in fig. 5, the pixel circuit 100 provided by the embodiment of the present disclosure further includes a light emission control circuit 140, and the light emission control circuit 140 is configured to receive the light emission control signal EM and control the organic light emitting diode OLED to emit light according to the light emission control signal EM.

It should be noted that the embodiments of the present disclosure include, but are not limited to, the case where the pixel circuit 100 includes the data writing circuit 120, the first reference voltage writing circuit 130, and the light emission control circuit 140, and may be other cases.

For example, as shown in fig. 5 and 6, in the pixel circuit 100 provided in the embodiment of the present disclosure, the switching error compensation circuit 110 includes a compensation capacitor CC, a first terminal of the compensation capacitor CC is connected to the first node N1, and a second terminal of the compensation capacitor CC is connected to the second node N2.

For example, due to the compensation capacitor CC, while the first transistor T1 is turned off, the charges released by the equivalent capacitor between the gate and the drain of the first transistor T1 can be fully or partially absorbed by the compensation capacitor CC, so as to achieve the purpose of maintaining the threshold voltage of the first capacitor C1 accurate and stable. The capacitance value of the compensation capacitor CC can be obtained by, for example, an experimental method.

For example, as shown in fig. 5 and 6, in the pixel circuit 100 provided in the embodiment of the present disclosure, the data writing circuit 120 includes a second transistor T2, a first pole of the second transistor T2 is connected to the data signal line to receive the data signal Vdt, a second pole of the second transistor T2 is connected to the third node N3, and a gate of the second transistor T2 is connected to the first control signal line to receive the first control signal Sn.

For example, as shown in fig. 5 and 6, in the pixel circuit 100 provided in the embodiment of the present disclosure, the first reference voltage writing circuit 130 includes a third transistor T3, a first pole of the third transistor T3 is connected to a first reference voltage line to receive the first reference voltage Vref1, a second pole of the third transistor T3 is connected to a third node N3, and a gate of the third transistor T3 is connected to a light emission control signal line to receive the light emission control signal EM.

For example, as shown in fig. 5 and 6, in the pixel circuit 100 provided in the embodiment of the present disclosure, the light emission control circuit 140 includes a fourth transistor T4, a first pole of the fourth transistor T4 is connected to the second node N2, a second pole of the fourth transistor T4 is connected to the fourth node N4, a gate of the fourth transistor T4 is connected to the light emission control signal line to receive the light emission control signal EM, and the organic light emitting diode OLED includes a first pole connected to the fourth node N4 and a second pole connected to the second power line to receive the second power supply voltage Vss.

It should be noted that the pixel circuit shown in fig. 6 is only one implementation of the pixel circuit shown in fig. 5, and the embodiments of the present disclosure include, but are not limited to, the implementation shown in fig. 6.

For example, for the pixel circuit shown in fig. 6, only the first control signal Sn and the emission control signal EM need to be provided, which facilitates the wiring of the circuit and can improve the resolution of the display panel.

For example, in this embodiment, the pixel circuit may further include a second reference voltage writing circuit, a discharging circuit, a second capacitor, and the like (not shown in the figure), and the implementation manner thereof is similar to that of the first embodiment, and is not described herein again.

Third embodiment

For example, an embodiment of the present disclosure provides a pixel circuit 100, as shown in fig. 7, the pixel circuit 100 includes a driving transistor DT, a first transistor T1, a first capacitor C1, an organic light emitting diode OLED, and a switching error compensation circuit 110. The driving transistor DT includes a first pole connected to the first power line to receive the first power voltage Vdd, a gate connected to the first node N1, and a second pole connected to the second node N2. The first transistor T1 includes a first pole connected to the second node N2, a gate connected to the first control signal line to receive the first control signal Sn, and a second pole connected to the first node N1. The first capacitor C1 includes a first terminal connected to the first node N1 and a second terminal connected to the third node N3. The organic light emitting diode OLED is configured to emit light under the driving of the driving transistor DT in operation. The switching error compensation circuit 110 is connected to the second node N2 and configured to compensate for a switching error of the first transistor T1.

For example, as shown in fig. 7, the pixel circuit 100 provided by the embodiment of the present disclosure further includes a data writing circuit 120, and the data writing circuit 120 is configured to receive the first control signal Sn and the data signal Vdt and write the data signal Vdt to the third node N3 according to the first control signal Sn.

For example, as shown in fig. 7, the pixel circuit 100 provided by the embodiment of the present disclosure further includes a first reference voltage writing circuit 130, and the first reference voltage writing circuit 130 is configured to receive the emission control signal EM and the first reference voltage Vref1 and write the first reference voltage Vref1 to the third node N3 according to the emission control signal EM.

For example, as shown in fig. 7, the pixel circuit 100 provided by the embodiment of the present disclosure further includes a light emission control circuit 140, and the light emission control circuit 140 is configured to receive the light emission control signal EM and control the organic light emitting diode OLED to emit light according to the light emission control signal EM.

For example, as shown in fig. 7 and 8, in the pixel circuit 100 provided in the embodiment of the present disclosure, the switching error compensation circuit 110 includes a second compensation transistor TC2, a first pole of the second compensation transistor TC2 is connected to the second node N2, a second pole of the second compensation transistor TC2 is connected to the discharging voltage line to receive the discharging voltage Vini, and a gate of the second compensation transistor TC2 is connected to the compensation control signal line to receive the compensation control signal NSn.

For example, while the first transistor T1 is turned off, the second compensation transistor TC2 is turned on by timing control, and the source potential of the first transistor T1 is pulled down to the discharge voltage Vini (e.g., 0V), causing the channel bias state of the first transistor T1 to momentarily flip (source and drain exchange). Thus, most of the channel charges will be driven to the source of the first transistor T1 in the normal operation state during the channel-clearing process, so as to avoid affecting the threshold voltage maintained in the first capacitor C1.

For example, as shown in fig. 7 and 8, in the pixel circuit 100 provided in the embodiment of the present disclosure, the data writing circuit 120 includes a second transistor T2, a first pole of the second transistor T2 is connected to the data signal line to receive the data signal Vdt, a second pole of the second transistor T2 is connected to the third node N3, and a gate of the second transistor T2 is connected to the first control signal line to receive the first control signal Sn.

For example, as shown in fig. 7 and 8, in the pixel circuit 100 provided in the embodiment of the present disclosure, the first reference voltage writing circuit 130 includes a third transistor T3, a first pole of the third transistor T3 is connected to the first reference voltage line to receive the first reference voltage Vref1, a second pole of the third transistor T3 is connected to the third node N3, and a gate of the third transistor T3 is connected to the light emission control signal line to receive the light emission control signal EM.

For example, as shown in fig. 7 and 8, in the pixel circuit 100 provided in the embodiment of the present disclosure, the light emission control circuit 140 includes a fourth transistor T4, a first pole of the fourth transistor T4 is connected to the second node N2, a second pole of the fourth transistor T4 is connected to the fourth node N4, a gate of the fourth transistor T4 is connected to the light emission control signal line to receive the light emission control signal EM, and the organic light emitting diode OLED includes a first pole connected to the fourth node N4 and a second pole connected to the second power line to receive the second power supply voltage Vss.

It should be noted that the pixel circuit shown in fig. 8 is only one implementation of the pixel circuit shown in fig. 7, and the embodiments of the present disclosure include, but are not limited to, the implementation shown in fig. 8.

The switching error compensation circuits 110 in the first, second, and third embodiments are implemented differently, but can compensate for the switching error of the first transistor T1. Thus, implementations of the switching error compensation circuit 110 in these embodiments may be used in combination without conflict.

Fourth embodiment

The embodiment of the present disclosure further provides a display panel 10, as shown in fig. 9, the display panel 10 includes the pixel circuit 100 provided in any one of the embodiments of the present disclosure.

For example, as shown in fig. 9, the display panel 10 provided in the embodiment of the present disclosure further includes: a data driver 11, a scan driver 12, and a controller 13. The data driver 11 is configured to supply the data signal Vdt to the pixel circuit 100; the scan driver 12 is configured to provide the light emission control signal EM, the first control signal Sn, the second control signal Sn-1, and the compensation control signal NSn to the pixel circuit 100; the controller 13 is configured to provide control instructions to the data driver 11 and the scan driver 12 to cause the data driver 11 and the scan driver 12 to operate in cooperation.

Fifth embodiment

Embodiments of the present disclosure also provide a display device 1, as shown in fig. 10, the display device 1 includes the display panel 10 provided in any embodiment of the present disclosure.

For example, the display device 1 provided by the embodiment of the present disclosure may include any product or component having a display function, such as a mobile phone, a tablet computer, a television, a display, a notebook computer, a digital photo frame, and a navigator.

Sixth embodiment

The embodiment of the present disclosure further provides a driving method of the pixel circuit 100 provided in any embodiment of the present disclosure, which includes a reset phase t1, a data writing phase t2, a switching error compensation phase t3, and a light emitting phase t 4. In the reset phase t1, the first node N1 is reset; in the data writing phase t2, writing the data signal Vdt; compensating for a switching error of the first transistor T1 during a switching error compensation period T3; in the light emitting period t4, the organic light emitting diode OLED is driven to emit light.

For example, in the driving method provided by the embodiment of the present disclosure, for the pixel circuit shown in fig. 2, that is, the pixel circuit 100 includes a driving transistor DT, a first transistor T1, a first capacitor C1, an organic light emitting diode OLED, a switching error compensation circuit 110, a data writing circuit 120, a first reference voltage writing circuit 130, and a light emission control circuit 140. The driving transistor DT includes a first pole connected to the first power line to receive the first power voltage Vdd, a gate connected to the first node N1, and a second pole connected to the second node N2. The first transistor T1 includes a first pole connected to the second node N2, a gate connected to the first control signal line to receive the first control signal Sn, and a second pole connected to the first node N1. The first capacitor C1 includes a first terminal connected to the first node N1 and a second terminal connected to the third node N3. The organic light emitting diode OLED is configured to emit light under the driving of the driving transistor DT in operation. The switching error compensation circuit 110 includes a first compensation transistor TC1, a first pole and a second pole of the first compensation transistor TC1 are connected to the first node N1, and a gate of the first compensation transistor TC1 is connected to the emission control signal line to receive the emission control signal EM. The data writing circuit 120 includes a second transistor T2, a first pole of the second transistor T2 is connected to the data signal line to receive the data signal Vdt, a second pole of the second transistor T2 is connected to the third node N3, and a gate of the second transistor T2 is connected to the first control signal line to receive the first control signal Sn. The first reference voltage writing circuit 130 includes a third transistor T3, a first pole of the third transistor T3 is connected to a first reference voltage line to receive the first reference voltage Vref1, a second pole of the third transistor T3 is connected to the third node N3, and a gate of the third transistor T3 is connected to a light emission control signal line to receive the light emission control signal EM. The light emission control circuit 140 includes a fourth transistor T4, a first electrode of the fourth transistor T4 connected to the second node N2, a second electrode of the fourth transistor T4 connected to the fourth node N4, a gate electrode of the fourth transistor T4 connected to the light emission control signal line to receive the light emission control signal EM, and an organic light emitting diode (oled) T4

The OLED includes a first pole connected to the fourth node N4 and a second pole connected to the second power line to receive the second power voltage Vss. The driving timing thereof is as shown in fig. 11.

For example, as shown in fig. 11, in the reset phase t1, the first control signal Sn is an on voltage, and the emission control signal EM is an on voltage; in the data writing phase t2, the first control signal Sn is an on voltage, and the emission control signal EM is an off voltage; in the switching error compensation stage t3, the first control signal Sn is a turn-off voltage, and the emission control signal EM is a turn-off voltage; in the light-emitting period t4, the first control signal Sn is an off voltage, and the light-emitting control signal EM is an on voltage.

It should be noted that the turn-on voltage in the embodiments of the present disclosure refers to a voltage that can turn on the first pole and the second pole of the corresponding transistor, and the turn-off voltage refers to a voltage that can turn off the first pole and the second pole of the corresponding transistor. When the transistor is a P-type transistor, the turn-on voltage is a low voltage (e.g., 0V) and the turn-off voltage is a high voltage (e.g., 5V); when the transistor is an N-type transistor, the turn-on voltage is a high voltage (e.g., 5V) and the turn-off voltage is a low voltage (e.g., 0V). The driving waveforms shown in fig. 11 to 13 are all described by taking P-type transistors as an example, that is, the on-voltage is a low voltage (e.g., 0V) and the off-voltage is a high voltage (e.g., 5V).

For example, the operation of the pixel circuit will be described below by taking the pixel circuit shown in fig. 2 and the driving timing shown in fig. 11 as examples.

For example, in the reset period t1, the first control signal Sn is a low level voltage, and the emission control signal EM is a low level voltage. The first transistor T1, the second transistor T2, the third transistor T3, and the fourth transistor T4 are all turned on (i.e., the source and the drain are turned on), the third transistor T3 writes the first reference voltage Vref1 into the third node, the voltage of the third node N3 is the first reference voltage Vref1, the second power supply voltage Vss is written into the first node N1 through the fourth transistor T4 and the first transistor T1, and the voltage of the first node N1 is the second power supply voltage Vss, that is, the pixel circuit is reset.

In the data writing period t2, the first control signal Sn is at a low level voltage, and the emission control signal EM is at a high level voltage. The first transistor T1 and the second transistor T2 are turned on, the third transistor T3 and the fourth transistor T4 are turned off (i.e., the source and the drain are not turned on), the second transistor T2 writes the data signal Vdt into the third node N3, the voltage of the third node is Vdt, the voltage of the first node N1 is Vdd + Vth, Vth is the threshold voltage of the driving transistor DT, and the voltage difference across the first capacitor C1 is Vdd + Vth-Vdt.

In the switching error compensation period t3, the first control signal Sn is a high level voltage, and the emission control signal EM is a high level voltage. The first transistor T1, the second transistor T2, the third transistor T3, and the fourth transistor T4 are turned off. The voltage difference across the first capacitor C1 is maintained at Vdd + Vth-Vdt. Since the first compensation transistor TC1 also has an equivalent capacitance, while the first transistor T1 is turned off, the charges released by the equivalent capacitance between the gate and the drain of the first transistor T1 can be fully or partially absorbed by the equivalent capacitance of the first compensation transistor TC1, so as to achieve the purpose of maintaining the threshold voltage in the first capacitor C1 accurate and stable. Since the first compensation transistor TC1 is made by the same process as the first transistor T1, so that the characteristics of the first compensation transistor TC1 are the same as or similar to those of the first transistor T1, the equivalent capacitance of the first compensation transistor TC1 is the same as or close to that of the first transistor T1, and the equivalent capacitance of the first compensation transistor TC1 accurately absorbs the charge released by the equivalent capacitance of the first transistor T1.

In the light emitting period t4, the first control signal Sn is a high level voltage, and the light emitting control signal EM is a low level voltage. The first transistor T1 and the second transistor T2 are turned off, and the third transistor T3 and the fourth transistor T4 are turned on. The third transistor T3 writes the first reference voltage Vref1 into the third node again, the voltage of the third node N3 is the first reference voltage Vref1, and at this time, the voltage of the first node N1 is changed to Vref1+ Vdd + Vth-Vdt due to the bootstrap effect of the first capacitor C1. The light emitting current Ioled flows into the organic light emitting diode OLED through the driving transistor DT and the fourth transistor T4, and the organic light emitting diode OLED emits light. The light emission current Ioled satisfies the following saturation current formula:

K(Vgs-Vth)²＝K(Vref1+Vdd+Vth-Vdt-Vdd-Vth)²＝K(Vref1-Vdt)²

wherein,μ_nfor the channel mobility of the driving transistor, Cox is the channel capacitance per unit area of the driving transistor, W and L are the channel width and channel length, respectively, of the driving transistor, and Vgs is the gate-source voltage (the difference between the gate voltage and the source voltage of the driving transistor) of the driving transistor.

It can be seen from the above equation that the current flowing through the OLED is independent of the threshold voltage of the driving transistor DT. Therefore, the present pixel circuit well compensates the threshold voltage of the driving transistor DT.

For example, in the driving method provided by the embodiment of the present disclosure, for the pixel circuit shown in fig. 3 or fig. 4, that is, the pixel circuit 100 includes the driving transistor DT, the first transistor T1, the first capacitor C1, the organic light emitting diode OLED, the switching error compensation circuit 110, the data writing circuit 120, the first reference voltage writing circuit 130, the light emission control circuit 140, the second reference voltage writing circuit 150, and the discharging circuit 160, the pixel circuit 100 shown in fig. 4 further includes the second capacitor C2. The driving transistor DT includes a first pole connected to the first power line to receive the first power voltage Vdd, a gate connected to the first node N1, and a second pole connected to the second node N2. The first transistor T1 includes a first pole connected to the second node N2, a gate connected to the first control signal line to receive the first control signal Sn, and a second pole connected to the first node N1. The first capacitor C1 includes a first terminal connected to the first node N1 and a second terminal connected to the third node N3. The organic light emitting diode OLED is configured to emit light under the driving of the driving transistor DT in operation. The switching error compensation circuit 110 includes a first compensation transistor TC1, a first pole and a second pole of the first compensation transistor TC1 are connected to the first node N1, and a gate of the first compensation transistor TC1 is connected to the emission control signal line to receive the emission control signal EM. The data writing circuit 120 includes a second transistor T2, a first pole of the second transistor T2 is connected to the data signal line to receive the data signal Vdt, a second pole of the second transistor T2 is connected to the third node N3, and a gate of the second transistor T2 is connected to the first control signal line to receive the first control signal Sn. The first reference voltage writing circuit 130 includes a third transistor T3, a first pole of the third transistor T3 is connected to a first reference voltage line to receive the first reference voltage Vref1, a second pole of the third transistor T3 is connected to the third node N3, and a gate of the third transistor T3 is connected to a light emission control signal line to receive the light emission control signal EM. The light emission control circuit 140 includes a fourth transistor T4, a first pole of the fourth transistor T4 is connected to the second node N2, a second pole of the fourth transistor T4 is connected to the fourth node N4, a gate of the fourth transistor T4 is connected to the light emission control signal line to receive the light emission control signal EM, and the organic light emitting diode OLED includes a first pole connected to the fourth node N4 and a second pole connected to the second power line to receive the second power voltage Vss. The second reference voltage writing circuit 150 includes a fifth transistor T5, a first pole of the fifth transistor T5 is connected to the second reference voltage line to receive the second reference voltage Vref2, a second pole of the fifth transistor T5 is connected to the third node N3, and a gate of the fifth transistor T5 is connected to the second control signal line to receive the second control signal Sn-1. The discharging circuit 160 includes a sixth transistor T6, a first pole of the sixth transistor T6 is connected to the first node N1, a second pole of the sixth transistor T6 is connected to a discharging voltage line to receive the discharging voltage Vini, and a gate of the sixth transistor T6 is connected to the second control signal line to receive the second control signal Sn-1. A first terminal of the second capacitor C2 in the pixel circuit shown in fig. 4 is connected to the first power line for receiving the first power voltage Vdd, and a second terminal of the second capacitor C2 is connected to the first node N1. The driving timing thereof is as shown in fig. 12.

For example, as shown in fig. 12, in the reset period t1, the first control signal Sn is an off voltage, the second control signal Sn-1 is an on voltage, and the emission control signal EM is an off voltage; in the data writing phase t2, the first control signal Sn is a turn-on voltage, the second control signal Sn-1 is a turn-off voltage, and the light-emitting control signal EM is a turn-off voltage; in the switching error compensation stage t3, the first control signal Sn is a turn-off voltage, the second control signal Sn-1 is a turn-off voltage, and the emission control signal EM is a turn-off voltage; in the light-emitting period t4, the first control signal Sn is an off voltage, the second control signal Sn-1 is an off voltage, and the light-emitting control signal EM is an on voltage.

For example, as shown in fig. 12, the driving method of the pixel circuit 100 shown in fig. 3 or 4 may further include a reset stabilization phase t1 ', and the reset stabilization phase t 1' is between the reset phase t1 and the data write phase t 2. In the reset stable period t 1', the first control signal Sn is an off voltage, the second control signal Sn-1 is an off voltage, and the emission control signal EM is an off voltage. For example, the reset stable period t 1' may provide a stable period after the circuit is reset, so as to improve the stability of the circuit.

For example, in the driving method provided by the embodiment of the present disclosure, for the pixel circuit shown in fig. 6, that is, the pixel circuit 100 includes a driving transistor DT, a first transistor T1, a first capacitor C1, an organic light emitting diode OLED, a switching error compensation circuit 110, a data writing circuit 120, a first reference voltage writing circuit 130, and a light emission control circuit 140. The driving transistor DT includes a first pole connected to the first power line to receive the first power voltage Vdd, a gate connected to the first node N1, and a second pole connected to the second node N2. The first transistor T1 includes a first pole connected to the second node N2, a gate connected to the first control signal line to receive the first control signal Sn, and a second pole connected to the first node N1. The first capacitor C1 includes a first terminal connected to the first node N1 and a second terminal connected to the third node N3. The organic light emitting diode OLED is configured to emit light under the driving of the driving transistor DT in operation. The switching error compensation circuit 110 includes a compensation capacitor CC, a first terminal of which is connected to the first node N1, and a second terminal of which is connected to the second node N2. The data writing circuit 120 includes a second transistor T2, a first pole of the second transistor T2 is connected to the data signal line to receive the data signal Vdt, a second pole of the second transistor T2 is connected to the third node N3, and a gate of the second transistor T2 is connected to the first control signal line to receive the first control signal Sn. The first reference voltage writing circuit 130 includes a third transistor T3, a first pole of the third transistor T3 is connected to a first reference voltage line to receive the first reference voltage Vref1, a second pole of the third transistor T3 is connected to the third node N3, and a gate of the third transistor T3 is connected to a light emission control signal line to receive the light emission control signal EM. The light emission control circuit 140 includes a fourth transistor T4, a first pole of the fourth transistor T4 is connected to the second node N2, a second pole of the fourth transistor T4 is connected to the fourth node N4, a gate of the fourth transistor T4 is connected to the light emission control signal line to receive the light emission control signal EM, and the organic light emitting diode OLED includes a first pole connected to the fourth node N4 and a second pole connected to the second power line to receive the second power voltage Vss. The driving timing thereof is as shown in fig. 11.

For example, in the driving method provided by the embodiment of the present disclosure, for the pixel circuit shown in fig. 8, that is, the pixel circuit 100 includes a driving transistor DT, a first transistor T1, a first capacitor C1, an organic light emitting diode OLED, a switching error compensation circuit 110, a data writing circuit 120, a first reference voltage writing circuit 130, and a light emission control circuit 140. The driving transistor DT includes a first pole connected to the first power line to receive the first power voltage Vdd, a gate connected to the first node N1, and a second pole connected to the second node N2. The first transistor T1 includes a first pole connected to the second node N2, a gate connected to the first control signal line to receive the first control signal Sn, and a second pole connected to the first node N1. The first capacitor C1 includes a first terminal connected to the first node N1 and a second terminal connected to the third node N3. The organic light emitting diode OLED is configured to emit light under the driving of the driving transistor DT in operation. The switching error compensation circuit 110 includes a second compensation transistor TC2, a first pole of the second compensation transistor TC2 is connected to the second node N2, a second pole of the second compensation transistor TC2 is connected to the discharging voltage line to receive the discharging voltage Vini, and a gate of the second compensation transistor TC2 is connected to the compensation control signal line to receive the compensation control signal NSn. The data writing circuit 120 includes a second transistor T2, a first pole of the second transistor T2 is connected to the data signal line to receive the data signal Vdt, a second pole of the second transistor T2 is connected to the third node N3, and a gate of the second transistor T2 is connected to the first control signal line to receive the first control signal Sn. The first reference voltage writing circuit 130 includes a third transistor T3, a first pole of the third transistor T3 is connected to a first reference voltage line to receive the first reference voltage Vref1, a second pole of the third transistor T3 is connected to the third node N3, and a gate of the third transistor T3 is connected to a light emission control signal line to receive the light emission control signal EM. The light emission control circuit 140 includes a fourth transistor T4, a first pole of the fourth transistor T4 is connected to the second node N2, a second pole of the fourth transistor T4 is connected to the fourth node N4, a gate of the fourth transistor T4 is connected to the light emission control signal line to receive the light emission control signal EM, and the organic light emitting diode OLED includes a first pole connected to the fourth node N4 and a second pole connected to the second power line to receive the second power voltage Vss. The driving timing thereof is as shown in fig. 13.

For example, as shown in fig. 13, in the reset phase t1, the first control signal Sn is an on voltage, the compensation control signal NSn is an off voltage, and the emission control signal EM is an on voltage; in the data writing phase t2, the first control signal Sn is an on voltage, the compensation control signal NSn is an off voltage, and the emission control signal EM is an off voltage; in the switching error compensation stage t3, the first control signal Sn is a turn-off voltage, the compensation control signal NSn is a turn-on voltage, and the emission control signal EM is a turn-off voltage; in the light-emitting period t4, the first control signal Sn is an off voltage, the compensation control signal NSn is an off voltage, and the light-emitting control signal EM is an on voltage.

For example, as shown in fig. 13, the driving method of the pixel circuit 100 shown in fig. 8 may further include a compensation stabilization phase t3 ', and the compensation stabilization phase t 3' is between the switching error compensation phase t3 and the light emitting phase t 4. In the compensation stable period t 3', the first control signal Sn is an off voltage, the compensation control signal NSn is an off voltage, and the emission control signal EM is an off voltage. For example, the compensation stabilization period t 3' may provide a stabilization period after the circuit switching error compensation, so as to improve the stability of the circuit.

For example, as shown in fig. 13, in the driving method of the pixel circuit 100 shown in fig. 8, when the first control signal Sn is changed from the on-voltage to the off-voltage, the compensation control signal NSn is synchronously changed from the off-voltage to the on-voltage, that is, when the first control signal Sn is changed from the on-voltage to the off-voltage at the time of the intersection of the data writing period t2 and the compensation period t3, the compensation control signal NSn is synchronously changed from the off-voltage to the on-voltage.

The pixel circuit, the display panel, the display device and the driving method provided by the embodiment of the disclosure can reduce or eliminate the switching error in the threshold compensation process, and improve the display uniformity of the display panel.

Although the present disclosure has been described in detail hereinabove with respect to general illustrations and specific embodiments, it will be apparent to those skilled in the art that modifications or improvements may be made thereto based on the embodiments of the disclosure. Accordingly, such modifications and improvements are intended to be within the scope of this disclosure, as claimed.

Claims

1. A pixel circuit, comprising:

a driving transistor including a first pole connected to a first power line to receive a first power voltage, a gate connected to a first node, and a second pole connected to a second node;

a first transistor including a first pole connected to the second node, a gate connected to a first control signal line to receive a first control signal, and a second pole connected to the first node;

a first capacitor including a first terminal connected to the first node and a second terminal connected to a third node;

an organic light emitting diode configured to emit light under the driving of the driving transistor in operation; and

a switching error compensation circuit connected with the first node and/or the second node and configured to compensate for a switching error of the first transistor.

2. The pixel circuit according to claim 1, wherein the switching error compensation circuit comprises a first compensation transistor, a first pole and/or a second pole of the first compensation transistor is connected to the first node, and a gate of the first compensation transistor is connected to a light emission control signal line to receive a light emission control signal.

3. The pixel circuit according to claim 2, wherein the first compensation transistor is fabricated by a same process as the first transistor.

4. The pixel circuit according to claim 1, wherein the switching error compensation circuit comprises a compensation capacitor, a first terminal of the compensation capacitor is connected to the first node, and a second terminal of the compensation capacitor is connected to the second node.

5. The pixel circuit according to claim 1, wherein the switching error compensation circuit comprises a second compensation transistor having a first pole coupled to the second node, a second pole coupled to a discharging voltage line to receive the discharging voltage, and a gate coupled to a compensation control signal line to receive a compensation control signal.

6. The pixel circuit according to any one of claims 1 to 5, further comprising:

a data write circuit configured to receive the first control signal and a data signal and write the data signal to the third node according to the first control signal.

7. The pixel circuit according to claim 6, wherein the data writing circuit comprises a second transistor, a first pole of the second transistor is connected to a data signal line to receive the data signal, a second pole of the second transistor is connected to the third node, and a gate of the second transistor is connected to the first control signal line to receive the first control signal.

8. The pixel circuit according to any one of claims 1 to 5, further comprising:

a first reference voltage writing circuit configured to receive a light emission control signal and a first reference voltage and write the first reference voltage to the third node according to the light emission control signal.

9. The pixel circuit according to claim 8, wherein the first reference voltage writing circuit includes a third transistor, a first pole of the third transistor is connected to a first reference voltage line to receive the first reference voltage, a second pole of the third transistor is connected to the third node, and a gate of the third transistor is connected to the light emission control signal line to receive the light emission control signal.

10. The pixel circuit according to any one of claims 1 to 5, further comprising:

and the light emitting control circuit is configured to receive the light emitting control signal and control the organic light emitting diode to emit light according to the light emitting control signal.

11. The pixel circuit according to claim 10, wherein the light emission control circuit comprises a fourth transistor, a first pole of the fourth transistor is connected to the second node, a second pole of the fourth transistor is connected to a fourth node, a gate of the fourth transistor is connected to the light emission control signal line to receive the light emission control signal, and the organic light emitting diode comprises a first pole connected to the fourth node and a second pole connected to a second power line to receive a second power supply voltage.

12. The pixel circuit according to any one of claims 1 to 5, further comprising:

a second reference voltage writing circuit configured to receive a second control signal and a second reference voltage and write the second reference voltage to the third node according to the second control signal.

13. The pixel circuit according to claim 12, wherein the second reference voltage writing circuit comprises a fifth transistor, a first pole of the fifth transistor is connected to a second reference voltage line to receive the second reference voltage, a second pole of the fifth transistor is connected to the third node, and a gate of the fifth transistor is connected to a second control signal line to receive the second control signal.

14. The pixel circuit according to any one of claims 1 to 5, further comprising:

a discharge circuit configured to receive a second control signal and a discharge voltage and write the discharge voltage to the first node according to the second control signal.

15. The pixel circuit according to claim 14, wherein the discharge circuit comprises a sixth transistor having a first pole connected to the first node, a second pole connected to a discharge voltage line to receive the discharge voltage, and a gate connected to a second control signal line to receive the second control signal.

16. The pixel circuit according to any one of claims 1 to 5, further comprising:

a second capacitor, wherein a first terminal of the second capacitor is connected to the first power line to receive the first power voltage, and a second terminal of the second capacitor is connected to the first node.

17. A display panel comprising the pixel circuit according to any one of claims 1 to 16.

18. A display device characterized by comprising the display panel according to claim 17.