CN206179856U - Superchip packaging structure that reroutes - Google Patents
Superchip packaging structure that reroutes Download PDFInfo
- Publication number
- CN206179856U CN206179856U CN201621112557.5U CN201621112557U CN206179856U CN 206179856 U CN206179856 U CN 206179856U CN 201621112557 U CN201621112557 U CN 201621112557U CN 206179856 U CN206179856 U CN 206179856U
- Authority
- CN
- China
- Prior art keywords
- chip
- layer
- salient point
- insulant
- reroutes
- Prior art date
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- 238000004806 packaging method and process Methods 0.000 title abstract description 4
- 239000002184 metal Substances 0.000 claims description 20
- 229910052751 metal Inorganic materials 0.000 claims description 20
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 claims 1
- 239000010931 gold Substances 0.000 claims 1
- 229910052737 gold Inorganic materials 0.000 claims 1
- 238000012536 packaging technology Methods 0.000 abstract description 3
- 239000011810 insulating material Substances 0.000 abstract 4
- 238000012856 packing Methods 0.000 abstract 2
- 230000002093 peripheral effect Effects 0.000 abstract 2
- 238000000034 method Methods 0.000 description 14
- 239000000463 material Substances 0.000 description 13
- 238000007747 plating Methods 0.000 description 10
- 239000000758 substrate Substances 0.000 description 8
- 238000005538 encapsulation Methods 0.000 description 6
- 238000004519 manufacturing process Methods 0.000 description 6
- 239000000047 product Substances 0.000 description 6
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 5
- 229910052802 copper Inorganic materials 0.000 description 5
- 239000010949 copper Substances 0.000 description 5
- 230000015572 biosynthetic process Effects 0.000 description 3
- 238000009713 electroplating Methods 0.000 description 3
- 238000005530 etching Methods 0.000 description 3
- 239000004744 fabric Substances 0.000 description 3
- 238000007639 printing Methods 0.000 description 3
- XEEYBQQBJWHFJM-UHFFFAOYSA-N Iron Chemical compound [Fe] XEEYBQQBJWHFJM-UHFFFAOYSA-N 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 238000005516 engineering process Methods 0.000 description 2
- 238000000465 moulding Methods 0.000 description 2
- 229910000863 Ferronickel Inorganic materials 0.000 description 1
- 238000010276 construction Methods 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 238000005868 electrolysis reaction Methods 0.000 description 1
- 238000011900 installation process Methods 0.000 description 1
- 238000009413 insulation Methods 0.000 description 1
- 229910052742 iron Inorganic materials 0.000 description 1
- KFZAUHNPPZCSCR-UHFFFAOYSA-N iron zinc Chemical compound [Fe].[Zn] KFZAUHNPPZCSCR-UHFFFAOYSA-N 0.000 description 1
- 239000000203 mixture Substances 0.000 description 1
- 239000004065 semiconductor Substances 0.000 description 1
- 239000011265 semifinished product Substances 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
- H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
- H01L21/568—Temporary substrate used as encapsulation process aid
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/04105—Bonding areas formed on an encapsulation of the semiconductor or solid-state body, e.g. bonding areas on chip-scale packages
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
- H01L2224/12105—Bump connectors formed on an encapsulation of the semiconductor or solid-state body, e.g. bumps on chip-scale packages
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
- H01L2224/19—Manufacturing methods of high density interconnect preforms
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/93—Batch processes
- H01L2224/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
- H01L2224/96—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being encapsulated in a common layer, e.g. neo-wafer or pseudo-wafer, said common layer being separable into individual assemblies after connecting
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/30—Technical effects
- H01L2924/35—Mechanical effects
- H01L2924/351—Thermal stress
- H01L2924/3511—Warping
Landscapes
- Production Of Multi-Layered Print Wiring Board (AREA)
Abstract
The utility model relates to a superchip packaging structure that reroutes, the structure includes metallic wiring layer (4), metallic wiring layer (4) openly are provided with bump (1), bump (1) facing is equipped with chip (2), the pad of chip (2) is connected with the bump, bump (1) and chip (2) peripheral packing has insulating material (3), metallic wiring layer (4) back is provided with pin wire way layer (5), the peripheral packing in metallic wiring layer (4) and pin wire way layer (5) has insulating material (3), insulating material (3) are exposed at pin wire way layer (5) the back, the ball regional setting of planting that insulating material (3) are exposed on pin wire way layer (5) has pombe (6). The utility model relates to a superchip packaging structure that reroutes, high -performance electric connection and good to ensure the reliability of are realized to it, form the high density packaging technology that reroutes.
Description
Technical field
This utility model is related to a kind of superchip and reroutes encapsulating structure, belongs to technical field of semiconductor encapsulation.
Background technology
Current chip sized package（CSP）Technique mainly has：
First, in chip surface wire bonding after chip is first mounted on lead frame or substrate, or chip surface two
Secondary wiring makes and be inverted on lead frame or substrate carrying out molding encapsulation and rear operation again after salient point；
2nd, soldered ball is made at wiring layer Pad after the secondary wiring of chip surface, then carries out molding encapsulation（Or bare chip）And
Operation afterwards.
Current chip sized package（CSP）Technique has the following disadvantages and defect：
1st, as encapsulating products miniaturization, ultrathin, highdensity requirement are improved constantly, to lead frame or substrate system
It is required also miniaturization, ultrathin, high density, lead frame or substrate manufacture process is yielding, warpage, difficulty is bigger, and then
Cause packaging technology difficulty big, high cost；
2nd, using the product of lead key closing process, limited by bonding wire camber and arc length, the thickness and size of product
It is impossible to accomplish less, while wire bonding cannot accomplish VHD, and routing inefficiency；
3rd, using reverse installation process or the product of wafer level packaging, chip needs secondary wiring to make salient point, early stage manufacture
It is relatively costly；
4th, with the raising for increasing and requiring chip size diminution of chip pin number, with substrate during flip-chip
Aligning accuracy requires very high；
5th, all employ underfill in most of upside-down mounting product, its effect be alleviate between chip and substrate by
Thermal coefficient of expansion（CTE）The caused shear stress of difference, but there is a problem of that filling is discontented, empty；
6th, chip and substrate FC are welded, and there is multiple material, and the CTE between each material differs, in easily causing encapsulation process
Warpage issues.
Utility model content
Technical problem to be solved in the utility model is to provide a kind of superchip weight cloth for above-mentioned prior art
Wire encapsulation construction, it first makes salient point on metal support plate surface, thinning after pressure insulant, exposes required salient point, then mounts
Chip makes it be connected with salient point one end, to removing support plate after chip pressure insulant, by weight cloth after exposing the salient point other end
Wiring technology is connected with outer pin, so as to realize that high performance electric connection and good reliability ensure, forms high density weight cloth
Line packaging technology.
The technical scheme in the invention for solving the above technical problem is：A kind of superchip reroutes encapsulation knot
Structure, it includes metallic circuit layer, and the metallic circuit layer front is provided with salient point, chip, the core are pasted with the salient point
The pad of piece is connected with salient point, and the salient point and chip periphery are filled with insulant, and the metallic circuit layer back side is provided with
Pin connection layer, the metallic circuit layer and pin connection layer periphery are filled with insulant, the pin connection layer back side dew
Go out insulant, the pin connection layer exposes the plant ball region of insulant and is provided with metal ball.
Compared with prior art, the utility model has the advantage of：
1st, this utility model adopts the direct pasting chip again after electroplating bumps on common support plate, it is not necessary to customize lead
Framework or substrate, and loading in mixture for multi-chip can be as needed carried out, reduce manufacturing cost；
2nd, this utility model directly makes chip PAD be connected with circuit is rerouted by the way of support plate electroplating bumps, realizes
Secondary wiring on chip makes the process of salient point, greatly reduces making salient point cost on early stage chip, improves production effect
Rate；
3rd, assembling mode of the present utility model does not need the upside-down mounting of chip and the later bottom of upside-down mounting to fill out operation, it is to avoid therefore
The upside-down mounting para-position of generation and bottom are filled a vacancy the risk in hole；
4th, the insulant that this utility model is used is single, and the CTE differential between material is little, and warpage is little, package reliability
Grade is high.
Description of the drawings
Fig. 1 ~ Figure 14 is each operation stream of the manufacture method that a kind of superchip of this utility model reroutes encapsulating structure
Cheng Tu.
Figure 15 is the schematic diagram that a kind of superchip of this utility model reroutes encapsulating structure.
Wherein：
Salient point 1
Chip 2
Insulant 3
Metallic circuit layer 4
Pin connection layer 5
Metal ball 6.
Specific embodiment
This utility model is described in further detail below in conjunction with accompanying drawing embodiment.
As shown in figure 15, a kind of superchip in the present embodiment reroutes encapsulating structure, and it includes metallic circuit layer
4, the front of metallic circuit layer 4 is provided with salient point 1, and chip 2, the pad and salient point of the chip 2 are pasted with the salient point 1
It is connected, the salient point 1 and the periphery of chip 2 are filled with insulant 3, and the back side of metallic circuit layer 4 is provided with pin connection
Layer 5, the metallic circuit layer 4 and the periphery of pin connection layer 5 are filled with insulant 3, and the back side of pin connection layer 5 is exposed absolutely
Edge material 3, the pin connection layer 5 exposes the plant ball region of insulant 3 and is provided with metal ball 6.
Its manufacture method is as follows：
Step one, take a metal support plate；
Referring to Fig. 1, the suitable metal support plate of a piece of thickness is taken, the material of metal support plate can be according to the function of chip and spy
Property enters line translation, for example：Copper material, iron material, ferronickel material or zinc-iron material etc.；
Step 2, metal support plate surface preplating copper material；
Referring to Fig. 2, in one layer of copper material of metal support plate electroplating surface, it is therefore an objective to make basis for follow-up plating, the plating
Mode can be using chemical plating or electrolysis plating；
Step 3, formation salient point
It is convex needed for the metal support plate surface for completing preplating copper material is formed by the method such as plating or etching referring to Fig. 3
Point；
Step 4, salient point periphery fill insulant
Referring to Fig. 4, using techniques such as press mold, encapsulating, printings in salient point periphery fill insulant, by the technique such as thinning
Salient point is set to expose insulant；
Step 5, pasting chip
Referring to Fig. 5, chip attachment is made on the salient point for exposing by upside-down mounting, and make chip pad be connected with salient point；
Step 6, chip periphery fill insulant
Referring to Fig. 6, using the techniques such as press mold, encapsulating, printing fill insulant between the chips, chip is formed and is protected
Shield；
Step 7, removal metal support plate
Referring to Fig. 7, metal support plate is removed by modes such as etching, peeling；
Step 8, formation metal conducting layer
Referring to Fig. 8, led by one layer of thin metal of formation of electroless copper plating on the insulant surface for removing metal support plate
Electric layer；
Step 9, plating metallic circuit layer
Referring to Fig. 9, metallic circuit layer is formed by plating in metallic conduction layer surface；
Step 10, plating pin connection layer
Referring to Figure 10, pin connection layer is formed by plating in metallic circuit layer surface；
Step 11, fast-etching
Referring to Figure 11, the metal conducting layer outside metallic circuit layer and pin connection layer is removed；
Step 12, metallic circuit layer and pin connection layer periphery fill insulant
Referring to Figure 12, using techniques such as press mold, encapsulating, printings in metallic circuit layer and the filling insulation of pin connection layer periphery
Material, makes pin connection layer expose insulant by the technique such as thinning；
Step 13, plant ball
Referring to Figure 13, in the plant ball region implanted metal ball that pin connection layer exposes；
Step 14, cutting
Referring to Figure 14, the semi-finished product for having planted metal ball are cut into into single product；
The step 8 to step 12 can step 7 between step 13 repeatedly, to form multiple layer metal
Line layer.
The plant ball of the step 13 can adopt other surfaces processing mode（Such as NiAu, PPF, OSP）Substitute.
In addition to the implementation, this utility model also includes other embodiment, all employing equivalents or equivalent
The technical scheme that substitute mode is formed, all should fall within this utility model scope of the claims.
Claims (1)
1. a kind of superchip reroutes encapsulating structure, it is characterised in that：It includes metallic circuit layer（4）, the metal wire
Road floor（4）Front is provided with salient point（1）, the salient point（1）On be pasted with chip（2）, the chip（2）Pad and salient point phase
Connection, the salient point（1）And chip（2）Periphery is filled with insulant（3）, the metallic circuit layer（4）The back side is provided with draws
Foot line layer（5）, the metallic circuit layer（4）With pin connection layer（5）Periphery is filled with insulant（3）, the lead-foot-line
Road floor（5）Expose insulant in the back side（3）, the pin connection layer（5）Expose insulant（3）Plant ball region be provided with gold
Category ball（6）.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201621112557.5U CN206179856U (en) | 2016-10-11 | 2016-10-11 | Superchip packaging structure that reroutes |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201621112557.5U CN206179856U (en) | 2016-10-11 | 2016-10-11 | Superchip packaging structure that reroutes |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN206179856U true CN206179856U (en) | 2017-05-17 |
Family
ID=58677379
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201621112557.5U Active CN206179856U (en) | 2016-10-11 | 2016-10-11 | Superchip packaging structure that reroutes |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN206179856U (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN106373931A (en) * | 2016-10-11 | 2017-02-01 | 江阴芯智联电子科技有限公司 | High-density chip re-wiring package structure and fabrication method thereof |
-
2016
- 2016-10-11 CN CN201621112557.5U patent/CN206179856U/en active Active
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN106373931A (en) * | 2016-10-11 | 2017-02-01 | 江阴芯智联电子科技有限公司 | High-density chip re-wiring package structure and fabrication method thereof |
| CN106373931B (en) * | 2016-10-11 | 2019-05-17 | 江阴芯智联电子科技有限公司 | A kind of superchip reroutes encapsulating structure and preparation method thereof |
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| GR01 | Patent grant | ||
| GR01 | Patent grant |