CN206117598U - "Frequency" adjustable clock generation circuit - Google Patents
"Frequency" adjustable clock generation circuit Download PDFInfo
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- CN206117598U CN206117598U CN201621009690.8U CN201621009690U CN206117598U CN 206117598 U CN206117598 U CN 206117598U CN 201621009690 U CN201621009690 U CN 201621009690U CN 206117598 U CN206117598 U CN 206117598U
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Abstract
The utility model discloses a "Frequency" adjustable clock generation circuit, including the following device that connects gradually: band gap reference circuit, digital analog converter, voltage controlled oscillator and signal shaping circuit, wherein, the invariable reference voltage of output of band gap reference circuit, digital analog converter receive the default with invariable reference voltage, and analog output voltage VR, this default is voltage setting value or frequency setting value, voltage controlled oscillator receives analog voltage VR to output sawtooth voltage V1, signal shaping circuit receives sawtooth voltage V1 to the clock signal CLK of output duty cycle 50%. It is inaccurate that this "Frequency" adjustable clock generation circuit has overcome the "Frequency" among the prior art, is difficult to linearity control "Frequency"'s problem, can obtain more stable clock signal output.
Description
Technical Field
The utility model relates to a high performance analog integrated circuit design technique specifically relates to oscillation frequency adjustable clock produces circuit.
Background
Various electronic circuits often need to support various small waveform signals during normal operation, including: sine waves, rectangular waves, triangular waves, sawtooth waves, and the like. These signals may be provided by waveform generation and conversion circuitry. A waveform generating circuit, also called an oscillator or a waveform generator, is a circuit that generates a signal having a certain frequency, a certain amplitude, and a certain waveform without an external excitation signal.
Resistance-capacitance (RC) oscillators typically operate at relatively low frequencies and are often used in low frequency electronic devices. The RC oscillator has the characteristics of simple circuit, easiness in starting oscillation, easiness in adjusting oscillation frequency and the like, and is adopted by most low-frequency oscillation circuits.
In a conventional RC oscillator, as shown in fig. 1, a resistor R, a capacitor C and an inverter form a charge-discharge network, and the oscillation frequency of the conventional RC oscillator is mainly determined by the product of RC parameters. In an actual circuit, in order to improve the accuracy of the oscillation frequency, an external resistor and capacitor with high accuracy and temperature compensation characteristics are often used. The inversion level of the inverter is closely related to the threshold value, the aspect ratio, the power supply voltage, the ambient temperature, and the like of the transistor. Therefore, due to the accuracy of the RC parameter and the influence of the inverter flip level, the oscillator cannot obtain a more accurate oscillation frequency, and it is difficult to adjust the oscillation frequency linearly.
SUMMERY OF THE UTILITY MODEL
The utility model aims at providing an oscillation frequency adjustable clock generation circuit, this oscillation frequency adjustable clock generation circuit have overcome the oscillation frequency among the prior art inaccurate, are difficult to linear adjustment oscillation frequency's problem, can obtain more stable clock signal output.
In order to achieve the above object, the present invention provides an oscillation frequency adjustable clock generation circuit, which includes the following devices connected in sequence: the band-gap reference circuit, the digital-to-analog converter, the voltage-controlled oscillator and the signal shaping circuit; wherein,
the output end of the band-gap reference circuit outputs a constant reference voltage, the digital-to-analog converter receives a preset value and the constant reference voltage and outputs an analog voltage VR, and the preset value is a voltage set value or a frequency set value;
the voltage-controlled oscillator receives the analog voltage VR and outputs a sawtooth wave voltage V1;
the signal shaping circuit receives the sawtooth wave voltage V1 and outputs a clock signal CLK with a duty cycle of 50%.
Preferably, the digital-to-analog conversion circuit includes: the circuit comprises a resistor string, a switch group and a decoder; wherein,
one end of the resistor string is connected to the band-gap reference circuit, and the other end of the resistor string is grounded; the input end of the switch group is connected between two adjacent resistors in the resistor string, and the output end of the switch group is connected with the input end of the voltage-controlled oscillator;
and the preset voltage and frequency are output to the input end of the decoder, and the output end of the decoder is output to the control end of the switch group so as to control the opening or closing of any switch in the switch group.
Further preferably, the digital-to-analog conversion circuit further includes: and one end of the filter capacitor C2 is connected to the output end of the switch group, and the other end of the filter capacitor C2 is grounded.
Further preferably, the voltage controlled oscillator includes:
a charge-discharge path, a voltage comparator and a NOT circuit; wherein,
the output end of the charge and discharge path is connected to the first input end of the voltage comparator, and the output end of the switch group is connected to the second input end of the voltage comparator;
the output end of the voltage comparator is connected to the input end of the NOT gate circuit, and the output end of the NOT gate circuit is connected to the signal shaping circuit.
Still further preferably, the voltage controlled oscillator further includes:
and one end of the capacitor C1 is connected to the output end of the charge and discharge circuit, and the other end of the capacitor C1 is grounded.
Further preferably, the charge and discharge path includes: the current reference, the first transistor and the second transistor, the drain of the first transistor is connected to the current reference, the source of the first transistor is connected to the drain of the second transistor, the source of the second transistor is grounded, and the gate of the first transistor and the gate of the second transistor are both connected to the output end of the NOT gate circuit; and the source electrode of the first transistor is the output end of the charge and discharge path.
Still further preferably, the signal shaping circuit includes: and the D trigger forms a frequency division circuit, and the clock signal input end of the D trigger is connected to the output end of the NOT circuit.
Through the above embodiment, the present invention can obtain more stable clock signal output, the frequency of which is mainly determined by the capacitance values of the reference current IREF, the reference voltage VR and the capacitor C1, and the correlation between the reference current IREF, the reference voltage VR and the temperature is smaller, so that more accurate clock frequency output can be obtained. The adjustable reference voltage VR is generated through the digital-to-analog converter, the oscillation frequency of the voltage-controlled oscillator can be changed, and the requirements of different systems on clock frequency are met.
Other features and advantages of the present invention will be described in detail in the detailed description which follows.
Drawings
The accompanying drawings, which are included to provide a further understanding of the invention and are incorporated in and constitute a part of this specification, illustrate embodiments of the invention and together with the description serve to explain the principles of the invention and not to limit the invention. In the drawings:
FIG. 1 is a prior art RC oscillator circuit diagram;
fig. 2 is a block diagram illustrating a clock generation circuit with adjustable oscillation frequency according to the present invention;
fig. 3 is a circuit diagram illustrating a clock generation circuit with adjustable oscillation frequency according to the present invention; and
fig. 4 is a signal waveform diagram illustrating a portion of an emulated signal waveform of a circuit of the present invention.
Detailed Description
The following detailed description of the embodiments of the present invention will be made with reference to the accompanying drawings. It is to be understood that the description of the embodiments herein is for purposes of illustration and explanation only and is not intended to limit the invention.
The utility model provides a clock generation circuit with adjustable oscillation frequency, as shown in FIG. 2, this clock generation circuit with adjustable oscillation frequency includes the following devices that connect gradually: the band-gap reference circuit, the digital-to-analog converter, the voltage-controlled oscillator and the signal shaping circuit; wherein,
the output end of the band-gap reference circuit outputs a constant reference voltage, the digital-to-analog converter receives a preset value and the constant reference voltage and outputs an analog voltage VR, and the preset value is a voltage set value or a frequency set value;
the voltage-controlled oscillator receives the analog voltage VR and outputs a sawtooth wave voltage V1;
the signal shaping circuit receives the sawtooth wave voltage V1 and outputs a clock signal CLK with a duty cycle of 50%.
In the utility model, the band gap reference circuit generates a reference voltage of 1.2V which is irrelevant to the power voltage and the temperature and provides the reference voltage for the digital-to-analog converter; generating a corresponding analog voltage VR by a digital-to-analog converter through preset voltage and frequency; the basic principle of the voltage-controlled oscillator is a charging and discharging circuit of a capacitor, and the charging voltage amplitude is determined by an input analog voltage VR: the higher the voltage of the analog voltage VR, the longer the charging time, and the lower the final clock frequency, whereas the lower the voltage of the analog voltage VR, the shorter the charging time, and the higher the final clock frequency. The sawtooth wave voltage V1 output by the voltage-controlled oscillator is sawtooth wave, and forms a clock signal output CLK with a duty ratio of 50% after signal shaping.
In the above way, the bandgap reference circuit generates a reference voltage independent of the power supply voltage and temperature, and outputs an adjustable reference voltage VR as the maximum charging voltage across the charging and discharging capacitor by changing the digital input of the 8-bit or 10-bit digital-to-analog converter. By controlling the amplitude of the charging voltage at the two ends of the capacitor C1, the clock output with adjustable frequency can be generated, and the output frequency and the input setting have a better linear relation, thereby meeting the requirement of a practical circuit system on high-precision clock signals.
In a specific embodiment of the present invention, the digital-to-analog conversion circuit may include: the circuit comprises a resistor string, a switch group and a decoder; wherein,
one end of the resistor string is connected to the band-gap reference circuit, and the other end of the resistor string is grounded; the input end of the switch group is connected between two adjacent resistors in the resistor string, and the output end of the switch group is connected with the input end of the voltage-controlled oscillator;
the preset voltage or frequency setting value is connected to the input end of the decoder, and the output end of the decoder is output to the control end of the switch group so as to control the opening or closing of any switch in the switch group.
An implementation of the present invention is shown in fig. 3. Wherein the bandgap reference generates a reference voltage VREF of 1.2V. The resistors R1 and R2 … … RN are a resistor string, and form a voltage selection circuit with the switch groups K1, K2, … … and K256. Decoder I5 converts the input 8-bit digital code into 256 switch control signals. The resistor string, the switch group and the decoder form a digital-to-analog converter to generate an adjustable reference voltage output VR.
To reduce the effect of circuit noise, VR filters the noise through capacitor C2. In this embodiment, the digital-to-analog conversion circuit may further include: and one end of the filter capacitor C2 is connected to the output end of the switch group, and the other end of the filter capacitor C2 is grounded.
In this embodiment, the voltage controlled oscillator may include:
a charge and discharge path, a voltage comparator COMP and a NOT gate circuit INV; wherein,
the output end of the charge and discharge path is connected to the first input end of the voltage comparator COMP, and the output end of the switch group is connected to the second input end of the voltage comparator COMP;
the output end of the voltage comparator COMP is connected to the input end of the inverter circuit INV, and the output end of the inverter circuit INV is connected to the signal shaping circuit.
In this embodiment, the voltage controlled oscillator may further include:
and one end of the capacitor C1 is connected to the output end of the charge and discharge circuit, and the other end of the capacitor C1 is grounded.
In this embodiment, the charge and discharge path may include: a current reference IREF, a first transistor M1 and a second transistor M2, wherein the drain of the first transistor M1 is connected to the current reference, the source of the first transistor M1 is connected to the drain of the second transistor M2, the source of the second transistor M2 is grounded, and the gate of the first transistor M1 and the gate of the second transistor M2 are both connected to the output terminal of the NOT gate circuit; the source electrode of the first transistor M1 is the output end of the charge and discharge path.
The current reference IREF is a constant independent of the supply voltage and temperature, when the second transistor M2 forms the discharge path of the capacitor C1. The reference voltage VR is connected to the positive input end of the voltage comparator COMP; one end of the capacitor C1 is connected to the negative input terminal of the voltage comparator COMP. When the terminal voltage VC of the capacitor C1 is lower than the reference voltage VR (voltage output by the digital-to-analog conversion circuit), the output VP of the voltage comparator COMP is at a high level, and the output voltage V1 is at a low level through the inverter INV, and at this time, when the first transistor M1 is turned on and the second transistor M2 is turned off, the current reference IREF charges the capacitor C1. When the terminal voltage of the capacitor C1 exceeds the reference voltage VR, the voltage comparator COMP is inverted, the output VP becomes low, the output voltage V1 of the inverter INV is high, and at this time, the transistor M1 is turned off and the transistor M2 is turned on, so as to discharge the capacitor C1.
In such an embodiment, the signal shaping circuit may include: and the D trigger forms a frequency division circuit, and the clock signal input end of the D trigger is connected to the output end of the NOT circuit INV.
Since the charging speed of the capacitor C1 is determined by the current reference IREF and the discharging speed is determined by the equivalent resistance of the transistor M2, the terminal voltage VC of the capacitor C1 is a sawtooth wave during normal operation of the circuit. The output voltage V1 of the inverter INV is a square wave with a small duty cycle, and is also the output of the voltage-controlled oscillator. The signal shaping circuit is implemented by a D flip-flop. The D flip-flop is connected to form a two-frequency division circuit, and converts the input voltage V1 with small duty ratio into a clock output signal with 50% duty ratio, wherein the frequency of the clock output signal is half of the output frequency of the voltage-controlled oscillator.
Fig. 4 is a partial simulation signal waveform of the circuit of the present invention. It can be seen that the reference voltage VR determines the maximum value of the terminal voltage VC of the capacitor C1 and also determines the output frequency of the final clock signal CLK. The charging and discharging times of the capacitor C1 are different: the charging current is determined by IREF, and the discharging process is directly discharged to the ground by the transistor M2, and the terminal voltage VC shows a sawtooth wave change. The frequency of the sawtooth wave is mainly determined by the magnitude of the reference current IREF and the capacitance C1. The comparator speed and the discharge speed of transistor M2 are fast, and have less effect on the frequency of the sawtooth wave, so the clock frequency at the output CLK is stable.
The preferred embodiments of the present invention have been described in detail with reference to the accompanying drawings, however, the present invention is not limited to the details of the above embodiments, and the technical concept of the present invention can be within the scope of the present invention to perform various simple modifications to the technical solution of the present invention, and these simple modifications all belong to the protection scope of the present invention.
It should be noted that the various technical features described in the above embodiments can be combined in any suitable manner without contradiction, and in order to avoid unnecessary repetition, the present invention does not need to describe any combination of the features.
In addition, various embodiments of the present invention can be combined arbitrarily, and the disclosed content should be regarded as the present invention as long as it does not violate the idea of the present invention.
Claims (7)
1. A clock generation circuit with adjustable oscillation frequency is characterized by comprising the following devices which are connected in sequence: the band-gap reference circuit, the digital-to-analog converter, the voltage-controlled oscillator and the signal shaping circuit; wherein,
the output end of the band-gap reference circuit outputs a constant reference voltage, the digital-to-analog converter receives a preset value and the constant reference voltage and outputs an analog voltage VR, and the preset value is a voltage set value or a frequency set value;
the voltage-controlled oscillator receives the analog voltage VR and outputs a sawtooth wave voltage V1;
the signal shaping circuit receives the sawtooth wave voltage V1 and outputs a clock signal CLK with a duty cycle of 50%.
2. The adjustable oscillation frequency clock generation circuit according to claim 1, wherein the digital-to-analog conversion circuit comprises: the circuit comprises a resistor string, a switch group and a decoder; wherein,
one end of the resistor string is connected to the band-gap reference circuit, and the other end of the resistor string is grounded; the input end of the switch group is connected between two adjacent resistors in the resistor string, and the output end of the switch group is connected with the input end of the voltage-controlled oscillator;
and a preset voltage or frequency set value is accessed to the input end of the decoder, and the output end of the decoder is output to the control end of the switch group so as to control the opening or closing of any switch in the switch group.
3. The adjustable oscillation frequency clock generation circuit of claim 2, wherein the digital-to-analog conversion circuit further comprises: and one end of the filter capacitor C2 is connected to the output end of the switch group, and the other end of the filter capacitor C2 is grounded.
4. The adjustable oscillation frequency clock generation circuit according to claim 2, wherein the voltage-controlled oscillator comprises:
a charge-discharge path, a voltage comparator and a NOT circuit; wherein,
the output end of the charge and discharge path is connected to the first input end of the voltage comparator, and the output end of the switch group is connected to the second input end of the voltage comparator;
the output end of the voltage comparator is connected to the input end of the NOT gate circuit, and the output end of the NOT gate circuit is connected to the signal shaping circuit.
5. The adjustable oscillation frequency clock generation circuit of claim 4, wherein the voltage controlled oscillator further comprises:
and one end of the capacitor C1 is connected to the output end of the charge and discharge circuit, and the other end of the capacitor C1 is grounded.
6. The adjustable oscillation frequency clock generation circuit of claim 4, wherein the charge and discharge path comprises: the current reference, the first transistor and the second transistor, the drain of the first transistor is connected to the current reference, the source of the first transistor is connected to the drain of the second transistor, the source of the second transistor is grounded, and the gate of the first transistor and the gate of the second transistor are both connected to the output end of the NOT gate circuit; and the source electrode of the first transistor is the output end of the charge and discharge path.
7. The adjustable oscillation frequency clock generation circuit according to claim 4, wherein the signal shaping circuit comprises: and the D trigger forms a frequency division circuit, and the clock signal input end of the D trigger is connected to the output end of the NOT circuit.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201621009690.8U CN206117598U (en) | 2016-08-31 | 2016-08-31 | "Frequency" adjustable clock generation circuit |
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| Application Number | Priority Date | Filing Date | Title |
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| CN201621009690.8U CN206117598U (en) | 2016-08-31 | 2016-08-31 | "Frequency" adjustable clock generation circuit |
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| CN206117598U true CN206117598U (en) | 2017-04-19 |
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| CN201621009690.8U Withdrawn - After Issue CN206117598U (en) | 2016-08-31 | 2016-08-31 | "Frequency" adjustable clock generation circuit |
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Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN106230385A (en) * | 2016-08-31 | 2016-12-14 | 黄继颇 | The adjustable clock generation circuit of frequency of oscillation |
| CN107134979A (en) * | 2017-04-21 | 2017-09-05 | 四川和芯微电子股份有限公司 | RC oscillators |
| CN113572429A (en) * | 2021-08-13 | 2021-10-29 | 成都爱旗科技有限公司 | Class F voltage-controlled oscillation circuit and temperature compensation method thereof |
-
2016
- 2016-08-31 CN CN201621009690.8U patent/CN206117598U/en not_active Withdrawn - After Issue
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN106230385A (en) * | 2016-08-31 | 2016-12-14 | 黄继颇 | The adjustable clock generation circuit of frequency of oscillation |
| CN106230385B (en) * | 2016-08-31 | 2023-03-28 | 安徽赛腾微电子有限公司 | Clock generation circuit with adjustable oscillation frequency |
| CN107134979A (en) * | 2017-04-21 | 2017-09-05 | 四川和芯微电子股份有限公司 | RC oscillators |
| CN107134979B (en) * | 2017-04-21 | 2020-06-16 | 四川和芯微电子股份有限公司 | RC oscillator |
| CN113572429A (en) * | 2021-08-13 | 2021-10-29 | 成都爱旗科技有限公司 | Class F voltage-controlled oscillation circuit and temperature compensation method thereof |
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| TR01 | Transfer of patent right |
Effective date of registration: 20190110 Address after: Room 1401, 1402 and 1403 on the north side of 14th floor of No. 4 Building of Service Outsourcing Industrial Park, Yijiang District, Wuhu City, Anhui Province Patentee after: ANHUI SAITENG MICROELECTRONICS Co.,Ltd. Address before: 241000 Outsourcing Industrial Park, No. 717 Zhongshan South Road, Wuhu High-tech Zone, Anhui Province, 4 1401-1403 Patentee before: Huang Jipo |
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Granted publication date: 20170419 Effective date of abandoning: 20230328 |
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| AV01 | Patent right actively abandoned |
Granted publication date: 20170419 Effective date of abandoning: 20230328 |