CN205540751U - Write -protect circuit and NAND FLASH memory of NANDFLASH memory - Google Patents

Abstract

The utility model provides a write -protect circuit and NAND FLASH memory of NANDFLASH memory relates to the circuit field. The utility model provides a write -protect circuit connection of NANDFLASH memory is between NAND FLASH memory chip and host computer, and the write -protect circuit includes: link to each other with host computer and NAND FLASH memory chip, be controlled by the host computer, hold the output low level to get into the the control unit of write -protect state with control NAND FLASH memory chip to the write -protect of NAND FLASH memory chip. Through connecting the control unit between host computer and NAND FLASH memory chip, its write -protect end output low level to NAND FLASH memory chip of PC control carries out the write -protect with control NAND FLASH memory chip, and then make NAND FLASH memory avoided because user's maloperation or storage file procedural appear the leak result in NAND FLASH memory in the file phenomenon of losing, NAND FLASH memory has further been solved because factory's maintenance need be returned in losing of file, lead to maintaining the problem of the cost -push of NAND FLASH memory.

Description

A write protection circuit of NAND FLASH memory and NAND FLASH memory

technical field

The utility model belongs to the field of circuits, in particular to a write protection circuit of a NAND FLASH memory and the NAND FLASH memory.

Background technique

Nowadays, NAND FLASH memory (flash memory) has been widely used in various entertainment devices. Although in the prior art, before rewriting the files in the NAND FLASH memory, the staff needs to erase or empty the NAND FLASH memory, but Because the files in the NAND FLASH memory are usually lost due to user misoperation or program loopholes in the stored files, the files in the NAND FLASH memory will be lost, and the device or system to which the NAND FLASH memory belongs will not work properly. For example, when the files in the NAND FLASH memory of the entertainment system components on the aircraft are lost, the entertainment system components will not work, and other associated components may not work properly. And in the prior art, when the files in the NAND FLASH memory are damaged or lost, they must be returned to the factory for repair, and the files must be manually burned again, resulting in an increase in the cost of maintaining the NAND FLASH memory.

Utility model content

The purpose of the embodiment of the utility model is to provide a write protection circuit for NAND FLASH memory, aiming to solve the loss of NAND FLASH memory files in the prior art due to user misoperation or loopholes in the storage file program , it must be returned to the factory for maintenance, and the files must be re-programmed manually, resulting in an increase in the cost of maintaining the NAND FLASH memory.

The utility model embodiment is achieved like this, a kind of write protection circuit of NAND FLASH memory, is connected between NAND FLASH memory chip and host computer, and described write protection circuit comprises:

Connect with the host computer and the NAND FLASH memory chip, be controlled by the host computer, output a low level to the write protection terminal of the NAND FLASH memory chip to control the NAND FLASH memory chip to enter the write protection state control unit.

Optionally, the control unit includes: a controlled terminal and a signal output terminal;

The controlled terminal is connected to the host computer, the signal output terminal is connected to the write protection terminal of the NAND FLASH memory chip, and the host computer controls the control unit to send data to the NAND FLASH through the controlled terminal. The write protection terminal of the memory chip outputs a high or low level to control the NAND FLASH memory chip to enter a rewriting state or enter a write protection state.

Optionally, the control unit further includes: an analog switch SW1, a resistor R1 and a resistor R2;

The first end of the analog switch SW1 is the controlled end of the control unit and is connected to the host computer, the second end of the analog switch SW1 is connected to the first end of the resistor R1, and the first end of the resistor R1 is The two ends and the first end of the resistor R2 are jointly connected to the write protection end of the NAND FLASH memory chip, and the second end of the resistor R2 is grounded.

The embodiment of the utility model also provides a kind of NAND FLASH memory, comprises NAND FLASH memory chip, and described NAND FLASH memory also comprises a write protection circuit, and described write protection circuit is connected between described NAND FLASH memory chip and host computer room, including:

Connect with the host computer and the NAND FLASH memory chip, be controlled by the host computer, output a low level to the write protection terminal of the NAND FLASH memory chip to control the NAND FLASH memory chip to enter the write protection state control unit.

Optionally, the control unit includes: a controlled terminal and a signal output terminal;

The controlled terminal is connected to the host computer, the signal output terminal is connected to the write protection terminal of the NAND FLASH memory chip, and the host computer controls the control unit to send data to the NAND FLASH through the controlled terminal. The write protection terminal of the memory chip outputs a high or low level to control the NAND FLASH memory chip to enter a rewriting state or enter a write protection state.

Optionally, the control unit further includes: an analog switch SW1, a resistor R1 and a resistor R2;

The first end of the analog switch SW1 is the controlled end of the control unit and is connected to the host computer, the second end of the analog switch SW1 is connected to the first end of the resistor R1, and the first end of the resistor R1 is The two ends and the first end of the resistor R2 are jointly connected to the write protection end of the NAND FLASH memory chip, and the second end of the resistor R2 is grounded.

Optionally, the NAND FLASH memory also includes:

The filter unit is connected between the power supply and the ground to filter the output voltage of the power supply.

Optionally, the filter unit includes a capacitor C1, a capacitor C2, and a capacitor C3;

The first end of the capacitor C1 is connected to a power supply, the first end of the capacitor C1 is connected to the first end of the capacitor C2 and the first end of the capacitor C3 in turn, and the first end of the capacitor C3 is connected to the NAND FLASH memory The power supply terminal VCC of the chip, the second terminal of the capacitor C1 , the second terminal of the capacitor C2 and the second terminal of the capacitor C3 are commonly grounded.

The embodiment of the utility model provides a write protection circuit of NAND FLASH memory and NAND FLASH memory. By connecting the control unit between the host computer and the NAND FLASH memory, the host computer controls it to output low power to the write protection terminal of the NAND FLASH memory. Ping to control the NAND FLASH memory for write protection, so that the NAND FLASH memory avoids the loss of NAND FLASH memory files due to user misoperation or storage file program loopholes, and further solves the problem of NAND FLASH memory due to file loss It needs to be returned to the factory for repair, resulting in an increase in the cost of maintaining NAND FLASH memory.

Description of drawings

Fig. 1 is the structural block diagram of the write protection circuit of the NAND FLASH memory that the utility model embodiment provides;

Fig. 2 is the schematic circuit diagram of the write protection circuit of the NAND FLASH memory that the utility model embodiment provides;

Fig. 3 is the structural block diagram of the NAND FLASH memory that the utility model embodiment provides;

FIG. 4 is a schematic circuit diagram of the NAND FLASH memory provided by the embodiment of the present invention.

detailed description

In order to make the purpose, technical solution and advantages of the utility model clearer, the utility model will be further described in detail below in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described here are only used to explain the utility model, and are not intended to limit the utility model.

The purpose of the embodiment of the utility model is to provide a write protection circuit for NAND FLASH memory, aiming to solve the loss of NAND FLASH memory files in the prior art due to user misoperation or loopholes in the storage file program , it must be returned to the factory for maintenance, and the files must be re-programmed manually, resulting in an increase in the cost of maintaining the NAND FLASH memory.

FIG. 1 shows a structural block diagram of a write protection circuit of a NAND FLASH memory provided by an embodiment of the present invention.

As shown in FIG. 1 , a write protection circuit 100 for a NAND FLASH memory provided by this embodiment is connected between a NAND FLASH memory chip U1 and a host computer 200 .

The write protection circuit 100 of a kind of NAND FLASH memory provided by the present embodiment comprises: control unit 10, and control unit 10 is connected with host computer 200 and NAND FLASH memory chip U1, is controlled by host computer 200 to the writing of NAND FLASH memory chip U1 The protection terminal flash_wp outputs a low level to control the NAND FLASH memory chip U1 to enter the write protection state

FIG. 2 shows a schematic circuit diagram of the write protection circuit of the NAND FLASH memory provided by the embodiment of the present invention.

In this embodiment, the host computer 200 may be an existing single-chip microcomputer, which has built-in control instructions for controlling the control unit 10 in the write protection circuit 100 of the NAND FLASH memory. For example, in order to realize that the NAND FLASH memory chip U1 directly enters the write-protected state after being powered on, the host computer 200 sends an output to the control unit 10 and keeps a low level instruction, so that the control unit 10 when the NAND FLASH memory chip U1 is turned on, Output low level to the write protection terminal flash_wp of NAND FLASH memory chip U1, and keep low level continuously, and then make NAND FLASH memory chip U1 directly enter write protection state after being powered on, control unit 10 sends to NAND FLASH memory chip U1 Write protection end flash_wp output high level.

Optionally, the control unit 10 includes: a controlled terminal and a signal output terminal.

The controlled terminal is connected to the host computer 200, and the signal output terminal is connected to the write protection terminal flash_wp of the NAND FLASH memory chip U1, and the host computer 200 controls the control unit 10 to output high or high to the write protection terminal WP of the NAND FLASH memory chip U1 through the controlled terminal. Low level, to control the NAND FLASH memory chip U1 to enter the rewriting state or enter the write protection state.

As shown in FIG. 2 , specifically, the control unit 10 further includes: an analog switch SW1 , a resistor R1 and a resistor R2 .

The first end of the analog switch SW1 is the controlled end of the control unit 10 and is connected to the host computer 200 . The second terminal of the analog switch SW1 is connected to the first terminal of the resistor R1, the second terminal of the resistor R1 and the first terminal of the resistor R2 are jointly connected to the write protection terminal flash_wp of the NAND FLASH memory chip U1, and the second terminal of the resistor R2 is grounded.

In this embodiment, since the first end of the analog switch SW1 is the controlled end of the control unit 10 and is connected to the host computer 200, when the host computer 200 controls the controlled end of the control unit 10, the analog switch SW1 is closed, The host computer 200 outputs a high level to the write protection terminal flash_wp of the NAND FLASH memory chip U1 through the analog switch SW1 and the resistor R1, and controls the NAND FLASH memory chip U1 to enter the rewriting state. At this time, files or files can be written to the NAND FLASH memory chip U1 Erase files. When the host computer 200 controls the controlled end of the control unit 10 so that the analog switch SW1 is disconnected, since the second end of the resistor R2 is grounded, a low level is output to the write protection end flash_wp of the NAND FLASH memory chip U1, thereby controlling the NAND FLASH memory chip U1 It enters the write-protected state. At this time, it is impossible to write files to the NAND FLASH memory chip U1 or erase its internal files.

In this embodiment, the upper computer 200 can be an existing single-chip microcomputer or PC, and the upper computer 200 selects a single-chip microcomputer as an example. The pin is connected with the controlled end of the control unit 10 . The host computer 200 sends a control command to the control unit 10, so that the control unit 10 outputs a high or low level to the write protection terminal flash_wp of the NAND FLASH memory chip U1, so as to control the NAND FLASH memory chip U1 to enter the rewriting state or enter the write protection state. For example, the host computer 200 sends a control command to the control unit 10, so that the control unit 10 outputs a high level to the write protection terminal flash_wp of the NAND FLASH memory chip U1, so as to control the NAND FLASH memory chip U1 to enter the rewriting state. For another example, the host computer 200 sends a control command to the control unit 10, so that the control unit 10 outputs a low level to the write protection terminal flash_wp of the NAND FLASH memory chip U1, so as to control the NAND FLASH memory chip U1 to enter the write protection state.

The utility model embodiment provides a kind of write protection circuit 100 of NAND FLASH memory, comprises control unit 10, by connecting control unit 10 between host computer 200 and NAND FLASH memory chip U1, host computer 200 controls it to NAND FLASH memory chip U1 The write protection terminal flash_wp of the chip U1 outputs a low level to control the NAND FLASH memory chip U1 to perform write protection, so that the NAND FLASH memory avoids the loss of NAND FLASH memory files due to user misoperation or loopholes in the stored file program. This phenomenon further solves the problem that the NAND FLASH memory needs to be returned to the factory for repair due to the loss of files, resulting in an increase in the cost of maintaining the NAND FLASH memory.

Corresponding to the above embodiments, another object of the embodiments of the present invention is to provide a NAND FLASH memory 300 .

Fig. 3 shows a structural block diagram of the NAND FLASH memory provided by the embodiment of the present invention.

A kind of NAND FLASH memory, comprises NAND FLASH memory chip U1, described NAND FLASH memory 300 also comprises a write protection circuit 100, and described write protection circuit 100 is connected between described NAND FLASH memory chip U1 and host computer 200, comprises :

Connect with the host computer 200 and the NAND FLASH memory chip U1, be controlled by the host computer 200, output a low level to the write protection terminal flash_wp of the NAND FLASH memory chip U1 to control the NAND FLASH memory chip U1 enters the control unit in the write-protected state.

Since the specific implementation of the write protection circuit 100 of the NAND FLASH memory in this embodiment has been described in detail in the above embodiments, it will not be repeated here.

FIG. 4 shows a schematic circuit diagram of the NAND FLASH memory provided by the embodiment of the present invention.

As shown in Figure 4, the NAND FLASH memory 300 also includes:

The filtering unit 310 is connected between the power supply VCC3V3 and the ground, and filters the voltage output by the power supply. In this embodiment, the filter unit 310 is connected between the NAND FLASH memory 300 and the power supply VCC3V3, and is used for filtering the voltage output by the power supply VCC3V3.

As shown in FIG. 3 , the filter unit 310 may include a capacitor C1 , a capacitor C2 and a capacitor C3 .

The first terminal of capacitor C1 is connected to the power supply VCC3V3, the first terminal of capacitor C1 is connected to the first terminal of capacitor C2 and the first terminal of capacitor C3 in turn, the first terminal of capacitor C3 is connected to the power supply terminal VCC of NAND FLASH memory chip U1, and the second terminal of capacitor C1 terminal, the second terminal of the capacitor C2 and the second terminal of the capacitor C3 are commonly grounded.

In this embodiment, capacitor C1 , capacitor C2 and capacitor C3 are polarized capacitors, which are set at the power supply terminal VCC of the NAND FLASH memory chip U1 for filtering.

The embodiment of the utility model provides a write protection circuit of NAND FLASH memory and NAND FLASH memory, by connecting the control unit between the host computer and the NAND FLASH memory chip U1, the host computer controls its write protection to the NAND FLASH memory chip U1 The terminal flash_wp outputs a low level to control the NAND FLASH memory chip U1 for write protection, so that the NAND FLASH memory avoids the loss of NAND FLASH memory files due to user misoperation or program loopholes in stored files, and further solves the problem. NAND FLASH memory needs to be returned to the factory for repair due to the loss of files, resulting in an increase in the cost of maintaining NAND FLASH memory.

The above descriptions are only preferred embodiments of the present utility model, and are not intended to limit the present utility model. Any modifications, equivalent replacements and improvements made within the spirit and principles of the present utility model shall be included in this utility model. within the scope of protection of utility models.

Claims (8)

1. a kind of write protection circuit of NAND FLASH memory, is connected between NAND FLASH memory chip and upper computer, it is characterized in that, described write protection circuit comprises: Connect with the host computer and the NAND FLASH memory chip, be controlled by the host computer, output a low level to the write protection terminal of the NAND FLASH memory chip to control the NAND FLASH memory chip to enter the write protection state control unit. 2. the write protection circuit of NAND FLASH memory as claimed in claim 1, is characterized in that, described control unit comprises: controlled end and signal output end; The controlled terminal is connected to the host computer, the signal output terminal is connected to the write protection terminal of the NAND FLASH memory chip, and the host computer controls the control unit to send data to the NAND FLASH through the controlled terminal. The write protection terminal of the memory chip outputs a high or low level to control the NAND FLASH memory chip to enter a rewriting state or enter a write protection state. 3. the write protection circuit of NAND FLASH memory as claimed in claim 2 is characterized in that, described control unit also comprises: analog switch SW1, resistance R1 and resistance R2; The first end of the analog switch SW1 is the controlled end of the control unit and is connected to the host computer, the second end of the analog switch SW1 is connected to the first end of the resistor R1, and the first end of the resistor R1 is The two ends and the first end of the resistor R2 are jointly connected to the write protection end of the NAND FLASH memory chip, and the second end of the resistor R2 is grounded. 4. a kind of NAND FLASH memory, comprise NAND FLASH memory chip, it is characterized in that, described NAND FLASH memory also comprises a write protection circuit, and described write protection circuit is connected between described NAND FLASH memory chip and upper computer, comprises : Connect with the host computer and the NAND FLASH memory chip, be controlled by the host computer, output a low level to the write protection terminal of the NAND FLASH memory chip to control the NAND FLASH memory chip to enter the write protection state control unit. 5. NAND FLASH memory as claimed in claim 4, is characterized in that, described control unit comprises: controlled end and signal output end; The controlled terminal is connected to the host computer, the signal output terminal is connected to the write protection terminal of the NAND FLASH memory chip, and the host computer controls the control unit to send data to the NAND FLASH through the controlled terminal. The write protection terminal of the memory chip outputs a high or low level to control the NAND FLASH memory chip to enter a rewriting state or enter a write protection state. 6. NAND FLASH memory as claimed in claim 5, is characterized in that, described control unit also comprises: analog switch SW1, resistance R1 and resistance R2; The first end of the analog switch SW1 is the controlled end of the control unit and is connected to the host computer, the second end of the analog switch SW1 is connected to the first end of the resistor R1, and the first end of the resistor R1 is The two ends and the first end of the resistor R2 are jointly connected to the write protection end of the NAND FLASH memory chip, and the second end of the resistor R2 is grounded. 7. NAND FLASH memory as claimed in claim 6, is characterized in that, described NAND FLASH memory also comprises: The filter unit is connected between the power supply and the ground to filter the output voltage of the power supply. 8. NAND FLASH memory as claimed in claim 7, is characterized in that, described filtering unit comprises electric capacity C1, electric capacity C2 and electric capacity C3; The first end of the capacitor C1 is connected to a power supply, the first end of the capacitor C1 is connected to the first end of the capacitor C2 and the first end of the capacitor C3 in turn, and the first end of the capacitor C3 is connected to the NAND FLASH memory The power supply terminal VCC of the chip, the second terminal of the capacitor C1 , the second terminal of the capacitor C2 and the second terminal of the capacitor C3 are commonly grounded.