CN205028629U - A drive circuit , In -cell touch panel and display device for touch -sensitive screen - Google Patents
A drive circuit , In -cell touch panel and display device for touch -sensitive screen Download PDFInfo
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Abstract
The utility model discloses a drive circuit, in -cell touch panel and display device for touch -sensitive screen controls supply circuit through time schedule controller and at the clock signal that the output of the shift register of very first time duan xiangdi N+1 -n level to the N level in demonstration stage has first amplitude, controls supply circuit and export the clock signal who has the second amplitude to shift register at different levels at the second time quantum that shows the stage, so that the height of the scanning signal's of the shift register of N+1 -n level to N level output current potential than the output of other grade of shift register, even thereby can guarantee that these scanning signal can attenuate in the touch time section, but the current potential after the decay still can guarantee the N+1 level to N+n level shift register can the normal output, and then solved among the prior art because scanning signal attenuate the N+1 that leads to and walked to the short and display effect problem dark partially of production of the capable pixel's of N+n charge time in the touch time section.
Description
Technical Field
The utility model relates to a touch-control technical field indicates a drive circuit, embedded touch-sensitive screen and display device for touch-sensitive screen especially.
Background
With the rapid development of display technology, displays have developed a trend of high integration and low cost. The GOA (gate driver array, array substrate line driver) technology integrates a TFT (thin film transistor) gate switch circuit on an array substrate of a display panel to form a scan driver for the display panel, so that a wiring space of a binding (Bonding) region and a Fan-out (Fan-out) region of a gate Integrated Circuit (IC) can be omitted, which not only can reduce product cost in two aspects of material cost and manufacturing process, but also can make the display panel achieve an aesthetic design of two-side symmetry and a narrow frame; moreover, the integration process can also omit the Bonding process in the direction of a grid scanning line, thereby improving the productivity and the yield.
Generally, a gate driving circuit is generally formed by a plurality of cascaded shift registers, and output signal terminals of each shift register correspond to one gate line respectively, and are used for outputting scanning signals to the plurality of gate lines sequentially row by row. With the higher resolution required by large-size displays, the gate driving circuit is often implemented by pre-charging, that is, each stage of shift register in the gate driving circuit outputs sequentially, and each clock signal has an overlap of 1/n pulse width in sequence, so that the scan signal output by the shift register of the current stage and the scan signal output by the shift register of the previous stage have an overlap of 1/n pulse width. Taking n as an example, as shown in fig. 1a, the gate driving circuit generally needs to connect 6 clock signal lines (CLK1, CLK2, CLK3, CLK4, CLK5, and CLK6), and in the gate driving circuit, except for the shift registers of the next 3 stages (SR (M), SR (M-1), and SR (M-2) in fig. 1 a), the Output signal terminal Output _ M of each shift register SR (M) is connected to the Input signal terminal Input of the shift register SR (M +3) of the next 3 stages respectively; fig. 1b shows a timing diagram of the gate driving circuit, where fig. 1b only shows a timing sequence of the scan signal Output by the Output signal terminal Output of the first 8 stages of shift registers.
However, in the touch and display time-sharing driving display device, it is necessary to insert a plurality of touch time periods, where N is 3, and the shift register shown in fig. 1c is taken as an example, assuming that a touch time period is inserted after the nth stage shift register outputs the scan signal and before the N +1 th stage shift register starts to output the scan signal, in the touch time period, the Input signal of the Input signal terminal Input of the N +1, N +2, N +3 th stage shift register is already valid, the voltage of the corresponding pull-up node PU is already pulled up, but due to the existence of the leakage current, the voltage of the pull-up node PU is attenuated (Drop), so that after the touch time period ends, the switching transistor M3 of the N +1, N +2, N +3 th stage shift register is not opened enough, and thus when the clock signal terminal ck1 is at a high level, the scan signal Output by the Output signal terminal Output has an increased rise time due to insufficient charging capability of the switching crystal M3, and further, the charging time of the pixel units in the N +1 th, N +2 th, and N +3 th rows is shortened, and the image display effect corresponding to the pixel units in the three rows is dark.
SUMMERY OF THE UTILITY MODEL
In view of this, the embodiment of the present invention provides a driving circuit for a touch panel, an in-cell touch panel and a display device, so as to solve the problem in the prior art that the rise time of the scanning signal output by the N +1 th to N th shift registers is longer due to the attenuation of the scanning signal output by the N +1 th to N th shift registers in the touch time period, and further the charging time of the N +1 th, N +2, N +3 th row pixel units is shortened, and the corresponding image display effect is darker.
Therefore, the embodiment of the present invention provides a driving circuit for a touch screen, including a gate driving circuit composed of cascaded M-stage shift registers, and a power supply circuit for providing a clock signal to each shift register in the gate driving circuit; in the grid driving circuit, except for the shift registers from the (M + 1) -n th stage to the M th stage, the output signal end of each shift register is respectively connected with the input signal end of the next nth shift register, wherein n is a positive integer larger than 0 and smaller than M; the drive circuit further includes: a time schedule controller; wherein the timing controller is configured to:
in a touch time period, controlling the power supply circuit to output a clock signal with an amplitude value of 0 to each stage of the shift register; the touch control time period is a preset time period after the Nth-stage shift register outputs the scanning signal and before the (N + 1) th-stage shift register starts to output the scanning signal, and N is a positive integer which is larger than N and smaller than M;
in a display stage, controlling the power supply circuit to output clock signals with a first amplitude to the shift registers from the (N + 1) -N th stage to the Nth stage in a first time period, and controlling the power supply circuit to output clock signals with a second amplitude to the shift registers of all stages in a second time period; wherein,
the first time period is a time period for the shift registers of the (N +1-N) th to nth stages to output scanning signals, and the second time period is a time period other than the first time period in the display time period; the first amplitude of the clock signal is greater than the second amplitude.
Preferably, in the above driving circuit provided in an embodiment of the present invention, the timing controller is further configured to:
detecting the output condition of each stage of shift register in the grid drive circuit in a display time period;
and determining a time period in which the number of stages of the shift register outputting the scanning signal is in the range from the (N-1) -N th stage to the (N) th stage as a first time period, and determining a time period in which the number of stages of the shift register outputting the scanning signal is not in the range from the (N-1-N) -N th stage to the (N) th stage as a second time period.
Preferably, in the above driving circuit provided in an embodiment of the present invention, the timing controller specifically includes: the detection circuit and the control circuit are connected between the detection circuit and the power supply circuit; wherein,
the detection circuit is configured to: detecting the output condition of each stage of shift register in the gate drive circuit in a display stage, determining that the time period when the stage numbers of the shift register units of the output scanning signals are all in the range from N-1-N to N is a first time period, outputting a first control signal to the control circuit in the first time period, determining that the time period when the stage numbers of the shift register units of the output scanning signals are not in the range from N-1-N to N is a second time period, and outputting a second control signal to the control circuit in the second time period;
the control circuit is configured to: when a first control signal sent by the detection circuit is received, the power supply circuit is controlled to output clock signals with a first amplitude to the shift registers from the (N + 1) -N th stage to the Nth stage; and when a second control signal sent by the detection circuit is received, the power supply circuit is controlled to output a clock signal with a second amplitude to each shift register.
Preferably, in the above driving circuit provided in an embodiment of the present invention, the timing controller specifically includes: the power supply circuit comprises a detection circuit, a first control circuit connected between the detection circuit and the power supply circuit, and a second control circuit connected between the detection circuit and the power supply circuit;
the detection circuit is configured to: detecting the output condition of each stage of shift register in the gate drive circuit in a display stage, determining that the time period when the stage numbers of the shift register units of the output scanning signals are all in the range from N-1-N to N is a first time period, outputting control signals to the first control circuit in the first time period, determining that the time period when the stage numbers of the shift register units of the output scanning signals are not in the range from N-1-N to N is a second time period, and outputting control signals to the second control circuit in the second time period;
the first control circuit is configured to: when receiving a control signal sent by the detection circuit, controlling the power supply circuit to output a clock signal with a first amplitude to the shift registers from the (N + 1) -N th stage to the Nth stage;
the second control circuit is configured to: and when receiving the control signal sent by the detection circuit, controlling the power supply circuit to output a clock signal with a second amplitude to each stage of the shift register.
Preferably, in the above driving circuit provided in an embodiment of the present invention, the power supply circuit specifically includes: the power supply sub-circuit is connected with the time sequence controller, and the level conversion sub-circuit is connected between the power supply sub-circuit and each level of shift register; wherein,
the power supply sub-circuit is to: outputting a first high potential voltage and a low potential voltage to the level shift sub-circuit at the same time under the control of the timing controller in the first period; outputting a second high potential voltage and a low potential voltage to the level shift sub-circuit under the control of the timing controller in the second period; wherein the first high potential voltage is higher than the second high potential voltage;
the level shift subcircuit is configured to: when receiving a first high potential voltage and a low potential voltage provided by the power supply subcircuit, outputting a clock signal with a first amplitude to each stage of shift register; and when receiving the second high potential voltage and the low potential voltage provided by the power supply subcircuit, outputting a clock signal with a second amplitude to each stage of the shift register.
Preferably, in the above-mentioned driving circuit provided by the embodiment of the present invention, the first amplitude is equal to a difference between the first high potential voltage and the low potential voltage, and the second amplitude is equal to a difference between the second high potential voltage and the low potential voltage.
Preferably, in the driving circuit provided by the embodiment of the present invention, the timing controller is connected to the power supply circuit through an I2C interface.
Preferably, in the above-mentioned driving circuit provided by the embodiment of the present invention, the longer the touch time period is, the larger the difference between the first amplitude and the second amplitude is.
Correspondingly, the embodiment of the utility model provides an embedded touch-sensitive screen is still provided, include the embodiment of the utility model provides an arbitrary kind of drive circuit of above-mentioned.
Correspondingly, the embodiment of the utility model provides a display device is still provided, include the embodiment of the utility model provides an foretell embedded touch-sensitive screen.
The embodiment of the utility model provides an above-mentioned drive circuit, embedded touch-sensitive screen and display device for touch-sensitive screen, through time schedule controller control supply circuit to the shift register output of (N + 1) -N level to the Nth level in the first time quantum in the display stage have the clock signal of first amplitude, control supply circuit to the shift register output of each level in the second time quantum in the display stage have the clock signal of second amplitude; the potential of the scanning signals output by the N-th-level shift registers from the (N + 1) -N-th level to the nth level is higher than the potential of the scanning signals output by the shift registers of other levels, so that the situation that even if the scanning signals are attenuated in a touch time period can be ensured, the attenuated potentials can still ensure that the shift registers from the (N + 1) -th level to the (N + N) -th level can normally output, and the problem that in the prior art, due to the fact that the scanning signals are attenuated in the touch time period, the charging time of pixel units in the (N + 1) -th row to the (N + N) -th row is short, and the display effect is dark is solved.
Drawings
Fig. 1a is a schematic structural diagram of a conventional gate driving circuit;
FIG. 1b is a timing diagram of the gate driving circuit shown in FIG. 1 a;
FIG. 1c is a schematic diagram of a conventional shift register;
fig. 2 is a schematic structural diagram of a driving circuit for a touch screen according to an embodiment of the present invention;
fig. 3a and fig. 3b are schematic structural diagrams of a driving circuit provided in an embodiment of the present invention.
Detailed Description
Embodiments of a driving circuit for a touch panel, an embedded touch panel and a display device according to embodiments of the present invention are described in detail below with reference to the accompanying drawings.
The embodiment of the utility model provides a drive circuit for touch-sensitive screen, as shown in fig. 2, including the grid drive circuit 3 (not shown M level shift register in fig. 2) that comprises cascaded M level shift register, be used for providing clock signal's power supply circuit 2 to each shift register in grid drive circuit 3; specifically, the cascade relationship of the gate driving circuit 3 is as shown in fig. 1a (in fig. 1a, n is 3 as an example), except for the M +1-n th to M stages of shift registers (SR (M +1-n), …, SR (M)), an Output signal terminal Output _ M of each stage of shift register SR (M) is respectively connected to an Input signal terminal Input of the next nth stage of shift register SR (M + n), where n is a positive integer greater than 0 and less than M; the drive circuit further includes: a time schedule controller 1; wherein, the time schedule controller 1 is used for:
in the touch time period, controlling the power supply circuit 2 to output a clock signal with the amplitude of 0 to each level of shift register; the touch time period is a preset time period after the Nth-stage shift register SR (N) outputs the scanning signal and before the (N + 1) th-stage shift register starts to output the scanning signal, wherein N is a positive integer which is greater than N and less than M;
in the display stage, the power supply circuit 2 is controlled to output clock signals with first amplitude to the shift registers from the (N + 1) -N th stage to the Nth stage in a first time period, and the power supply circuit 2 is controlled to output clock signals with second amplitude to the shift registers of all stages in a second time period; wherein,
the first time period is the time period from the N +1-N stage to the Nth stage of the shift register to output the scanning signal, and the second time period is the time period except the first time period in the display time period; the first amplitude of the clock signal is greater than the second amplitude.
The embodiment of the utility model provides an above-mentioned drive circuit, through the clock signal that time schedule controller control supply circuit has first amplitude to the shift register output of (N + 1) -N level to the Nth level in the first time quantum in the display stage, control supply circuit to the shift register output of each level in the second time quantum in the display stage have the clock signal of second amplitude; the potential of the scanning signals output by the N-th-level shift registers from the (N + 1) -N-th level to the nth level is higher than the potential of the scanning signals output by the shift registers of other levels, so that the situation that even if the scanning signals are attenuated in a touch time period can be ensured, the attenuated potentials can still ensure that the shift registers from the (N + 1) -th level to the (N + N) -th level can normally output, and the problem that in the prior art, due to the fact that the scanning signals are attenuated in the touch time period, the charging time of pixel units in the (N + 1) -th row to the (N + N) -th row is short, and the display effect is dark is solved.
It should be noted that, in the above-mentioned driving circuit provided by the embodiment of the present invention, N may be any one or more positive integers greater than N and smaller than M, when N only takes 1 positive integer, it means that only one touch time period is inserted in the time period of one frame, and when N takes a plurality of positive integers, it means that a plurality of touch time periods are inserted in the time period of one frame.
Preferably, in the above-mentioned driving circuit provided by the embodiment of the present invention, the longer the touch time period is, the larger the difference between the first amplitude and the second amplitude is. This is because the longer the touch time period is, the greater the attenuation degree of the scanning signal after the touch time period is, and thus, to ensure that the potential of the attenuated scanning signal meets the requirement of the node voltage, the difference between the first amplitude and the second amplitude is large.
Preferably, in the above driving circuit provided in the embodiments of the present invention, the timing controller is further configured to:
detecting the output condition of each stage of shift register in the grid drive circuit in a display time period;
and determining a time period in which the number of stages of the shift register outputting the scanning signal is in the range from the (N-1) -N th stage to the (N) th stage as a first time period, and determining a time period in which the number of stages of the shift register outputting the scanning signal is not in the range from the (N-1-N) -N th stage to the (N) th stage as a second time period.
The following describes a specific implementation of a driving circuit according to an embodiment of the present invention in detail with reference to the accompanying drawings.
Preferably, in the driving circuit provided in the embodiment of the present invention, as shown in fig. 3a, the timing controller 1 specifically includes: a detection circuit 11, a control circuit 12 connected between the detection circuit 11 and the power supply circuit 2; wherein,
the detection circuit 11 is configured to: detecting the output condition of each stage of shift register in the gate drive circuit 3 at a display stage, determining that the time periods when the stages of the shift register units of the output scanning signals are all in the range from N-1-N to N are first time periods, outputting a first control signal to the control circuit 12 in the first time periods, determining that the time periods when the stages of the shift register units of the output scanning signals are not in the range from N-1-N to N are second time periods, and outputting a second control signal to the control circuit 12 in the second time periods;
the control circuit 12 is configured to: when receiving a first control signal sent by the detection circuit 11, controlling the power supply circuit 2 to output a clock signal with a first amplitude to the shift registers of the (N + 1) -nth stage to the nth stage; when receiving the second control signal sent by the detection circuit 11, the control power supply circuit 2 outputs a clock signal with a second amplitude to each stage of the shift register.
Alternatively, preferably, in the driving circuit provided in the embodiment of the present invention, as shown in fig. 3b, the timing controller 1 specifically includes: a detection circuit 11, a first control circuit 13 connected between the detection circuit 11 and the power supply circuit 2, and a second control circuit 14 connected between the detection circuit 11 and the power supply circuit 2; wherein,
the detection circuit 11 is configured to: detecting the output condition of each stage of shift register in the gate drive circuit 3 at the display stage, determining that the time periods when the stages of the shift register units of the output scanning signals are all in the range from N-1-N to N are first time periods, outputting control signals to the first control circuit 13 in the first time periods, determining that the time periods when the stages of the shift register units of the output scanning signals are not in the range from N-1-N to N are second time periods, and outputting control signals to the second control circuit 14 in the second time periods;
the first control circuit 13 is configured to: when receiving the control signal sent by the detection circuit 11, controlling the power supply circuit 2 to output a clock signal with a first amplitude to the shift registers of the (N + 1) -N th stage to the nth stage;
the second control circuit 14 is configured to: when receiving the control signal sent by the detection circuit 11, the control power supply circuit 2 outputs a clock signal having a second amplitude to each stage of the shift register.
The embodiment of the utility model provides an among the above-mentioned time schedule controller, detection circuitry, control circuit, first control circuit or second control circuit all can realize through the semiconductor circuit of entity.
Preferably, in the driving circuit provided in the embodiment of the present invention, as shown in fig. 3a and 3b, the power supply circuit 2 specifically includes: a power supply sub-circuit 21 connected to the timing controller 1, and a level shift sub-circuit 22 connected between the power supply sub-circuit 21 and each stage of the shift register; wherein,
the power supply sub-circuit 21 is configured to: in the first period, under the control of the timing controller 1, the first high potential voltage and the low potential voltage are simultaneously output to the level shift sub-circuit 22; in the second period, under the control of the timing controller 1, the second high potential voltage and the low potential voltage are simultaneously output to the level shift sub-circuit 22; wherein the first high potential voltage is higher than the second high potential voltage;
the level shift sub-circuit 22 is configured to: when receiving the first high potential voltage and the low potential voltage supplied from the power supply sub circuit 21, outputting a clock signal having a first amplitude to each stage of the shift register; when receiving the second high potential voltage and the low potential voltage supplied from the power supply sub circuit 21, the clock signal having the second amplitude is output to each stage of the shift register.
When the embodiment of the present invention provides an above-mentioned driving circuit, the first amplitude is equal to the difference between the first high potential voltage and the low potential voltage, and the second amplitude is equal to the difference between the second high potential voltage and the low potential voltage.
In specific implementation, in the driving circuit provided in the embodiment of the present invention, the power supply sub-circuit is generally a DC-DC converter, and of course, the power supply sub-circuit may also be other hardware capable of implementing the same function, and is not limited herein.
In a specific implementation, in the driving circuit provided in the embodiments of the present invention, the level shifting sub-circuit is generally a level shifter, and of course, the level shifting sub-circuit may also be other hardware capable of implementing the same function, and is not limited herein.
Preferably, in the driving device provided in the embodiment of the present invention, as shown in fig. 3a and 3b, the timing controller 1 is connected to the power supply circuit 2 through an I2C interface 4.
Based on same utility model the design, the embodiment of the utility model provides an embedded touch-sensitive screen is still provided, include the embodiment of the utility model provides an above-mentioned arbitrary drive circuit who is used for the touch-sensitive screen that is provided. Since the principle of solving the problem of the in-cell touch screen is similar to that of the driving circuit, the implementation of the in-cell touch screen can be referred to the implementation of the driving circuit, and repeated details are not repeated.
Based on same utility model the design, the embodiment of the utility model provides a still provide a display device, include the embodiment of the utility model provides an above-mentioned embedded touch-sensitive screen. The display device may be: any product or component with a display function, such as a mobile phone, a tablet computer, a television, a display, a notebook computer, a digital photo frame, a navigator and the like. The implementation of the display device can be referred to the embodiment of the in-cell touch screen, and repeated details are not repeated.
The embodiment of the utility model provides a drive circuit, embedded touch-sensitive screen and display device for touch-sensitive screen, through time schedule controller control supply circuit to the shift register output of (N + 1) -N level to the Nth level in the first time quantum of demonstration stage have the clock signal of first amplitude, control supply circuit to the shift register output of each level in the second time quantum of demonstration stage have the clock signal of second amplitude; the potential of the scanning signals output by the N-th-level shift registers from the (N + 1) -N-th level to the nth level is higher than the potential of the scanning signals output by the shift registers of other levels, so that the situation that even if the scanning signals are attenuated in a touch time period can be ensured, the attenuated potentials can still ensure that the shift registers from the (N + 1) -th level to the (N + N) -th level can normally output, and the problem that in the prior art, due to the fact that the scanning signals are attenuated in the touch time period, the charging time of pixel units in the (N + 1) -th row to the (N + N) -th row is short, and the display effect is dark is solved.
It will be apparent to those skilled in the art that various changes and modifications may be made without departing from the spirit and scope of the invention. Thus, if such modifications and variations of the present invention fall within the scope of the claims and their equivalents, the present invention is also intended to include such modifications and variations.
Claims (10)
1. A driving circuit for a touch screen comprises a grid driving circuit consisting of M cascaded shifting registers, and a power supply circuit for providing clock signals for each shifting register in the grid driving circuit; in the grid driving circuit, except for the shift registers from the (M + 1) -n th stage to the M th stage, the output signal end of each shift register is respectively connected with the input signal end of the next nth shift register, wherein n is a positive integer larger than 0 and smaller than M; characterized in that the drive circuit further comprises: a time schedule controller; wherein the timing controller is configured to:
in a touch time period, controlling the power supply circuit to output a clock signal with an amplitude value of 0 to each stage of the shift register; the touch control time period is a preset time period after the Nth-stage shift register outputs the scanning signal and before the (N + 1) th-stage shift register starts to output the scanning signal, and N is a positive integer which is larger than N and smaller than M;
in a display stage, controlling the power supply circuit to output clock signals with a first amplitude to the shift registers from the (N + 1) -N th stage to the Nth stage in a first time period, and controlling the power supply circuit to output clock signals with a second amplitude to the shift registers of all stages in a second time period; wherein,
the first time period is a time period for the shift registers of the (N +1-N) th to nth stages to output scanning signals, and the second time period is a time period other than the first time period in the display time period; the first amplitude of the clock signal is greater than the second amplitude.
2. The driving circuit of claim 1, wherein the timing controller is further configured to:
detecting the output condition of each stage of shift register in the grid drive circuit in a display time period;
and determining a time period in which the number of stages of the shift register outputting the scanning signal is in the range from the (N-1) -N th stage to the (N) th stage as a first time period, and determining a time period in which the number of stages of the shift register outputting the scanning signal is not in the range from the (N-1-N) -N th stage to the (N) th stage as a second time period.
3. The driving circuit according to claim 2, wherein the timing controller specifically includes: the detection circuit and the control circuit are connected between the detection circuit and the power supply circuit; wherein,
the detection circuit is configured to: detecting the output condition of each stage of shift register in the gate drive circuit in a display stage, determining that the time period when the stage numbers of the shift register units of the output scanning signals are all in the range from N-1-N to N is a first time period, outputting a first control signal to the control circuit in the first time period, determining that the time period when the stage numbers of the shift register units of the output scanning signals are not in the range from N-1-N to N is a second time period, and outputting a second control signal to the control circuit in the second time period;
the control circuit is configured to: when a first control signal sent by the detection circuit is received, the power supply circuit is controlled to output clock signals with a first amplitude to the shift registers from the (N + 1) -N th stage to the Nth stage; and when a second control signal sent by the detection circuit is received, the power supply circuit is controlled to output a clock signal with a second amplitude to each shift register.
4. The driving circuit according to claim 2, wherein the timing controller specifically includes: the power supply circuit comprises a detection circuit, a first control circuit connected between the detection circuit and the power supply circuit, and a second control circuit connected between the detection circuit and the power supply circuit; wherein,
the detection circuit is configured to: detecting the output condition of each stage of shift register in the gate drive circuit in a display stage, determining that the time period when the stage numbers of the shift register units of the output scanning signals are all in the range from N-1-N to N is a first time period, outputting control signals to the first control circuit in the first time period, determining that the time period when the stage numbers of the shift register units of the output scanning signals are not in the range from N-1-N to N is a second time period, and outputting control signals to the second control circuit in the second time period;
the first control circuit is configured to: when receiving a control signal sent by the detection circuit, controlling the power supply circuit to output a clock signal with a first amplitude to the shift registers from the (N + 1) -N th stage to the Nth stage;
the second control circuit is configured to: and when receiving the control signal sent by the detection circuit, controlling the power supply circuit to output a clock signal with a second amplitude to each stage of the shift register.
5. The driving circuit according to claim 1, wherein the power supply circuit specifically comprises: the power supply sub-circuit is connected with the time sequence controller, and the level conversion sub-circuit is connected between the power supply sub-circuit and each level of shift register; wherein,
the power supply sub-circuit is to: outputting a first high potential voltage and a low potential voltage to the level shift sub-circuit at the same time under the control of the timing controller in the first period; in the second time period, under the control of the time schedule controller, simultaneously outputting a second high potential voltage and a low potential voltage to the level conversion sub-circuit; wherein the first high potential voltage is higher than the second high potential voltage;
the level shift subcircuit is configured to: when receiving a first high potential voltage and a low potential voltage provided by the power supply subcircuit, outputting a clock signal with a first amplitude to each stage of shift register; and when receiving the second high potential voltage and the low potential voltage provided by the power supply subcircuit, outputting a clock signal with a second amplitude to each stage of the shift register.
6. The driver circuit according to claim 5, wherein the first magnitude is equal to a difference between the first high potential voltage and the low potential voltage, and the second magnitude is equal to a difference between the second high potential voltage and the low potential voltage.
7. The driving circuit of claim 5, wherein the timing controller is connected to the power supply circuit via an I2C interface.
8. The driving circuit according to any one of claims 1 to 4, wherein the longer the touch time period is, the larger the difference between the first amplitude and the second amplitude is.
9. An in-cell touch screen comprising the driving circuit according to any one of claims 1 to 8.
10. A display device comprising the in-cell touch screen of claim 9.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201520816081.2U CN205028629U (en) | 2015-10-20 | 2015-10-20 | A drive circuit , In -cell touch panel and display device for touch -sensitive screen |
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN105139798A (en) * | 2015-10-20 | 2015-12-09 | 京东方科技集团股份有限公司 | Driving circuit for touch screen, embedded touch screen and display device |
| JP2020531877A (en) * | 2017-08-16 | 2020-11-05 | 京東方科技集團股▲ふん▼有限公司Ｂｏｅ Ｔｅｃｈｎｏｌｏｇｙ Ｇｒｏｕｐ Ｃｏ．，Ｌｔｄ． | Shift register unit, shift register unit drive method, gate driver on array and display device |
-
2015
- 2015-10-20 CN CN201520816081.2U patent/CN205028629U/en active Active
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN105139798A (en) * | 2015-10-20 | 2015-12-09 | 京东方科技集团股份有限公司 | Driving circuit for touch screen, embedded touch screen and display device |
| WO2017067407A1 (en) * | 2015-10-20 | 2017-04-27 | 京东方科技集团股份有限公司 | Touch screen driver circuit , embedded touch screen and display device |
| US9953555B2 (en) | 2015-10-20 | 2018-04-24 | Boe Technology Group Co., Ltd. | Driving circuit for touch screen, in-cell touch screen and display apparatus |
| JP2020531877A (en) * | 2017-08-16 | 2020-11-05 | 京東方科技集團股▲ふん▼有限公司Ｂｏｅ Ｔｅｃｈｎｏｌｏｇｙ Ｇｒｏｕｐ Ｃｏ．，Ｌｔｄ． | Shift register unit, shift register unit drive method, gate driver on array and display device |
| JP7040732B2 (en) | 2017-08-16 | 2022-03-23 | 京東方科技集團股▲ふん▼有限公司 | Shift register unit, shift register unit drive method, gate driver on array and display device |
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