CN204887208U - Concatenation video data's system and device - Google Patents
Concatenation video data's system and device Download PDFInfo
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- CN204887208U CN204887208U CN201520686114.6U CN201520686114U CN204887208U CN 204887208 U CN204887208 U CN 204887208U CN 201520686114 U CN201520686114 U CN 201520686114U CN 204887208 U CN204887208 U CN 204887208U
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Abstract
The utility model discloses a concatenation video data's system and device for set up the FPGA of video data concatenation for setting up the video data of proportion all the way in advance of proportion in advance with the N way, be used for receiving the video data's after the concatenation APU, FPGA with APU connects, FPGA with APU connects to solve that traditional hardware implementation scheme exists to occupy the system bandwidth many.
Description
Technical field
The utility model relates to the technical field of Video processing, particularly relates to a kind of system and the device that splice video data.
Background technology
When designing two-path video splicing system, the video input mouth that usually can run into application processor APU is fewer, APU limited bandwidth, and the video input mouth of APU is in the majority with one, two.Current existing two-path video splicing system implementation is: need the video of splicing to be input to APU two-way simultaneously, can waste APU like this and input bandwidth.
Utility model content
The purpose of this utility model is to propose a kind of system and the device that splice video data, is intended to solve the problem of how splicing video data at not waste bandwidth.
For reaching this object, the utility model by the following technical solutions:
Splice a system for video data, described system comprises:
Video data for N road being pre-set ratio is spliced into the FPGA that a road pre-sets the video data of ratio, and for receiving the APU of spliced video data, described FPGA is connected with described APU, and described FPGA is connected with described APU.
Preferably, described FPGA comprises:
For receiving and storing the video input cache module of video data of camera shooting, for carrying out the video cutting module of cutting according to the effective coverage of presetting to the video data received, video for merging the video data after cutting merges module, described video input cache module and described video cutting model calling, described video cutting module and described video merge model calling.
Preferably, the ratio pre-set described in is 16:9 or 4:3.
Splice a device for video data, described device comprises:
For receiving and storing the video input cache module of video data of camera shooting, for carrying out the video cutting module of cutting according to the effective coverage of presetting to the video data received, video for merging the video data after cutting merges module, described video input cache module and described video cutting model calling, described video cutting module and described video merge model calling.
The utility model provides a kind of system and the FPGA that splice video data, video data for N road being pre-set ratio is spliced into the FPGA that a road pre-sets the video data of ratio, for receiving the APU of spliced video data, described FPGA is connected with described APU, described FPGA is connected with described APU, thus solve existing for conventional hardware implementation to take system bandwidth many.
Accompanying drawing explanation
Fig. 1 is that the utility model provides a kind of system construction drawing splicing video data;
Fig. 2 is a kind of high-level schematic functional block diagram of splicing the device of video data that the utility model provides.
Fig. 3 is a kind of method schematic diagram splicing video data that the utility model provides.
Embodiment
The technical solution of the utility model is further illustrated by embodiment below in conjunction with accompanying drawing.
That the utility model provides a kind of system construction drawing splicing the system of video data with reference to figure 1, Fig. 1.
In embodiment one, the system of described splicing video data comprises:
Video data for N road being pre-set ratio is spliced into the FPGA101 that a road pre-sets the video data of ratio, for receiving the APU102 of spliced video data, described FPGA101 is connected with described APU102, and described FPGA101 is connected with described APU102.
Preferably, be a kind of high-level schematic functional block diagram of splicing the device of video data that the utility model provides with reference to figure 2, Fig. 2.
Described FPGA101 comprises:
For receiving and storing the video input cache module 201 of video data of camera shooting, for carrying out the video cutting module 202 of cutting according to the effective coverage of presetting to the video data received, video for merging the video data after cutting merges module 203, described video input cache module 201 is connected with described video cutting module 202, and described video cutting module 202 merges module 203 with described video and is connected.
Preferably, the ratio pre-set described in is 16:9 or 4:3.
Concrete, be a kind of method schematic diagram splicing video data that the utility model provides with reference to figure 3, Fig. 3.As shown in Figure 3, two-way 16:9 (horizontal resolution of 16:9 presentation video and the ratio of vertical resolution) camera video, converts a road 16:9 video frequency output APU to through field programmable logic array (FPGA).Because the video that two-way is to be spliced, the part being actually used in splicing is limited, and two-path video can calculate in advance for the part of effective splicing, and the part that every road video is used for effectively splicing probably accounts for the half of its whole video area.Therefore when transmission of video, only need fractional transmission two-path video being used for effective splicing to APU, the present invention adopts scheme as shown in Figure 1, two-path video to be input in FPGA in video input buffer unit, then through video cutting module, output to two-path video and merge module, export as 16:9 video is to APU.
The schematic diagram of two-way 16:9 Video Composition one road 16:9 video as shown in Figure 3.Two-way 16:9 video will merge into a road 16:9 video according to following step.
Step 1: two-way 16:9 video input is to video input buffer unit.
Step 2: cutting is carried out respectively to the two-path video of step 1 buffer memory in the video effective coverage according to presetting.
Step 3: merged by the two-path video that step cutting completes, exports a road 16:9 video.
Can complete two-way 16:9 Video Composition according to above-mentioned steps 1,2,3 is a road 16:9 video.
The utility model provides a kind of system and the device that splice video data, video data for N road being pre-set ratio is spliced into the FPGA that a road pre-sets the video data of ratio, for receiving the APU of spliced video data, described FPGA is connected with described APU, described FPGA is connected with described APU, thus solve existing for conventional hardware implementation to take system bandwidth many.
Below know-why of the present utility model is described in conjunction with specific embodiments.These describe just in order to explain principle of the present utility model, and can not be interpreted as the restriction to the utility model protection range by any way.Based on explanation herein, those skilled in the art does not need to pay performing creative labour can associate other embodiment of the present utility model, and these modes all will fall within protection range of the present utility model.
Claims (4)
1. splice a system for video data, it is characterized in that, described system comprises:
Video data for N road being pre-set ratio is spliced into the FPGA that a road pre-sets the video data of ratio, and for receiving the APU of spliced video data, described FPGA is connected with described APU, and described FPGA is connected with described APU.
2. system according to claim 1, is characterized in that, described FPGA comprises:
For receiving and storing the video input cache module of video data of camera shooting, for carrying out the video cutting module of cutting according to the effective coverage of presetting to the video data received, video for merging the video data after cutting merges module, described video input cache module and described video cutting model calling, described video cutting module and described video merge model calling.
3. system according to claim 1, is characterized in that, described in the ratio that pre-sets be 16:9 or 4:3.
4. splice a device for video data, it is characterized in that, the device of described splicing video data comprises:
For receiving and storing the video input cache module of video data of camera shooting, for carrying out the video cutting module of cutting according to the effective coverage of presetting to the video data received, video for merging the video data after cutting merges module, described video input cache module and described video cutting model calling, described video cutting module and described video merge model calling.
Priority Applications (1)
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CN201520686114.6U CN204887208U (en) | 2015-09-07 | 2015-09-07 | Concatenation video data's system and device |
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CN201520686114.6U CN204887208U (en) | 2015-09-07 | 2015-09-07 | Concatenation video data's system and device |
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Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN107005703A (en) * | 2016-09-09 | 2017-08-01 | 深圳市大疆创新科技有限公司 | Method for encoding images and system |
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Cited By (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN107005703A (en) * | 2016-09-09 | 2017-08-01 | 深圳市大疆创新科技有限公司 | Method for encoding images and system |
WO2018045571A1 (en) * | 2016-09-09 | 2018-03-15 | 深圳市大疆创新科技有限公司 | Image coding method and system |
US10972681B2 (en) | 2016-09-09 | 2021-04-06 | SZ DJI Technology Co., Ltd. | Image encoding method and system |
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C14 | Grant of patent or utility model | ||
GR01 | Patent grant | ||
CF01 | Termination of patent right due to non-payment of annual fee | ||
CF01 | Termination of patent right due to non-payment of annual fee |
Granted publication date: 20151216 Termination date: 20210907 |