CN204375758U - There is the deep-groove power MOS component of superelevation cellular density - Google Patents
There is the deep-groove power MOS component of superelevation cellular density Download PDFInfo
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- CN204375758U CN204375758U CN201520062357.2U CN201520062357U CN204375758U CN 204375758 U CN204375758 U CN 204375758U CN 201520062357 U CN201520062357 U CN 201520062357U CN 204375758 U CN204375758 U CN 204375758U
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Abstract
The utility model relates to a kind of deep-groove power MOS component with superelevation cellular density, cellular in its cellular region adopts groove structure, on the cross section of power MOS (Metal Oxide Semiconductor) device, inwall and the bottom grown of cellular groove have gate oxide, are deposited with conductive polycrystalline silicon in cellular groove; Arrange thermal oxide layer at the notch of cellular groove, thermal oxide layer deposits insulating medium layer, described insulating medium layer and thermal oxide layer are only and be distributed in the notch of cellular groove; On the cross section of described power MOS (Metal Oxide Semiconductor) device, source contact openings extends down in the second conduction type well layer from the first conduction type source area, source metal is filled with, source metal and the first conduction type source area, the equal ohmic contact of the second conduction type well layer in source contact openings.The utility model compact conformation, can significantly reduce MOS device channel resistance, thus reduce the specific on-resistance of whole device.
Description
Technical field
The utility model relates to a kind of power MOS (Metal Oxide Semiconductor) device, and especially a kind of deep-groove power MOS component with superelevation cellular density, belongs to the technical field of power semiconductor.
Background technology
Power MOS (Metal Oxide Semiconductor) device with groove has the advantages that integrated level is high, conducting resistance is low, switching speed is fast, switching loss is little, is widely used in all kinds of power management and switch transition.Along with industrial expansion, global warming causes climatic environment more and more severe, various countries start more and more to pay attention to carbon reduction and sustainable development, therefore require more and more higher for the power consumption of power MOS (Metal Oxide Semiconductor) device and conversion efficiency thereof, when applying frequency is not high, power consumption determines primarily of conduction loss, and conduction loss is mainly limited by the impact of specific on-resistance size; Wherein, specific on-resistance is less, and conduction loss is less.
Reducing one of effective ways of specific on-resistance is by improving cellular density, increases the total effective width of unit are, thus reaches the object reducing specific on-resistance.Improve cellular density namely to need to reduce adjacent distance between cells (pitch), the minimum pitch of current existing domestic and international volume production is at about 1.0 μm, prior art again reduction is downwards limited by photolithographic process capability and mask aligner aligning accuracy, photolithographic process capability mainly refers to expose minimum groove live width and contact hole live width, the aligning accuracy of the main finger-hole exposure hole when of aligning accuracy and cellular groove.Current domestic batch production technique can expose and the minimum cellular trench line that the rear pattern of etching is good can be kept wide about 0.25 μm, final etching after making sacrificial oxide layer and insulated gate oxide layer, groove live width about 0.4 μm, domestic volume production can expose and can keep etching the good minimum cellular contact hole live width about 0.25 μm of rear pattern, 248nmDUV mask aligner aligning accuracy is at about 60nm, for ensureing enough process windows, cellular contact hole is at least 0.09 μm to the spacing finally finishing insulated gate oxide layer cellular groove, such prior art processes, the minimum pitch that can reach is about 0.83 μm, be difficult to reduce further.
Therefore, how by improving device layout, overcoming technological ability limitation, improving cellular density, reduce the important research direction that conducting resistance becomes those skilled in the art of the present technique.
Summary of the invention
The purpose of this utility model overcomes the deficiencies in the prior art, a kind of deep-groove power MOS component with superelevation cellular density is provided, its compact conformation, cellular density is only limited by minimum feature and the spacing of cellular groove, source contact openings etching adopts self-registered technology, be not limited by contact hole live width and the hole aligning accuracy to cellular groove, cellular density can rise to 2.133G single cell structure/inch2 from the 0.645G of common process single cell structure/inch2, can significantly reduce MOS device channel resistance, thus reduce the specific on-resistance of whole device.
According to the technical scheme that the utility model provides, the described deep-groove power MOS component with superelevation cellular density, in the top plan view of described power MOS (Metal Oxide Semiconductor) device, comprise and be positioned at cellular region on semiconductor substrate and terminal protection district, described cellular region is positioned at the center of semiconductor substrate, and terminal protection district is around the described cellular region of encirclement; On the cross section of described power MOS (Metal Oxide Semiconductor) device, semiconductor substrate comprises superposed first conductive type epitaxial layer and is positioned at the first conductivity type drain district of bottom, and described first conductivity type drain district and the first conductive type epitaxial layer adjoin;
In cellular region, top in first conductive type epitaxial layer is provided with the second conduction type well layer, some cellulars be arranged in parallel are comprised in cellular region, cellular in cellular region adopts groove structure, cellular groove is positioned at the second conduction type well layer, the degree of depth stretches in the first conductive type epitaxial layer below the second conduction type well layer, be provided with the first conduction type source area above the sidewall of adjacent cellular groove, described first conduction type source area is positioned at the top of the second conduction type well layer and contacts with the sidewall of cellular groove; It is characterized in that:
On the cross section of described power MOS (Metal Oxide Semiconductor) device, inwall and the bottom grown of cellular groove have gate oxide, in the cellular groove that described growth has gate oxide, be deposited with conductive polycrystalline silicon; At the notch of cellular groove, thermal oxide layer is set, described thermal oxide layer covers the conductive polycrystalline silicon below the gate oxide of cellular trenched side-wall and cellular groove notch, thermal oxide layer deposits insulating medium layer, and described insulating medium layer and thermal oxide layer are only and be distributed in the notch of cellular groove;
On the cross section of described power MOS (Metal Oxide Semiconductor) device, source contact openings is provided with above the second conduction type well layer, described source contact openings extends down in the second conduction type well layer from the first conduction type source area, source metal is filled with in source contact openings, described source metal and the first conduction type source area, the equal ohmic contact of the second conduction type well layer, and source metal and the conductive polycrystalline silicon in cellular groove are insulated mutually by insulating medium layer and thermal oxide layer and isolate.
Described first conductive type epitaxial layer comprises the first conduction type first epitaxial loayer and the first conduction type second epitaxial loayer, first conduction type first epitaxial loayer is positioned at the first conduction type second epitaxial loayer and the first conductivity type drain is interval, and the first conduction type first epitaxial layer adjacent first conductivity type drain district and the first conduction type second epitaxial loayer; Second conduction type well layer is positioned at the top of the first conduction type second epitaxial loayer; The degree of depth of cellular groove stretches in the first conduction type second epitaxial loayer or the first conduction type first epitaxial loayer.
Being distributed in thermal oxide layer in cellular groove notch and insulating medium layer as blocking masking layer, adopting Self-aligned etching technique, obtaining source contact openings.
In both described " the first conduction type " and " the second conduction type ", for N-type metal-oxide-semiconductor field effect transistor, the first conduction type refers to N-type, and the second conduction type is P type; For P type metal-oxide-semiconductor field effect transistor, the first conduction type is just in time contrary with N-type metal-oxide-semiconductor field effect transistor with the type of the second conduction type indication.
Advantage of the present utility model: in cellular groove, the top of conductive polycrystalline silicon and the growth of cellular trench sidewall area have thermal oxide layer, thermal oxide layer is deposited with insulating medium layer, described thermal oxide layer and insulating medium layer are only covered in the notch of cellular groove, utilize thermal oxide layer and insulating medium layer can realize the Self-aligned etching of source contact openings, namely the thermal oxide layer above dependence cellular groove and insulating medium layer, as blocking screen, realize the autoregistration of cellular groove lateral wall source contact openings and generally etch.Owing to being employing Self-aligned etching technique, therefore the cellular density of cellular region is no longer limited by contact hole live width and the contact hole aligning accuracy to cellular groove, only be limited by minimum feature and the spacing of cellular groove, 2.133G single cell structure/inch2 of 0.55 μm of pitch cellular density can be risen to from 0.645G single cell structure/inch2 of common process 1.0 μm of pitch cellular density, cellular density improves about 220%, can significantly reduce MOS device channel resistance, thus reduce the specific on-resistance of whole device.
Accompanying drawing explanation
Fig. 1 is structure cutaway view of the present utility model.
Fig. 2 ~ Figure 15 is concrete implementing process step cutaway view of the present utility model, wherein
Fig. 2 is the cutaway view of the utility model semiconductor substrate.
Fig. 3 is the cutaway view that the utility model obtains hard mask window.
Fig. 4 is the cutaway view after the utility model obtains cellular groove.
Fig. 5 is the cutaway view after the utility model obtains sacrificial oxide layer.
Fig. 6 is the cutaway view after the utility model obtains gate oxide.
Fig. 7 is the cutaway view after the utility model obtains Gate Electrode Conductive polysilicon material layer.
Fig. 8 is the cutaway view after the utility model obtains conductive polycrystalline silicon.
Fig. 9 is the cutaway view after the utility model P type well layer.
Figure 10 is the cutaway view after the utility model obtains N-type source area.
Figure 11 is the cutaway view after the utility model obtains thermal oxide layer.
Figure 12 is the cutaway view after the utility model obtains insulating medium layer.
Figure 13 is the cutaway view after the utility model etches insulating medium layer and thermal oxide layer.
Figure 14 is the cutaway view after the utility model obtains source contact openings.
Figure 15 is the cutaway view after the utility model obtains source metal.
Description of reference numerals: 1-N type drain region, 2-N type first epitaxial loayer, 3-N type second epitaxial loayer, 4-P type well layer, 5-source metal, 6-cellular groove, 7-N type source area, 8-source contact openings, 9-insulating medium layer, 10-thermal oxide layer, 11-gate oxide, 12-conductive polycrystalline silicon, 13-first interarea, 14-second interarea, 15-hard mask layer, the hard mask window of 16-, 17-sacrificial oxide layer and 18-notch.
Embodiment
Below in conjunction with concrete drawings and Examples, the utility model is described in further detail.
As shown in Fig. 1 and Figure 15: in order to significantly reduce MOS device channel resistance, thus reduce the specific on-resistance of whole device, for N-type power MOS (Metal Oxide Semiconductor) device, the utility model is in the top plan view of described power MOS (Metal Oxide Semiconductor) device, comprise and be positioned at cellular region on semiconductor substrate and terminal protection district, described cellular region is positioned at the center of semiconductor substrate, and terminal protection district is around the described cellular region of encirclement; On the cross section of described power MOS (Metal Oxide Semiconductor) device, semiconductor substrate comprises superposed N-type epitaxy layer and is positioned at the N-type drain electrode 1 of bottom, and described N-type drain electrode 1 adjoins with N-type epitaxy layer;
In cellular region, top in N-type epitaxy layer is provided with P type well layer 4, some cellulars be arranged in parallel are comprised in cellular region, cellular in cellular region adopts groove structure, cellular groove 6 is positioned at P type well layer 4, the degree of depth stretches in the N-type epitaxy layer below P type well layer 4, is provided with N-type source area 7 above the sidewall of adjacent cellular groove 6, and described N-type source area 7 is positioned at the top of P type well layer 4 and contacts with the sidewall of cellular groove 6;
On the cross section of described power MOS (Metal Oxide Semiconductor) device, inwall and the bottom grown of cellular groove 6 have gate oxide 11, in the cellular groove 6 that described growth has gate oxide 11, be deposited with conductive polycrystalline silicon 12; At the notch 18 of cellular groove 6, thermal oxide layer 10 is set, described thermal oxide layer 10 covers the conductive polycrystalline silicon 12 below the gate oxide 11 of cellular groove 6 sidewall and cellular groove notch 18, thermal oxide layer 10 deposits insulating medium layer 9, and described insulating medium layer 9 and thermal oxide layer 10 are only and be distributed in the notch 18 of cellular groove 6;
On the cross section of described power MOS (Metal Oxide Semiconductor) device, source contact openings 8 is provided with above P type well layer 4, described source contact openings 8 extends down in P type well layer 4 from N-type source area 7, source metal 5 is filled with in source contact openings 8, described source metal 5 and N-type source area 7, the equal ohmic contact of P type well layer 4, and source metal 5 and the conductive polycrystalline silicon in cellular groove 6 12 pass through insulating medium layer 9 and thermal oxide layer 10 phase insulate and isolate.
Particularly; the terminal protection district of corresponding power MOS (Metal Oxide Semiconductor) device can be not limited to any form; form P type well layer 4 in N-type epitaxy layer after; on the cross section of cellular region; P well layer 4 is positioned at the top of N-type epitaxy layer; the bottom land of cellular groove 6 is positioned at the below of P well layer 4, and N-type source area 7 is positioned at the top of adjacent cellular groove 6 sidewall, and N-type source area 7 is overlapped mutually with the conductive polycrystalline silicon 12 in cellular groove 6.
In the utility model embodiment, thermal oxide layer 10 and insulating medium layer 9 are only and be distributed in the notch position of cellular groove 6, the gate oxide 11 that thermal oxide layer 10 is corresponding with cellular groove 6 inner tank mouths 18 position and the conductive polycrystalline silicon 12 being positioned at notch 18 position contact, insulating medium layer 9 covers on thermal oxide layer 10, can as blocking screen by insulating medium layer 9 and thermal oxide layer 10, the autoregistration realizing cellular groove 6 lateral wall source contact openings 8 generally etches, contact hole live width and the source contact openings aligning accuracy to cellular groove 6 is no longer limited by make the cellular density of cellular region, namely to be distributed in thermal oxide layer 10 in cellular groove notch 18 and insulating medium layer 9 as blocking masking layer, adopt Self-aligned etching technique, obtain source contact openings 8, thus can significantly reduce MOS device channel resistance, reduce the specific on-resistance of whole MOS device.
Source contact openings 8 runs through N-type source area 7 and enters in P type well layer 4, and the degree of depth of source contact openings 8 in P type well layer 4 is not more than the degree of depth of P type well layer 4, after source contact openings 8 runs through N-type source area 7, obtain the N-type source area 7 on cellular groove 6 lateral wall, source metal 5 all contacts with N-type source area 7 and P type well layer 4, and source metal 5 and N-type source area 7 and the equal ohmic contact of P type well layer 4, the source electrode of power MOS (Metal Oxide Semiconductor) device can be obtained by source metal 5, because insulating medium layer 9 and thermal oxide layer 10 are distributed in the notch 18 of cellular groove 6, therefore, the conductive polycrystalline silicon 12 being positioned at cellular groove 6 is isolated with source metal 5 mutually insulated by insulating medium layer 9 and thermal oxide layer 10, the gate electrode that can not affect whole MOS device is drawn.
Further, described N-type epitaxy layer comprises N-type first epitaxial loayer 2 and N-type second epitaxial loayer 3, and N-type first epitaxial loayer 2 is positioned between N-type second epitaxial loayer 3 and N-type drain electrode 1, and N-type first epitaxial loayer 2 adjoins N-type drain electrode 1 and N-type second epitaxial loayer 3; P type well layer 4 is positioned at the top of N-type second epitaxial loayer 3; The degree of depth of cellular groove 6 stretches in N-type second epitaxial loayer 3 or N-type first epitaxial loayer 2.The degree of depth of cellular groove 6 can not be greater than the thickness of N-type epitaxy layer, and namely the bottom land of cellular groove 6 is positioned at the top of N-type drain electrode 1.
As shown in Fig. 2 ~ Figure 15, above-mentioned have superelevation cellular density deep-groove power MOS component, and can be prepared by following processing step, concrete steps comprise:
A, provide the semiconductor substrate with two opposing main faces, described two opposing main faces comprise the first interarea 13 and the second interarea 14, N-type epitaxy layer and N-type drain electrode 1 is comprised between the first interarea and 13 second interareas 14, the upper surface of N-type epitaxy layer forms the first interarea 13 of semiconductor substrate, and the lower surface of N-type drain electrode 1 forms the second interarea 14 of semiconductor substrate;
As shown in Figure 2, the material of semiconductor substrate comprises silicon, N-type epitaxy layer comprises N-type first epitaxial loayer 2 and N-type second epitaxial loayer 3, the doping content of N-type drain electrode 1 is greater than the doping content of N-type first epitaxial loayer 2, the doping content of N-type first epitaxial loayer 2 is greater than the doping content of N-type second epitaxial loayer 3, and in the specific implementation, N-type epitaxy layer also can only include N-type first epitaxial loayer 2 or N-type second epitaxial loayer 3, specifically can select as required, repeat no more herein.
B, on the first interarea 13 of above-mentioned semiconductor substrate deposit hard mask layer 15, optionally shelter and etch hard mask layer 15, to form the hard mask window 16 of etching groove above the first interarea 13 of semiconductor substrate;
As shown in Figure 3, described hard mask layer 15 is LPTEOS, thermal oxidation silicon dioxide adds chemical vapour deposition (CVD) silicon dioxide or thermal silicon dioxide adds silicon nitride.The through hard mask layer 15 of hard mask window 16, the technical process the first interarea 13 of semiconductor substrate arranging hard mask layer 15 and obtains hard mask window 16 is known by the art personnel, repeats no more herein.
C, utilize above-mentioned hard mask window 16, the first interarea 13 of etching semiconductor substrate, to obtain required deep trench in semiconductor substrate, described deep trench comprises cellular groove 6;
As shown in Figure 4, position due to hard mask window 16 can be carried out selection as required and be arranged, there is the position of hard mask window 16 again by exposed for semiconductor substrate first interarea 13 of bottom, by dry etching semiconductor substrate, thus having the position of hard mask window 16 to obtain deep trench, because cellular region in the utility model adopts groove structure, therefore, deep trench comprises cellular groove 6, cellular groove 6 is from the first interarea 13 to downward-extension, and the degree of depth of cellular groove 6 is not more than the thickness of N-type epitaxy layer.
D, on above-mentioned the first interarea 14 moving substrate to, grow sacrificial oxide layer 17, described sacrificial oxide layer 17 covers the first interarea 13 of semiconductor substrate, and is covered in sidewall and the diapire of cellular groove 6;
As shown in Figure 5, sacrificial oxide layer 17 carbon dioxide layer, sacrificial oxide layer 17 can be obtained by thermal oxide growth.
E, by etching remove the above-mentioned sacrificial oxide layer 17 be covered in the first interarea 13 and cellular groove 6, and gate oxide 11 is grown on the first interarea 13 removing sacrificial oxide layer 17, described gate oxide 11 covers the first interarea 13 of semiconductor substrate, and covers sidewall and the diapire of cellular groove 6;
As shown in Figure 6, the impurity in semiconductor substrate first interarea 13 and cellular groove 6 can be removed by sacrificial oxide layer 17, improve the cleannes in semiconductor substrate first interarea 13 and cellular groove 6, remove sacrificial oxide layer 17 and can adopt existing conventional etching technics, specifically repeat no more.After removal sacrificial oxide layer 17, thermal oxide growth obtains gate oxide 11 again.
F, on the first interarea 13 of above-mentioned semiconductor substrate deposit Gate Electrode Conductive polysilicon material layer, described Gate Electrode Conductive polysilicon material layer to be filled in cellular groove 6 and to cover on the gate oxide 11 above the first interarea 13;
As shown in Figure 7, by Gate Electrode Conductive polysilicon material layer for the formation of conductive polycrystalline silicon.
G, remove Gate Electrode Conductive polysilicon material layer above above-mentioned semiconductor substrate first interarea 13, to obtain the conductive polycrystalline silicon 12 being positioned at cellular groove 6;
As shown in Figure 8, remove the Gate Electrode Conductive polysilicon material layer above semiconductor substrate first interarea 13, obtain the conductive polycrystalline silicon 12 being positioned at cellular groove 6, the conductive polycrystalline silicon 12 in cellular groove 6 lower than the height of cellular groove 6, to have one section of vacant height at the notch of cellular groove 6.The concrete technology removing Gate Electrode Conductive polysilicon material layer on the first interarea 13, known by the art personnel, repeats no more herein.
H, on the first interarea 13 of above-mentioned semiconductor substrate implanting p-type foreign ion, and by forming the P type well layer 4 being positioned at cellular region after pushing away trap in N-type epitaxy layer, the bottom land of cellular groove 6 is positioned at the below of cellular region P type well layer 4;
As shown in Figure 9, implanting p-type foreign ion above the first interarea 13 of semiconductor substrate, thus after pushing away trap, form P type well layer 4, implanting p-type concentration impurity ion and push away trap process known by the art personnel, repeat no more herein, the degree of depth of P type well layer 4 in N-type epitaxy layer is less than the degree of depth of cellular groove 6, and namely the bottom land of cellular groove 6 is positioned at the below of P type well layer 4.
I, on the first interarea 13 of above-mentioned semiconductor substrate, carry out source area photoetching, and inject N-type impurity ion, by forming N-type source area 7 after knot in the P type well layer 4 of cellular region;
As shown in Figure 10, after formation P well layer 4, by injecting N-type impurity ion and source area photoetching, thus N-type source area 7 is formed in P type well layer 4, the process of carrying out source area photoetching and injection N-type impurity ion knot formation N-type source area 7 is the technological means that the art is commonly used, known by the art personnel, repeat no more herein.
J, on the first interarea 13 of above-mentioned semiconductor substrate by thermal oxide growth thermal oxide layer 10;
As shown in figure 11, thermal oxide layer 10 is silicon dioxide layer, and the thickness of described thermal oxide layer 10 is 1000 à ~ 5000 à.Because gate oxide 11 and thermal oxide layer 10 are silicon dioxide layer, therefore, the silicon dioxide layer on the first interarea 13, all forms the thermal oxide layer 10 of silicon dioxide layer.
K, on the first interarea 13 of above-mentioned semiconductor substrate, deposit insulating medium layer 9, described insulating medium layer 9 covers on thermal oxide layer 10;
As shown in figure 12, described insulating medium layer 9 is silex glass (USG), boron-phosphorosilicate glass (BPSG) or phosphorosilicate glass (PSG).
L, carry out contact hole photoetching to above-mentioned insulating medium layer 9, to obtain the source contact openings 8 be positioned at outside cellular groove 6, described source contact openings 8 extends down in P type well layer 4 from N-type source area 7;
As shown in Figure 13 and Figure 14, in step l, specifically comprise the steps:
L1, the insulating medium layer 9 above semiconductor substrate first interarea 13 and thermal oxide layer 10 to be etched, to remove insulating medium layer 9 outside cellular groove notch 18 and thermal oxide layer 10;
In the utility model embodiment, insulating medium layer 9 and thermal oxide layer 10 are etched, until the insulating medium layer 9 on the first interarea 13 is etched totally with thermal oxide layer 10, namely the insulating medium layer 9 and the thermal oxide layer 10 that are positioned at notch 18 is retained, the technique etched insulating medium layer 9 and thermal oxide layer 10 is known by the art personnel, repeat no more, the result after etching as shown in figure 13 herein.
L2, the insulating medium layer 9 of cellular groove notch and thermal oxide layer 10 is utilized to carry out Self-aligned etching, to obtain source contact openings 8.
Utilize insulating medium layer 9 and thermal oxide layer 10 as blocking screen, silicon etching is carried out to semiconductor substrate, after adopting the autoregistration of contact hole generally to etch, source contact openings 8 can be obtained, source contact openings 8 runs through N-type source area 7, thus also can obtain the N-type source area 7 that contacts above cellular groove 6 sidewall and with the lateral wall of cellular groove 6, as shown in figure 14.
M, on the first interarea 13 of above-mentioned semiconductor substrate implanting p-type foreign ion annealing;
In the utility model embodiment, the concentration of implanting p-type foreign ion can not affect N-type source area 7, the processing step that implanting p-type foreign ion carrying out is annealed, and can improve the reliability of source metal 5 and N-type source area 7 and P type well layer 4 ohmic contact.Described p type impurity ion is generally BF
2(boron difluoride) or B(boron), Implantation Energy is usually at 20kev ~ 80kev, and implantation dosage is usually between 1e13 ~ 1e15, and annealing temperature is usually at 700 DEG C ~ about 900 DEG C.
N, above the first interarea 13 of above-mentioned semiconductor substrate deposited metal, described metal level to be filled in source contact openings 8 and is covered on the insulating medium layer 9 above cellular groove notch 18, to form metal connecting line; Described metal connecting line comprises source metal 5, described source metal 5 and N-type source area 7 and the equal ohmic contact of P type well layer 4.
As shown in figure 15, the materials and process that the metal level of deposit can adopt the art conventional, can form the electrode of power MOS (Metal Oxide Semiconductor) device, namely comprise source metal 5 of the present utility model, can form source electrode by source metal 5 at the metal connecting line formed.
In the utility model cellular groove 6, the top of conductive polycrystalline silicon 12 and the growth of cellular groove 6 sidewall areas have thermal oxide layer 10, thermal oxide layer 10 is deposited with insulating medium layer 9, described thermal oxide layer 10 and insulating medium layer 9 are only covered in the notch 18 of cellular groove 6, utilize thermal oxide layer 10 and insulating medium layer 9 can realize the Self-aligned etching of source contact openings 8, namely the thermal oxide layer 10 above dependence cellular groove 6 and insulating medium layer 9, as blocking screen, realize the autoregistration of cellular groove 6 lateral wall source contact openings and generally etch.Owing to being employing Self-aligned etching technique, therefore the cellular density of cellular region is no longer limited by contact hole live width and the contact hole aligning accuracy to cellular groove 6, only be limited by minimum feature and the spacing of cellular groove 6,2.133G single cell structure/inch2 of 0.55 μm of pitch cellular density can be risen to from 0.645G single cell structure/inch2 of common process 1.0 μm of pitch cellular density, cellular density improves about 220%, can significantly reduce MOS device channel resistance, thus reduce the specific on-resistance of whole device.
Claims (3)
1. one kind has the deep-groove power MOS component of superelevation cellular density, in the top plan view of described power MOS (Metal Oxide Semiconductor) device, comprise and be positioned at cellular region on semiconductor substrate and terminal protection district, described cellular region is positioned at the center of semiconductor substrate, and terminal protection district is around the described cellular region of encirclement; On the cross section of described power MOS (Metal Oxide Semiconductor) device, semiconductor substrate comprises superposed first conductive type epitaxial layer and is positioned at the first conductivity type drain district of bottom, and described first conductivity type drain district and the first conductive type epitaxial layer adjoin;
In cellular region, top in first conductive type epitaxial layer is provided with the second conduction type well layer, some cellulars be arranged in parallel are comprised in cellular region, cellular in cellular region adopts groove structure, cellular groove is positioned at the second conduction type well layer, the degree of depth stretches in the first conductive type epitaxial layer below the second conduction type well layer, be provided with the first conduction type source area above the sidewall of adjacent cellular groove, described first conduction type source area is positioned at the top of the second conduction type well layer and contacts with the sidewall of cellular groove; It is characterized in that:
On the cross section of described power MOS (Metal Oxide Semiconductor) device, inwall and the bottom grown of cellular groove have gate oxide, in the cellular groove that described growth has gate oxide, be deposited with conductive polycrystalline silicon; At the notch of cellular groove, thermal oxide layer is set, described thermal oxide layer covers the conductive polycrystalline silicon below the gate oxide of cellular trenched side-wall and cellular groove notch, thermal oxide layer deposits insulating medium layer, and described insulating medium layer and thermal oxide layer are only and be distributed in the notch of cellular groove;
On the cross section of described power MOS (Metal Oxide Semiconductor) device, source contact openings is provided with above the second conduction type well layer, described source contact openings extends down in the second conduction type well layer from the first conduction type source area, source metal is filled with in source contact openings, described source metal and the first conduction type source area, the equal ohmic contact of the second conduction type well layer, and source metal and the conductive polycrystalline silicon in cellular groove are insulated mutually by insulating medium layer and thermal oxide layer and isolate.
2. the deep-groove power MOS component with superelevation cellular density according to claim 1, it is characterized in that: described first conductive type epitaxial layer comprises the first conduction type first epitaxial loayer and the first conduction type second epitaxial loayer, first conduction type first epitaxial loayer is positioned at the first conduction type second epitaxial loayer and the first conductivity type drain is interval, and the first conduction type first epitaxial layer adjacent first conductivity type drain district and the first conduction type second epitaxial loayer; Second conduction type well layer is positioned at the top of the first conduction type second epitaxial loayer; The degree of depth of cellular groove stretches in the first conduction type second epitaxial loayer or the first conduction type first epitaxial loayer.
3. the deep-groove power MOS component with superelevation cellular density according to claim 1, it is characterized in that: to be distributed in thermal oxide layer in cellular groove notch and insulating medium layer as blocking masking layer, adopt Self-aligned etching technique, obtain source contact openings.
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| CN104576743A (en) * | 2015-01-28 | 2015-04-29 | 无锡新洁能股份有限公司 | Deep-groove power MOS (metal oxide semiconductor) device with ultrahigh cellular density and manufacturing method of deep-groove power MOS device |
| CN110010693A (en) * | 2019-05-07 | 2019-07-12 | 无锡紫光微电子有限公司 | A kind of structure and preparation method thereof of high pressure deep slot type super node MOSFET |
| CN112133750A (en) * | 2019-06-25 | 2020-12-25 | 华润微电子（重庆）有限公司 | Deep trench power device and preparation method thereof |
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| CN104576743A (en) * | 2015-01-28 | 2015-04-29 | 无锡新洁能股份有限公司 | Deep-groove power MOS (metal oxide semiconductor) device with ultrahigh cellular density and manufacturing method of deep-groove power MOS device |
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| CN110010693B (en) * | 2019-05-07 | 2024-03-12 | 无锡紫光微电子有限公司 | Structure of high-voltage deep trench type super-junction MOSFET and manufacturing method thereof |
| CN112133750A (en) * | 2019-06-25 | 2020-12-25 | 华润微电子（重庆）有限公司 | Deep trench power device and preparation method thereof |
| CN112133750B (en) * | 2019-06-25 | 2024-02-13 | 华润微电子（重庆）有限公司 | Deep trench power device and preparation method thereof |
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