CN204068926U - Apply the radioresistance latch of four input protection doors - Google Patents

Abstract

The utility model relates to radiation hardened integrated circuit design field.For providing a kind of latch that can be applied under radiation environment, SEU and part MBU can be resisted.When there is dibit upset due to particle bombardment in the memory node of latch and input signal; this latch can be released the electric charge be deposited on sensitive nodes by shutter; thus the store status of latch can not be changed, make correct level signal import late-class circuit into.For this reason; the technical solution adopted in the utility model is; apply the radioresistance latch of four input protection doors; by 7 transmission gate TG1 ~ 6; 3 inverter INV1 ~ 3; 3 two input protection doors (Double Input Guardgate, DIG) DIG1 ~ 3 and four input protection doors are formed.The utility model is mainly used in radiation hardened integrated circuit design.

Description

Apply the radioresistance latch of four input protection doors

Technical field

The utility model relates to radiation hardened integrated circuit design field; especially design use two input protection door and four input protection doors are reinforced sequence circuit; there is anti-single particle overturn (Single event upset; SEU) and part resist the ability of many bit reversals (Multiple-bit upset, MBU).Specifically, the radioresistance latch of a kind of application four input protection doors is related to.

Background technology

Application of integrated circuit is when space field, particle bombardment can be suffered to cause soft error, radiation mechanism in common space has the bombardment of α particle, high energy neutrons, high energy cosmic ray, low energy cosmic neutron, and these particles are beaten and caused transistor internal to produce unlatching or the shutoff of excess charge and mistake to silicon face.For the digital circuit be applied in space environment, particularly sequence circuit, the generation of single-particle inversion can have a strong impact on the correctness of chip functions.When the quantity of electric charge injected is not enough to cause level to overturn and causes the momentary pulse of level, there is single-ion transient state effect (Single Event Transient, SET).Existing reinforcement technique is most for SEU, but along with the reduction of integrated circuit dimensions and the decline of chip power supply voltage, MBU odds progressively rises, thus affects the performance of circuit.

Latch is the most frequently used memory cell arrived in circuit, and the reinforcing for latch is particularly important.Conventional design reinforcement method (Radiation Hardened-by Design, RHBD) has module redundancy and uses shutter.Module redundancy can increase circuit area and power consumption greatly, and shutter circuit then can not.That conventional is two input protection doors (Double Input Guard_gate, DIG), can resist SEU and SET occurring in two inputs.This structure also applies four input protection doors (Four Input Guard_gate, FIG) in addition.

Summary of the invention

For overcoming the deficiencies in the prior art, the utility model aims to provide a kind of latch that can be applied under radiation environment, can resist SEU and part MBU.When there is dibit upset due to particle bombardment in the memory node of latch and input signal; this latch can be released the electric charge be deposited on sensitive nodes by shutter; thus the store status of latch can not be changed, make correct level signal import late-class circuit into.For this reason, the technical solution adopted in the utility model is, apply the radioresistance latch of four input protection doors, by 7 transmission gate TG1 ~ 6, 3 inverter INV1 ~ 3, 3 two input protection doors (Double Input Guardgate, DIG) DIG1 ~ 3 and four input protection doors are formed, in the input signal that four tunnels are identical three tunnels respectively correspondence be input to input D1, D2, D3, input D1, D2, D3 is corresponding in turn to by transmission gate TG1, transmission gate T G2, transmission gate TG3 sends into two corresponding input protection door DIG1 ~ 3, input signal is through input D1, input D2 is as the input of two input protection door DIG1, the output A of two input protection door DIG1 is connected to input D1 through inverter INV1 and transmission gate TG5, input D2, input D3 are as the input of two input protection door DIG2, and the output B of two input protection door DIG2 is connected to input D2 via inverter INV2 and transmission gate TG6, input D1, input D3 are as the input of two input protection door DIG3, and the output C of two input protection door DIG3 is connected to input D3 through inverter INV3 and TG7, export A, B, C input signal as four input protection doors, the road beyond aforementioned three road input signals inputs four input protection doors and exports Q.

Two input protection door DIG structures are, use two PMOS PM1 and PM2 series connection, two NMOS tube NM1 and NM2 series connection; The source class of PM1 meets VDD, and the drain electrode of PM2 connects the drain electrode of NM2, and the source class of NM1 meets GND, and the grid of PM1 and NM1 inputs B as the grid that inputs A, PM2 and NM2 as another, and the drain electrode of PM2 and NM2 is as output O.

The structure of four input protection doors is, uses four PMOS series connection, four NMOS tube series connection; The source class of the 4th PMOS meets VDD, the drain electrode of the 1st PMOS connects the drain electrode of the 1st NMOS tube, the source class of the 4th NMOS tube meets GND, the grid of the 1st NMOS tube and the 1st PMOS connects just anticlockwise respectively, the grid of the 2nd NMOS tube and the 2nd PMOS is as an input, the grid of the 3rd NMOS tube and the 3rd PMOS inputs as another, the grid of the 4th NMOS tube and the 4th PMOS is re-used as an input, and the drain electrode of the 1st NMOS tube and the 1st PMOS is as output O.

Technical characterstic of the present utility model and effect:

The utility model is reinforced circuit by the means of structural design, therefore, it is possible to upset while multiple sensitive nodes in the different traps that cause due to single radiating particle of opposing, thus the store status of latch can not be changed.

The utility model, owing to directly reaching Q by D when the transparent stage, reduces propagation delay, and is by D Direct driver Q, so the size of FIG transistor can use minimum dimension, reduce chip area.

Accompanying drawing explanation

Fig. 1 applies the circuit structure of the radioresistance latch of four input protection doors;

The transistor-level structure of Fig. 2 (a) DIG, the logical symbol of (b) DIG, the sequential chart of (c) DIG;

The transistor-level structure of Fig. 3 (a) FIG, the logical symbol of (b) FIG, the sequential chart of (c) FIG.

Embodiment

The formation of the utility model latch uses 7 transmission gate TG1 ~ 7,3 inverter INV1 ~ 3,3 two input protection door DIG1 ~ 3 and FIG.The identical input signal in Ta You tetra-tunnel is respectively D1, D2, D3, D4, and they send into latch each via switch TG1, TG2, TG3, TG4.D1, D2 are as the input of DIG1, and the output A of DIG1 feeds back to its an input D1 through an inverter INV1 and switch TG5.Same D2, D3, as the input of DIG2, export B and feed back to D2 via INV2 and TG6.D1, D3, as the input of DIG3, export C and feed back to D3 through INV3 and TG7.A connects PM4 and NM4 of FIG structure, and B connects PM3 and NM3, and C connects PM2 and NM2, and PM1 meets clock signal C K, and NM1 meets the anti-phase NCK of clock signal.Output is Q.DIG is wherein (as Fig. 2 (a) is depicted as its transistor-level structure, b () is its logical symbol, c () is its sequential chart) use two PMOS and two NMOS series connection, PM1 and PM2 connects, NM1 and NM2 connects, the source class of PM1 meets VDD, the drain electrode of PM2 connects the drain electrode of NM2, and the source class of NM1 meets GND, and the grid of PM1 and NM1 is as an input A, the grid of PM2 and NM2 inputs B as another, and the drain electrode of PM2 and NM2 is as output O.It is high-impedance state that DIG inputs not identical time output at two.When two input signals are identical, the function of this unit is consistent with the function of inverter.FIG is (as Fig. 3 (a) is depicted as its transistor-level structure, b () is its logical symbol, c () is its sequential chart) similar with DIG, four PMOS and four NMOS are used to connect, there are four inputs, export as high-impedance state when four input signals are not identical.When four input signals are identical, the function of this unit is consistent with the function of inverter.

Latch is in the transparent stage when CK=1, TG1 ~ 4 conducting, and TG5 ~ 7 are ended, and FIG ends.The conducting of D4 branch road, input signal directly passes to Q.Latch is in the maintenance stage when CK=0, and TG1 ~ 4 are ended, and TG5 ~ 7 conducting, FIG conducting, the state of D1, D2, D3 passes to Q via DIG.May there is SEU and MBU in the maintenance stage, need to protect this.

Internal node has 7, keeps stage TG4 to disconnect, so whether D4 does not correctly affect Q.Remaining 6 nodes can be divided into 2 groups, are node { D1, D2, D3} and { A, B, C}, also can classify by Component units, is divided into 3 branch roads { DIG1, INV1}, { DIG2, INV2}, { DIG3, INV3} respectively.When there is SEU, can be divided into 2 classes, namely SEU occurs in the first group node and the second group node respectively.First analyze D2 and A node and how to shield SEU, other the first group node and D2 similar, the second group node and category-A are seemingly.When SEU occurs in D2, D2 is the input of DIG1 and DIG2, so these two DIG state floatings, export A and B and C and remain unchanged within this clock cycle, shielding mistake, latch exports Q and also just remains unchanged.When SEU occurs in node A, branch road DIG1, INV1} floating, but B and C keeps normal, remains unchanged so latch exports Q.

When there is binode upset (Double-node Upset, DNU), having 15 kinds of combinations, can be divided three classes.We get three kinds of typical case and are described.When DNU occurs D1 and D2, two inputs of DIG1 change simultaneously, and the state of A overturns, { DIG1, INV1} floating, makes the state of D1 irrecoverable within this clock cycle by INV1 to branch road, and the state of B is constant, the state of D2 is recovered by INV2, and the state of C is also constant.So there is a state A change in three of TIG inputs, exports Q and remain unchanged.When DNU occurs in D2 and A, the error level of A makes D1 overturn by INV1, two input signal D1 and D2 all mistakes of DIG2, the upset so B also makes a mistake, branch road { DIG1, INV1} and { DIG2, INV2} floating.But C is correct, so the output level of TIG is still correct.When DNU occurs in A and B, the state of D1 and D2 to be made a mistake upset by INV1 and INV2, branch road { DIG1, INV1} and { DIG2, INV2} floating, but D3 and C is correct, so the output Q of TIG is still correct.If level upset is irresistible but output node Q makes a mistake.So the opposing probability of DNU is

Unit	PMOS/ minimum dimension	NMOS/ minimum dimension
			Switch	1	1
Inverter	2	1
			DIG	4	2
FIG	2	1

Table 1

The breadth length ratio of this circuit transistor used is as shown in table 1.In circuit transmission gate transistor used adopt minimum dimension (in 180nm commercial standard (CS) cell library the minimum length of PMOS raceway groove and wide be 220nm and 180nm respectively, i.e. breadth length ratio 180/220), the width of the P pipe of inverter is 2 times of minimum widith, ensures the consistent of rise time and fall time.DIG transistor size used be 2 times of inverter to ensure to drive intensity, the size of TIG transistor used is identical with inverter, can reduce chip area.

Claims (3)

1. the radioresistance latch of application four input protection doors, it is characterized in that, by 7 transmission gate TG1 ~ 6, 3 inverter INV1 ~ 3, 3 two input protection doors (Double Input Guardgate, DIG) DIG1 ~ 3 and four input protection doors are formed, in the input signal that four tunnels are identical three tunnels respectively correspondence be input to input D1, D2, D3, input D1, D2, D3 is corresponding in turn to by transmission gate TG1, transmission gate T G2, transmission gate TG3 sends into two corresponding input protection door DIG1 ~ 3, input signal is through input D1, input D2 is as the input of two input protection door DIG1, the output A of two input protection door DIG1 is connected to input D1 through inverter INV1 and transmission gate TG5, input D2, input D3 are as the input of two input protection door DIG2, and the output B of two input protection door DIG2 is connected to input D2 via inverter INV2 and transmission gate TG6, input D1, input D3 are as the input of two input protection door DIG3, and the output C of two input protection door DIG3 is connected to input D3 through inverter INV3 and TG7, export A, B, C input signal as four input protection doors, the road beyond aforementioned three road input signals inputs four input protection doors and exports Q.

2. the radioresistance latch of application as claimed in claim 1 four input protection doors, it is characterized in that, two input protection door DIG structures are, use two PMOS PM1 and PM2 series connection, two NMOS tube NM1 and NM2 series connection; The source class of PM1 meets VDD, and the drain electrode of PM2 connects the drain electrode of NM2, and the source class of NM1 meets GND, and the grid of PM1 and NM1 inputs B as the grid that inputs A, PM2 and NM2 as another, and the drain electrode of PM2 and NM2 is as output O.

3. the radioresistance latch of application as claimed in claim 1 four input protection doors, it is characterized in that, the structure of four input protection doors is: use four PMOS series connection, four NMOS tube series connection; The source class of the 4th PMOS meets VDD, the drain electrode of the 1st PMOS connects the drain electrode of the 1st NMOS tube, the source class of the 4th NMOS tube meets GND, the grid of the 1st NMOS tube and the 1st PMOS connects just anticlockwise respectively, the grid of the 2nd NMOS tube and the 2nd PMOS is as an input, the grid of the 3rd NMOS tube and the 3rd PMOS inputs as another, the grid of the 4th NMOS tube and the 4th PMOS is re-used as an input, and the drain electrode of the 1st NMOS tube and the 1st PMOS is as output O.