CN1934558A - Signaling arrangement and approach therefor - Google Patents
Signaling arrangement and approach therefor Download PDFInfo
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- CN1934558A CN1934558A CNA2005800087305A CN200580008730A CN1934558A CN 1934558 A CN1934558 A CN 1934558A CN A2005800087305 A CNA2005800087305 A CN A2005800087305A CN 200580008730 A CN200580008730 A CN 200580008730A CN 1934558 A CN1934558 A CN 1934558A
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- pci express
- point devices
- communication link
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/38—Information transfer, e.g. on bus
- G06F13/42—Bus transfer protocol, e.g. handshake; Synchronisation
- G06F13/4282—Bus transfer protocol, e.g. handshake; Synchronisation on a serial bus, e.g. I2C bus, SPI bus
- G06F13/4295—Bus transfer protocol, e.g. handshake; Synchronisation on a serial bus, e.g. I2C bus, SPI bus using an embedded synchronisation
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/14—Handling requests for interconnection or transfer
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/38—Information transfer, e.g. on bus
- G06F13/42—Bus transfer protocol, e.g. handshake; Synchronisation
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Abstract
A communications arrangement is implemented for tag-field type communications signaling. According to an example embodiment of the present invention, a communications arrangement, such as a PCI Express type arrangement, is configurable for communicating over a communications link using a tag (or similar) available field. According to an example embodiment of the present invention involving PCI Express communications, a first PCI Express endpoint device (150) is adapted to communicate selected information (e.g., synchronous event signals) to a second PCI Express endpoint device (152) using the tag field of data posted to a PCI Express communications link (130). The tag field is set to indicate a characteristic of the synchronous event, and passed from the first PCI Express endpoint device to the second PCI Express endpoint device.
Description
Invention field
Present invention relates in general to transmission information and relate in particular to usage flag (or similarly) field transmit the information transmission of information.
Background technology
For various purposes and utilize various dissimilar devices and system to carry out many dissimilar electronic communications.One type electronic communication system relates to those communications that are associated with BUS type communication between two or more different assemblies.For example, computing machine comprises the central processing unit (CPU) of communicating by letter with peripheral unit via bus in typical case.Between the peripheral unit on CPU and communication bus or other link, transmit instruction and other information.
One type communication means relates to PCI (periphery component interconnection) system that uses.PCI is the interconnection system between microprocessor and auxiliary equipment, makes expansion slot closely separately so that high speed operation in described auxiliary equipment.Use PCI, computing machine can support new pci card to continue supporting industry standard architecture (ISA) expansion card simultaneously, and described industry standard architecture is an older standard.PCI is designed to be independent of microprocessor Design and synchronous with the clock speed of microprocessor.PCI uses (multiple spot connects on (multi-drop) bus) active path to send address and data-signal, is sending the address on the clock period and send data on the next clock period.Pci bus can be with requiring each other the adapter and/or the system storage of fast access to assemble, and can be visited by the speed of host-processor with the complete local bus speed that approaches processor.The transmission of reading and write via PCI bust utilizes burst transfers of data to realize, described burst transfers of data can adopt beginning the period 1 send the address and the consecutive periods that ascertaining the number subsequently on send data sequence mode send.The length of bursty data is held consultation between promoter and destination apparatus and can be had any length.The architecture of PCI type is implemented widely, and is installed in now on most of desk-top computer.
PCI Express (PCI fast) architecture presents the architecture similar in appearance to PCI, and definite variation is arranged again simultaneously.PCI Express architecture is used switch, and described switch utilization is used for providing the switch of fan-out (fan-out) to replace the multiple spot connecting bus of PCI architecture to I/O (I/O) bus.The fan out capability of switch is convenient to additional high performance I/O is carried out a series of connection.Switch is the logic element that can realize in assembly, and described assembly also comprises host bridge.The PCI switch logically for example can be counted as the set of PCI to the PCI bridge, and one of them bridge is the upstream bridge to one group of additional PCI to the upstream extremity of PCI bridge, and described upstream bridge is connected to special-purpose local bus via its downstream end.
In some cases, wishing can device coupled to each other communicatedly being signaled to such as the information that is used to show synchronous event, such as PCI Express end-point devices.In typical case, this signaling relates to the interruption of a plurality of groupings of request for utilization, other processing that communication process was handled or trended towards slowing down to dealer's unique message.The periodic breaks that these interruptions are usually directed to communicate by letter on the bus, thereby interrupt flow send the data such as writing data.These interruptions trend towards increasing the communication overhead (for example, by increasing the stand-by period and taking communication bandwidth) of synchronization events.
These and other restriction comprises that to utilization the various communication meanss of PCI Express communication means realize that integrated device has proposed challenge.
Summary of the invention
Various aspects of the present invention relate to the communication means that is used for various counting circuits, comprise the counting circuit etc. of communication BUS type structure (for example structure of PCI type) such as those.In a plurality of implementations and the present invention of application illustrated, wherein some have been summarized below.
According to exemplary embodiment of the present invention, information is included in the tag field of the data that communication link is dropped, described data are such as the request msg of dropping.These data of dropping transmit and for example can be used for the signaling synchronous event being coupled between the device of link.Utilize the method, the above-mentioned restriction that is associated with the synchronous event signaling of interruption and other type is reduced and/or has eliminated in typical case, meets any on-the-spot requirement that is associated of using simultaneously fully, such as what require with PCI Express to be realized.
According to another exemplary embodiment of the present invention, be set to " very " value by the tag field that writes request msg of being dropped and come to PCI Express device signaling synchronous event.For example, can utilize the common PCI Express link handle data relevant with synchronous event to send to another PCI Express end-point devices from PCI Express end-point devices according to PCI Express communication means usage flag field, wherein said device can be coupled to described PCI Express link communicatedly.When utilizing writing request msg and realizing of being dropped, the said write request msg does not require response (for example, finishing), can require to realize tag field according to PCI Express, so that the tag field of this request comprises any value.Information in the tag field can stride across that hub passes on switch and is correspondingly compatible mutually with PCIExpress protocol requirement and verifier.
Above summary of the present invention also is not intended to description each embodiment of the present invention or each implementation.Above summary of the present invention also is not intended to description each illustrated embodiment of the present invention or each implementation.Accompanying drawing subsequently and these embodiment that described especially illustration in detail.
Description of drawings
Consider that in conjunction with the accompanying drawings the following detailed description of each embodiment of the present invention can understand the present invention more completely, wherein:
Fig. 1 is the equipment that is used to communicate by letter according to exemplary embodiment of the present invention, described communication relate to and the link device that can be coupled communicatedly between the signaling synchronous event; With
Fig. 2 is according to another exemplary embodiment of the present invention, is used for the process flow diagram of the method for signaling synchronous event between the end points on the PCI Express link.
Embodiment
Though the present invention is obedient to various changes and alternative forms, also will describe in detail it yet show its particular form with way of example in the accompanying drawings.Yet should be appreciated that and be not intended to the present invention is restricted to described specific embodiment.On the contrary, be intended to cover that the institute that falls in the defined scope of the invention of claims changes, equivalent and alternative means.
The present invention is considered to be applicable to various circuit and the method that relates to electronic communication, and is particularly useful for those and relates to the circuit and the method for communicating by letter between the endpoint type device of shared link being coupled to.Though the present invention is not necessarily limited to this application, yet can obtain correct evaluation best to various aspects of the present invention by discussing example in this environment.
According to exemplary embodiment of the present invention, a kind of communication facilities comprises communication link, described communication link has and is suitable for using communication marks (or similar) field to transmit at least two endpoint type devices that (for example, via the tag field that writes data of being dropped) transmits information via communication link.Communication link for example can comprise PCI Express bus, switch and/or other assembly.Utilize the method, can realize tag field communication, utilize other communication (promptly needn't require or not allow to use the communication of described tag field) to make the transmission of selected information be convenient to carry out simultaneously.
In an implementation, said method utilizes PCI Express equipment to realize.Tag field is returned by requester function (Requester function) identification and by finishing device function (Completer function), and in some cases, wherein requester function relates to and do not require that dropping of finishing writes.Requester function realizes that by requester (being used for sequence or logical transition are incorporated into the logical unit in PCI Express territory) the described request device has been realized request or grouping.Finish the device function and realize by finishing device (by the logical unit of requester addressing), the described device of finishing is finished or is divided into groups in response to asking to produce, and termination or part terminator sequence.In the PCI Express that determines uses, wherein finish device to the data in the tag field and insensitive (promptly finish the device function and do not handle described tag field), requester function is used described tag field according to any way, such as being used for the signaling synchronous event.
For about as in conjunction with the more information of the above-mentioned functions that application realized of " adapting " (and other function here) with PCI Express, can be with reference to can be from Oregon, " the PCI Express BaseSpecification Revision 1.0a " that obtains among the PCI-SIG of Portland (PCI special interest groups), in April, 2003.The PCI Express basic norm method that adapts can be considered to " adapting with PCI Express " therewith.
Turn to accompanying drawing now, Fig. 1 shows the communication system 100 of PCIExpress type according to another exemplary embodiment of the present invention, and it is implemented to use the tag field that writes grouping of being dropped to come the transmitting synchronous incident.Though utilize the method for PCI Express type to illustrate and discuss, yet communication system 100 can use other communication type and agreement to realize, no matter be same as PCI Express and be different from PCI Express.
Each end- point devices 150 and 152 is configured to use the tag field of being transmitted on virtual bus 130 that writes grouping of dropping to transmit synchronous event information.For example, when end-point devices 150 transmits information via virtual bus 130 with block form, can utilize the data relevant that tag field in the packet partial is set with synchronous event.Information in end-point devices 152 described groupings of analysis and the usage flag field is determined synchronous event information then.
In an implementation, end-point devices 150 is served as requester dropping to write in the data, and the request that writes is posted to Virtual PC I Express bus 130 with block form.This writes request and is included in " in the mark (tag the in) " signal (for example, one or more bits) that writes in the request header, warns the synchronous event situation to the recipient who writes request.Mark in the data is set up when synchronous event is " very " and works as synchronous event and is not removed (or not being provided with) for true time.
The mark that is used for analyzing end-point devices (for example end-point devices 152) the use data of the request that writes of being dropped identifies synchronous event and adopts suitably to move the sync event signal from end-point devices 150 is responded.Here this end-point devices is served as not and to be finished apparatus (promptly comprise the request of tag field signaling and do not require and finish) to what end-point devices 150 responded.
In some implementation, that is planned drops the recipient that the recipient who writes data needs not to be the sync event signal of being planned.In this, the other end point apparatus of finishing apparatus 152 and/or being coupled to one of downstream port 140-146 can be handled synchronous event data, and different endpoint device processes is dropped the other parts that write data simultaneously.
In another implementation, use adapter to create grouping so that on Virtual PC I Express bus 130, send in response to the request of each end-point devices is next.Each adapter for example can in conjunction be used to produce drop the PCI Express end-point devices that writes or realize at PCIExpress switch 110 places.Each adapter has input and corresponding output (for example, individual bit or reach the extended bit of about 8 bit widths), is used for providing sync event signal in tag field.
In an implementation, the following sync event signal that provides is provided for adapter and input and output signal one.Utilize adapter (for example, dynamic termination logic (dynamictermination logic DTL) target interface) to come at input interface by the address sampled input signal.This input signal (for example, one or more bits) is driven into the highest significant position of tag field in the stem of memory writer command.Provide the address at interface (for example, DTL promoter interface) to output signal (for example, one or more bits) corresponding to input signal.The highest significant position (bit 7 of byte 6) that is used for the tag field that storer writes drives this output signal from the stem of all memory writer commands according to the timing consistent with storage address output timing.Output signal is zero for all other cycles (promptly wherein not carrying out the cycle of signaling synchronous event) and has only when the address and export when effective just effectively.
In some implementation, when PCI Express assembly that is connected to non-user and/or system, forbid synchronous signaling.For example have when dissimilar when end- point devices 150 and 152, wherein utilize non-user's PCI Express assembly and/or system to realize end-point devices 152, forbid signaling from end-point devices 150.This forbids for example using switch or gate type approach to realize.In addition as mentioned above, the method can utilize the manufacturer of compatible end-point devices to use the synchronous event signaling to realize in conjunction with selectivity.
Above-mentionedly can realize for various application and according to variety of way in conjunction with the method for Fig. 1 and other method here.For example, in a further exemplary embodiment, the tag field that writes data of dropping in PCI Express equipment is implemented and defines, thus require to finish each do not finish affairs (requiring the operation of not dropping of response) and have unique mark.These uncompleted affairs are not implemented to transmit synchronous event data in tag field, and adapt with communicating by letter of PCI Express type.When utilizing 8 bit data field to realize, read operation uses four least significant bit (LSB)s (LSB) rather than with four MSB, and utilization " 0 " value realizes in view of the above.Completion logic is configured to ignore the tag field that writes of dropping, and described tag field is being implemented the communication that is used for PCI Express type as mentioned above in typical case.In this, tag field is implemented to utilize drop and writes data (promptly not requiring the data of finishing) and carry out synchronous event communication.
The length of tag field is suitable for specific application, wherein uses PCI Express equipment and further realizes according to available bit.For example, in many PCIExpress implementations, keep 5 bits in typical case for tag field.In other implementation, as discussed in the preceding paragraph, realize tag field (for example when enabling extending marking) with 8 or more bits.
In a further exemplary embodiment, incorporation of markings field sync method is used the JetStream PCI Express core that can obtain from the Perle system of the Nashville of Tennessee State.When realizing the JetStream core, for the cycle that requires to finish, do not use highest significant position (MSB), and whole 8 bit fields are fixed to complete zero so that write.Optionally, realize this 8 bit field for the synchronous event signaling.Can come further differently to realize the method for the different PCI Express of dealer core types.
In more specific exemplary embodiment, be implemented as the type of device that the end-point devices of utilizing tag field to carry out the synchronous event signaling is configured to the incident signaling is restricted to selection.For example when synchronous event will be received by the device that satisfies the particular manufacturer criterion by signaling, code or other recognition methods were implemented to guarantee that the end-point devices that receives sync event signal satisfies described criterion (for example, being made by specific manufacturer).After having satisfied described criterion, code or other recognition methods sign enables the synchronous event signaling.For example when the synchronous event signaling will be carried out for two PCI Express end-point devices with co-manufactured merchant, after having identical manufacturer, definite another PCI Express end-point devices makes a PCI Express end-point devices signaling.
For example use adapter that signal in the mark (for example individual bit or a plurality of bit) is added to tag field, described adapter places the communication stem to described marking signal.When ' synchronous event ' is true time, for example write or frame-synchronizing impulse is a true time when last, signal in this mark is set, optionally identical with any address wire basically mode realizes timing.When realizing synchronous event, outer (tag out) signal (for example, individual bit or a plurality of bit) of mark adds the tag field of communication to so that remove synchronous event information from the added communications that realizes via adapter.Can realize the mark external signal according to the mode that is similar to signal in the above-mentioned realization mark.For example, can use adapter to come from the tag field of stem, to obtain bit, thereby provide and the address output identical time of timing to new signal according to the mode that is similar to from stem extraction address bit.
Fig. 2 shows the process flow diagram that is used for the synchronous event signaling according to another exemplary embodiment of the present invention.At piece 210, write data so that post to PCI Express communication link in PCI Express end-point devices generation.If at piece 220 synchronous events is movable, at piece 230 tag field header that writes data is set so, to show the activity nature of described synchronous event.At piece 240, utilize sync event signal (for example, being used to represent the data of synchronous event) to drop and write data such as " very " bit.If at piece 220 synchronous events is not movable, write data not having under the situation of sync event signal to drop so as an alternative at piece 225.
Drop at piece 250 and to write data accessed (for example, at another PCI Express end-point devices receive).Write data and have sync event signal if drop at piece 260, it is utilized sync event signal and handles at piece 270 so.Write data and do not have sync event signal if drop at piece 260, it is at piece 280 processed (not considering synchronously) so.In some cases, for example when specific synchronous event is applicable to PCI Express end-point devices, handle sync event signal not handling to write under the data conditions, wherein said PCI Express end-point devices may not be that other of being planned dropped the recipient who writes data.
Here the method for being discussed can utilize the equipment and the method for various PCI Express types to realize.In some implementation, the protocol-compliant of the method and PCI Express type, consider for this reason and do not require that the request of finishing (request of dropping), the value in the tag field are not defined and can comprise any value (referring to above-cited PCI Express basic norm revised edition 1.0a).The method further with PCI Express protocol-compliant, described agreement shows that for the request of being dropped the value in the tag field must be able to not influence the processing of receiver to described request; Thereby the market bit of non-zero is legal.In addition, can realize that the method so that tag field do not influence receiver to processing of request.
Only provide each embodiment also illustrated in the accompanying drawings as mentioned above and it should be construed as limiting the invention with exemplary forms.According to above-mentioned argumentation and example, those skilled in the art easily recognize and can carry out various modifications and change to the present invention illustrated in not strictly observing here and under the situation of exemplary embodiment of describing and application.For example, the data except that the synchronous event categorical data can be modified to and use similar approach to transmit.In addition, one or more above-mentioned exemplary embodiments and implementation can utilize various PCIExpress devices and other method to realize, comprise chip and printed circuit board (PCB) (PCB).Above-mentioned exemplary embodiment and implementation can also be integrated with various circuit, device, system and method, comprise those circuit, device, the system and method that use in conjunction with memory storage, display, internet and mobile communication.In addition, each embodiment that is discussed in PCI and PCI Express type application scope can use various devices and communication means to realize, comprises device and communication means that those needn't be applicable to PCI or PCI Express.These methods have been realized in conjunction with each exemplary embodiment of the present invention.This modifications and variations do not break away from below illustrated true spirit of the present invention and scope in the claim.
Claims (20)
1. a PCI Express equipment comprises: PCI Express communication link (110); PCI Express end-point devices (150), can be coupled communicatedly with described PCI Express communication link and be suitable for using the tag field of being transmitted via described PCI Express communication link of dropping data, selected information is sent to another PCI Express end-point devices (152) that can be coupled communicatedly with described PCI Express communication link.
2. equipment as claimed in claim 1, wherein said PCI Express communication link is suitable for using via what described PCI Express communication link was transmitted drops the tag field that writes data, selected information is sent to another PCI Express end-point devices that can be coupled communicatedly with described PCI Express communication link, and wherein selected information comprises asynchronous event information.
3. equipment as claimed in claim 2, wherein said PCI Express end-point devices also are suitable for using to be dropped the tag field that writes data and ad hoc transmits selected information.
4. equipment as claimed in claim 2, wherein said PCI Express end-point devices also are suitable for the unique mark of data allocations that transmitted to via described PCI Express communication link, and wherein said data do not comprise selected information.
5. equipment as claimed in claim 4, wherein said PCI Express end-point devices also is suitable for the unique mark of data allocations that transmitted to via described PCI Express communication link, and wherein said data demand is from the response of another PCI Express end-point devices.
6. equipment as claimed in claim 1, wherein said PCI Express end-point devices also is suitable for using the tag field of the data of dropping ad hoc to transmit information, and the described data of dropping do not require response from another PCI Express end-point devices.
7. equipment as claimed in claim 1, wherein said PCI Express end-point devices are configured and are arranged to use the tag field of being transmitted via described PCI Express communication link of dropping packet to come transmission information.
8. equipment as claimed in claim 1, wherein said PCI Express end-point devices is configured and is arranged to use the tag field in the stem of dropping packet to transmit selected information.
9. equipment as claimed in claim 1, wherein said PCI Express communication link is suitable for using the tag field of being transmitted via described PCI Express communication link of dropping data that selected information is sent to another PCI Express end-point devices, and wherein selected information comprises synchronous event information.
10. equipment as claimed in claim 9, wherein said PCI Express end-point devices are suitable for using described tag field to transmit being used to show that synchronous event is genuine logic " very " signal.
11. equipment as claimed in claim 1, wherein said PCI Express end-point devices are suitable for detecting the characteristic of another PCI Express end-point devices and according to the characteristic that is detected, use described tag field to transmit selected information.
12. equipment as claimed in claim 11, wherein said PCI Express end-point devices are suitable for detecting manufacturer's characteristic of another PCI Express end-point devices and according to the manufacturer's characteristic that is detected, use described tag field to transmit selected information.
13. equipment as claimed in claim 1, wherein said PCI Express end-point devices are suitable for using described tag field to transmit selected information according to the mode that adapts with PCI Express.
14. equipment as claimed in claim 1, also comprise adapter, be configured and be arranged to receive the request that is used for selected information is posted to the PCIExpress communication link from described PCI Express end-point devices, and in response to described request, generation comprises the packet of tag field, and described tag field has the information that is used for selected information is sent to another PCIExpress end-point devices.
15. a PCI Express system comprises: PCI Express communication link; At least two PCI Express end-point devices that can be coupled communicatedly with described PCI Express communication link; In at least two PCI Express end-point devices first is suitable for synchronous event information is included in the tag field that writes data that described PCI Express communication link is dropped, and that is dropped writes data and do not require the response of finishing from another PCI Express end-point devices; And at least two PCI Express end-point devices second is suitable for receiving and handle the synchronous event information in the described tag field.
16. system as claimed in claim 15, wherein said PCI Express communication link comprises PCI Express switch.
17. system as claimed in claim 16, wherein said PCI Express switch comprises: Virtual PC I Express bus; The upstream port of the switch that can be coupled communicatedly with described PCI Express bus; A plurality of downstream ports with the switch that can be coupled communicatedly with described PCI Express bus, first of the downstream port of switch is coupled to a described PCI Express end-point devices, and second of the downstream port of switch is coupled to described the 2nd PCI Express end-point devices.
18. method that is used for the information that transmits at PCI Express equipment, described PCIExpress equipment comprises the PCIExpress end-point devices that can be coupled to PCI Express communication link communicatedly, and described method comprises: use the tag field of being transmitted via described PCI Express communication link of dropping data that selected information is sent to another PCI Express end-point devices that can be coupled communicatedly with described PCI Express communication link.
19. method as claimed in claim 18 is wherein used the tag field of the data of being transmitted via described PCI Express communication link to come that selected information is sent to another PCI Express end-point devices that can be coupled communicatedly with described PCI Express communication link and is comprised: use and do not require that finishing the tag field that dropping of response write data transmits selected information.
20. method as claimed in claim 19 wherein is sent to another PCI Express end-point devices to selected information and comprises: use the described tag field that writes data of dropping that synchronous event data is sent to another PCI Express end-point devices.
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US55450404P | 2004-03-19 | 2004-03-19 | |
| US60/554,504 | 2004-03-19 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN1934558A true CN1934558A (en) | 2007-03-21 |
Family
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Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CNA2005800087305A Pending CN1934558A (en) | 2004-03-19 | 2005-03-19 | Signaling arrangement and approach therefor |
Country Status (5)
| Country | Link |
|---|---|
| EP (1) | EP1728170A2 (en) |
| JP (1) | JP2007529815A (en) |
| KR (1) | KR20060130664A (en) |
| CN (1) | CN1934558A (en) |
| WO (1) | WO2005091156A2 (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102341797A (en) * | 2009-06-02 | 2012-02-01 | 国际商业机器公司 | Detecting lost and out of order posted write packets in a peripheral component interconnect (PCI) express network |
| CN114207382A (en) * | 2019-07-31 | 2022-03-18 | 西门子股份公司 | Signaling device |
Families Citing this family (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP5057548B2 (en) * | 2006-05-02 | 2012-10-24 | 株式会社リコー | Image data transfer apparatus and image data transfer method |
| US7702827B2 (en) | 2007-06-29 | 2010-04-20 | International Business Machines Corporation | System and method for a credit based flow device that utilizes PCI express packets having modified headers wherein ID fields includes non-ID data |
| US8139575B2 (en) | 2007-06-29 | 2012-03-20 | International Business Machines Corporation | Device, system and method of modification of PCI express packet digest |
| JP5151567B2 (en) * | 2008-03-07 | 2013-02-27 | 日本電気株式会社 | Method and system for avoiding deadlock in data communication system and control program therefor |
| JPWO2015155997A1 (en) * | 2014-04-11 | 2017-04-27 | 日本電気株式会社 | Setting device, control device, setting method, and network switch |
Family Cites Families (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5751723A (en) * | 1996-07-01 | 1998-05-12 | Motorola, Inc. | Method and system for overhead bandwidth recovery in a packetized network |
| US7120722B2 (en) * | 2002-05-14 | 2006-10-10 | Intel Corporation | Using information provided through tag space |
-
2005
- 2005-03-19 CN CNA2005800087305A patent/CN1934558A/en active Pending
- 2005-03-19 EP EP05718562A patent/EP1728170A2/en not_active Withdrawn
- 2005-03-19 KR KR1020067019311A patent/KR20060130664A/en not_active Application Discontinuation
- 2005-03-19 WO PCT/IB2005/051031 patent/WO2005091156A2/en not_active Application Discontinuation
- 2005-03-19 JP JP2007503488A patent/JP2007529815A/en not_active Withdrawn
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102341797A (en) * | 2009-06-02 | 2012-02-01 | 国际商业机器公司 | Detecting lost and out of order posted write packets in a peripheral component interconnect (PCI) express network |
| CN102341797B (en) * | 2009-06-02 | 2014-07-23 | 国际商业机器公司 | Detecting lost and out of order posted write packets in a peripheral component interconnect (PCI) express network |
| CN114207382A (en) * | 2019-07-31 | 2022-03-18 | 西门子股份公司 | Signaling device |
| CN114207382B (en) * | 2019-07-31 | 2024-01-02 | 西门子股份公司 | Signalling device |
| US12018961B2 (en) | 2019-07-31 | 2024-06-25 | Siemens Aktiengesellschaft | Signaling device |
Also Published As
| Publication number | Publication date |
|---|---|
| JP2007529815A (en) | 2007-10-25 |
| EP1728170A2 (en) | 2006-12-06 |
| WO2005091156A2 (en) | 2005-09-29 |
| WO2005091156A3 (en) | 2006-03-02 |
| KR20060130664A (en) | 2006-12-19 |
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