CN1933018A - Memory system and method having point-to-point link - Google Patents
Memory system and method having point-to-point link Download PDFInfo
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- CN1933018A CN1933018A CNA2006101536308A CN200610153630A CN1933018A CN 1933018 A CN1933018 A CN 1933018A CN A2006101536308 A CNA2006101536308 A CN A2006101536308A CN 200610153630 A CN200610153630 A CN 200610153630A CN 1933018 A CN1933018 A CN 1933018A
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/14—Handling requests for interconnection or transfer
- G06F13/16—Handling requests for interconnection or transfer for access to memory bus
- G06F13/1668—Details of memory controller
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
- G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
- G11C7/1075—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers for multiport memories each having random access ports and serial ports, e.g. video RAM
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Abstract
A memory system includes a controller for generating a control signal and a primary memory for receiving the control signal from the controller. A secondary memory is coupled to the primary memory, the secondary memory being adapted to receive the control signal from the primary memory. The control signal defines a background operation to be performed by one of the primary and secondary memories and a foreground operation to be performed by the other of the primary and secondary memories. The primary memory and the secondary memory are connected by a point-to-point link. At least one of the links between the primary and secondary memories can be an at least partially serialized link. At least one of the primary and secondary memories can include an on-board internal cache memory.
Description
Technical field
The present invention relates to accumulator system, more specifically, relate to a kind of accumulator system that between storer, has point-to-point link, and a kind of accumulator system that can synchronously carry out prospect (foreground) and background (background) operation.
Background technology
Fig. 1 comprises the schematic block diagram of graphic extension memory module 10, and Fig. 2 comprises the schematic block diagram of graphic extension accumulator system 100, and this accumulator system 100 comprises the memory module 10 of a plurality of Fig. 1.With reference to figure 1, memory module 10 comprises a plurality of memory unit M1-M8.Eight memory unit M1-M8 are shown and share common command/address (CA) signal wire 12 that connects from the main frame (not shown).This sharing of public CA line is meant multiple spot (multi-drop) link.Usually, eight or four shared public CA lines of memory units.
Among the memory unit M1-M8 each also receives many parallel datas (DQ) signal wire 14.In the memory module of Fig. 1, each memory unit receives eight DQ (X8) line 14.In legacy memory module 10, every DQ signal wire 14 is connected to memory member by point-to-point link from the main frame (not shown).
As shown in Figure 2, conventional memory systems 100 comprises a plurality of memory modules 210,220 of memory module shown in Figure 1 10 types etc.Memory module 210,220 is connected with main frame 200 and communicates.Memory module 210 comprise a plurality of memory member M11, M12 ..., M1N, memory module 220 comprise a plurality of memory member M21, M22 ..., M2N.CA signal wire 212 by multiple spot link be connected to memory member M11, M12 in the memory module 210 ..., M1N.CA signal wire 222 by the link of another multiple spot be connected to memory member M21, M22 in the memory module 220 ..., M2N.Many parallel DQ signal wire 214-1 is connected to memory member M11 and M21 by the multiple spot link.Many parallel DQ signal wire 214-2 is connected to memory member M12 and M22 by the multiple spot link.Many parallel DQ signal wire 214-N is connected to memory member M1N and M2N by the multiple spot link.
Typical high-density storage system comprises a plurality of memory modules as shown in Figure 2.The DQ signal wire has the multiple spot link, and therefore a plurality of memory member M share public DQ line.The operating speed of the load meeting negative effect accumulator system 100 of the DQ line that the multiple spot link causes.For example, eight SDRAM or four double data rate (DDR) storeies or two DDR2 or DDR3 storer can all couple together by wall scroll DQ line.The capacity load that reduces to be caused by the link of the multiple spot of CA and DQ line is important to the operating speed that improves accumulator system 100.
Summary of the invention
According to the present invention, in the high-speed memory system, for example, in the accumulator system that is equal to or greater than 2GHz bps operation, point-to-point (PTP) link is used for all signal wires between Memory Controller (main frame) and the single memory parts, promptly, CA and DQ signal wire.The PTP link has reduced the cutting back (stub) of capacity load and every signal line.
For the high-density storage system, use a plurality of memory modules.Each accumulator system with PTP link comprises the I/O tap that is used for every signal line.This can cause the quantity of module tap to increase so that hold the PTP link.According to the present invention, in the high-density storage system that supports the PTP link, avoid the increase of module tap (tab) by the memory member that uses the flat memory parts on the single memory module or pile up (stacked).As a result, accumulator system can only have the single memory module.According to the present invention, a plurality of memory members on the single memory module have the PTP link between them, so that can carry out high speed operation.
According to first aspect, the invention provides a kind of accumulator system.This accumulator system comprises: controller is used to generate control signal; Primary memory is used to receive the control signal of self-controller; With the secondary store that is couple to primary memory, this secondary memory being adapted receives the control signal of autonomous memory.Control signal limits and will and will be operated by the prospect of another execution in the secondary store of advocating peace by the background operation of an execution in the secondary store of advocating peace.
In one embodiment, when the target output port of one of the secondary store of advocating peace was not operated, background operation was by an execution in the secondary store of advocating peace.Background operation can be one of power operation, precharge operation and self refresh operation.
In one embodiment, when one of prospect and background operation are read operation, in the data of controller place reception from secondary store.Data from secondary store can be sent to controller by primary memory.
Primary memory and be that in the secondary store each can be the DRAM storer.
Between controller and the primary memory be connected and primary memory and secondary store between to be connected can be differential connection or single-ended connection.
Primary memory and secondary store can be linked by point-to-point link.
According on the other hand, the invention provides a kind of accumulator system, comprising: controller; Be couple to the primary memory of controller, thereby between primary memory and controller, can use first signal transfer protocol to transmit signal; With the secondary store that is couple to primary memory, thereby between primary memory and secondary store, can use the secondary signal host-host protocol to transmit signal, the first and second signal transfer protocol differences.
In one embodiment, first signal transfer protocol basic synchronization ground transmission, first number of bits, and secondary signal host-host protocol basic synchronization ground transmission second number of bits, the first and second quantity differences.
In one embodiment, the secondary signal host-host protocol is the partial continuous version of first signal transfer protocol at least.
Primary memory and be that in the secondary store each can be the DRAM storer.
Between controller and the primary memory be connected and primary memory and secondary store between to be connected can be differential connection or single-ended connection.
Primary memory and secondary store can be linked by point-to-point link.
According on the other hand, the invention provides a kind of accumulator system, comprising: controller is used to generate control signal; Primary memory is used to receive the control signal of self-controller; With the secondary store that is couple to primary memory, primary memory and secondary store are linked by point-to-point link; With the cache memory that is couple to primary memory, this cache memory is configured to store the information from secondary store.
Cache memory can be in the inside of primary memory and/or secondary store.
Primary memory and be that in the secondary store each can be the DRAM storer.
Between controller and the primary memory be connected and primary memory and secondary store between to be connected can be differential connection or single-ended connection.
Description of drawings
By the more specifically description of the preferred aspect of the present invention shown in the accompanying drawing, of the present invention above and other aspects, feature and advantage will be more obvious, whole accompanying drawing, identical referenced drawings indicia point components identical.Accompanying drawing needn't be drawn in proportion, but emphasizes graphic extension principle of the present invention.In the accompanying drawing, amplified the thickness in floor and district in order to know.
Fig. 1 comprises the schematic block diagram of graphic extension legacy memory module.
Fig. 2 comprises the schematic block diagram of graphic extension conventional memory systems, and this conventional memory systems comprises the memory module of a plurality of Fig. 1.
Fig. 3 A-3C is the synoptic diagram that functional graphic extension has the accumulator system 250 of PTP link structure.
Fig. 4 is the schematic block diagram of graphic extension according to the embodiment of accumulator system of the present invention.
Fig. 5-7 comprises the schematic block diagram according to three kinds of structures of the accumulator system of Fig. 4 of the embodiment of the invention.
Fig. 8 A is the schematic block diagram of master (P) storer according to the embodiment of the invention.
Fig. 8 B is the detailed schematic block diagram of internal circuit of the primary memory of Fig. 8 A.
Fig. 9 comprises graphic extension according to the download of embodiment of the invention grouping with upload the sequential chart of the processing of grouping.
Figure 10 comprises the schematic illustrations according to the download C/A grouping of the embodiment of the invention.
Figure 11 comprises the value qualified list according to the CS0-CS1 field of the embodiment of the invention.
Figure 12 comprises the value qualified list according to the RS0-RS2 field of the embodiment of the invention.
Figure 13 comprises according to the identification prospect of the embodiment of the invention and the table of background operation.
Figure 14 comprises the schematic block diagram according to the accumulator system of the embodiment of the invention.
Figure 15 comprises the table of graphic extension according to the example of the C/A packet command of the embodiment of the invention.
Figure 16 comprises the table of graphic extension according to another example of the C/A packet command of the embodiment of the invention.
Figure 17 comprises the sequential chart of graphic extension in conjunction with the operation of the example command execution of Figure 16 description.
Figure 18 comprises the table of graphic extension according to the command packet form of memory write order of the present invention.
Figure 19 comprises the table of graphic extension according to the form of the packet after the write order grouping of Figure 18 of the present invention.
Figure 20-22 comprises the schematic block diagram of accumulator system according to another embodiment of the present invention.
Figure 23 is the schematic block diagram of the main memory system shown in Figure 20-22 according to the embodiment of the invention.
Figure 24 A and 24B comprise the table of the form of the serialized according to an embodiment of the invention example WR/CA signal of expression.
Figure 25-28 comprises the schematic block diagram of each embodiment of the accumulator system of wherein using serialization of the present invention and background and prospect operation.
Figure 29 comprises the table of serialization command packet that graphic extension can be applicable to the accumulator system of Figure 27 and 28.
Figure 30 comprises the schematic block diagram of accumulator system according to another embodiment of the present invention.
Figure 31 is the schematic block diagram according to the primary memory shown in Figure 30 of the embodiment of the invention.
The schematic block diagram that Figure 32 comprises according to another embodiment of the present invention, wherein primary memory and secondary store comprise the accumulator system of high-speed buffer.
Figure 33 is the graphic extension schematic block diagram of accumulator system according to another embodiment of the present invention.
Embodiment
Fig. 3 A-3C is the synoptic diagram that functional graphic extension has the accumulator system 250 of PTP link structure.The accumulator system of Fig. 3 A and 3B comprises main memory section 252 and secondary store parts 254.Main frame or controller 266 will be ordered with data and send to primary memory 252 and secondary store 254 when execution of program instructions, and receive order and data from primary memory 252 and secondary store 254.
Fig. 3 A schematic illustration the situation of main memory section 252 controlled devices 266 accesses wherein.Dotted line 258 illustrates and comprises by the read command that comes autonomous memory of system 250 and the signal flow of read data.Fig. 3 B illustrates the wherein situation of secondary store parts 254 controlled devices 266 accesses.Dotted line 268 illustrate comprise by system 250 from the read command of secondary store and the signal flow of read data.Fig. 3 C is the table of operation that is illustrated in the accumulator system 250 of situation figure below 3A of main memory section 252 and 266 accesses of secondary store parts 254 controlled devices and 3B.Shown in Fig. 3 A and 3C, when carrying out the primary memory Writing/Reading, the secondary store state is " standby ", and just, when controller 266 visit primary memorys 252, secondary store 254 is not carried out any operation.When carrying out the primary memory Writing/Reading, primary memory 252 is in effective status, and just, primary memory 252 is effectively to carry out institute's requested operation.Shown in Fig. 3 B and 3C, when carrying out the secondary store Writing/Reading, the secondary store state is effectively to carry out institute's requested operation.During the secondary store Writing/Reading, primary memory 252 is in " transmission " state, mean that primary memory 252 only repeats (transmissions) WR/CA information to secondary store 254 along line 260, and along line 264 repeat or delay from secondary store 254 to controller 266 read data.Memory member with PTP link use efficient and total line use ratio of accumulator system 250 of this classic method shown in Fig. 3 A-3C lower, because only can respond the individual command that sends to main or secondary store parts and operate.
Use method of the present invention to eliminate this poor efficiency.According to the present invention, when Memory Controller from one of storer of constituting the PTP link read/or when writing wherein, other storeies are carried out some operation that can not influence the memory bus that memory bus/slave controller of being connected to controller connects synchronously.Use the packet oriented protocol of two operations of identification (being referred to herein as first operation or " prospect " operation and second operation or " background " operation) can carry out two synchronous operations.Therefore, the invention provides accumulator system and the method for using the PTP link structure to raise the efficiency.
According to some embodiment of the present invention, I/O (IO) agreement between Memory Controller and the primary memory and interface link I/O (IO) agreement and the interface that are different between the memory member and link.Particularly, in these embodiments, except all storeies of primary memory have serial line interface, thereby the signal route between the storer can be easier, and the grouping size can be littler than the grouping size of using conventional P TP link situation.
According to some embodiment of the present invention, primary memory can comprise the inner high speed impact damper, and being used to save expectation will be by controller from the secondary store read data of frequent access more.According to these embodiment, because primary memory is more accessed more continually than secondary store, therefore, high-speed buffer is arranged in main dram.In high-speed buffer, select the also content of the auxilliary DRAM of more pre-aligned frequent access in advance.This causes throughput of system to increase.
Fig. 4 is the schematic block diagram of graphic extension according to the embodiment of accumulator system 350 of the present invention.The accumulator system 350 of Fig. 4 comprises memory module 320 and Memory Controller or is used for main frame 366 that signal and data are sent to memory module 320 and therefrom transmit signal and data.Main frame 366 is connected to memory module 320 by four channel C H0-CH3 of external bus OBUS.External bus OBUS comprises the download bus (DLB) that transmits command signal, address signal, write clock signal and/or write data signal.External bus OBUS also comprise transmit read data and read clock signal upload bus (ULB).Externally on the bus OBUS, transmit all signals by PTP link non-directional ground.
Memory module 320 comprises master (P) storer 322 and auxilliary (S) storer 324 that is used for each channel C H0-CH3.Primary memory 322 is directly connected to main frame 366 by external bus OBUS.Secondary store 324 is connected to each autonomous memory 322 by internal bus IBUS.Primary memory 322 is known as the RANK0 storer, and secondary store is known as the RANK1 storer.Reference clock CLK_Ref is provided to each storer 322,324.
Fig. 5-7 comprises the schematic block diagram according to three kinds of structures of the accumulator system of Fig. 4 of the embodiment of the invention.With reference to figure 5, accumulator system 350a is included in last master (P) storer 322 that connects of top side 325a of printed circuit board (PCB) or motherboard 325 and auxilliary (S) storer 324 that connects on the bottom side 325b of printed circuit board (PCB) or motherboard 325. Storer 322 and 324 is connected to motherboard 325 via a plurality of electric conductivity pins or projection (bump) 329.Primary memory 322 is connected to secondary store 324 by electric conductivity pin or the projection 329 of carrying IBUS.Primary memory 322 is connected to main frame 366 by OBUS.
With reference to figure 6, the top side 327a that accumulator system 350b is included in printed circuit board (PCB) or motherboard 327 goes up master (P) storer 322 and auxilliary (S) storer 324 that connects. Storer 322 and 324 is connected to motherboard 327 via a plurality of electric conductivity pins or projection 329.Primary memory 322 is connected to secondary store 324 by IBUS.Primary memory 322 is connected to main frame 366 by OBUS.
With reference to figure 7, accumulator system 350c comprises master (P) storer 322 and auxilliary (S) storer 324 of a side 331a who is connected to printed circuit board (PCB) or motherboard 331.Primary memory 322 is directly connected to printed circuit board (PCB) or motherboard 331 via a plurality of electric conductivity pins or projection 329.Secondary store 324 is stacked on the top of primary memory 322 and is connected to printed circuit board (PCB) or motherboard 331 by a plurality of electric conductivity pins or protruding 329 via primary memory 322.Perhaps, primary memory 322 can be two the separation moulds (die) that are integrated into the single encapsulation (package) that is connected with printed circuit board (PCB) or motherboard 331 with secondary store.Primary memory 322 is connected to secondary store 324 by electric conductivity pin or the projection 329 of carrying IBUS.Primary memory 322 is connected to main frame 366 by OBUS.
Fig. 8 A is the schematic block diagram of master (P) storer 322 according to the embodiment of the invention.Fig. 8 B is the detailed schematic block diagram of internal circuit of the primary memory 322 of Fig. 8 A.With reference to figure 8A, primary memory 322 comprises four input/output end ports, is used for order and data are sent to controller and secondary store 324 and slave controller and secondary store 324 reception order and data.The port 354 that is labeled as RFC comes the receiving port of self-controller, and it receives the signal that comprises order and write data from main frame or controller 366.The port 351 that is labeled as RFD is the receiving ports from storer, and it is from the signal of other storeies receptions such as reading data signal such as secondary store 324.The port 355 that is labeled as TTD is the transmit ports to storer, and it sends signal to other storeies such as secondary store 324.The port 356 that is labeled as TTC is the transmit ports to controller, and it will comprise that the signal of read data sends to controller or main frame 366.
With reference to figure 8B, storer 322 comprises and is used for realizing circuit of the present invention and the traditional circuit that uses at memory member.Storer 322 comprises the n * m memory array 360 that is connected to sensor amplifier 361.Sensor amplifier 362 is connected to data buffer 362, and this data buffer 362 is connected to output buffer 368 successively.Row decoder 358 and column decoder 363 are used to the storage address in the decoding storage array 360 in a conventional manner.Be read out amplifier 361 from the data of memory array and read (sense) and be sent to output buffer 368, the data that this output buffer 368 transmits from storer 322 via TTC port 356 by data buffer 362.The WR/CA signal that command decoder and input buffer 357 receive from main frame 366 via RFC port 354.Order is by command decoder and input buffer 357 decodings.Storer 322 also will be ordered by the TTD port via duplicator 369 and the write data slave controller repeats to secondary store 324.
For the main memory access order, command decoder and input buffer 357 are sent to row decoder 358 and column buffer 365 with address information.Column buffer 365, column decoder 363 and row decoder 358 be decode address information and memory array 360 carried out access in a conventional manner.Writing under the situation of processing, data input register 359 receives the input data and it is delivered to addressed memory array 360 from command decoder and input buffer 357.Under the situation of read operation, from memory array 360 reading of data and by data buffer 362 data are delivered to output buffer 368 from sensor amplifier 361, and read from storer 322 by TTC port 356.
For ordering the processing that will be repeated secondary store 324, via RFC port 354, at command decoder and input buffer 357 places reception WR/CA signal.Along line 371 the WR/CA signal is outputed to duplicator circuit 369 from command decoder and input buffer 357.And, for the data that repeat the secondary store in the autonomous memory, receive read data at the RFD port, by the read data input buffer read data is sent to output buffer then.As a result, will be sent to controller from the read data of secondary store via the TTC port.On online 377 repeat control signal is sent to duplicator 369 and is sent to read data input buffer 353 from mode register 367.
As the part of this re-treatment, mode register can be determined whether enabling duplicator and read data input buffer by MRS (mode register setting) operation setting.If memory member is used as primary memory, then duplicator and read data input buffer are enabled by the repeat control signal from mode register output.If memory member is used as secondary store, then duplicator and read data input buffer are not enabled by the repeat control signal from mode register output.Perhaps, for re-treatment, duplicator and read data input buffer can be controlled by the identifying information of the position of expression storer in the PTP link structure.
The read data that reads from secondary store by primary memory 322 or situation about being postponed by primary memory 322 under, at RFD port 351 places, receive read datas from secondary store 324.On the read data input buffer 353 online 373 read data RD is sent to output buffer 368.
It can be the memory member of primary memory and secondary store that Fig. 8 A and 8B illustrate respectively, decides by MRS operation to enable duplicator and the read data input buffer comes repetition WR/CA and read data.And, if storer is used as primary memory, always then WR/CA is repeated, and no matter decoding WR/CA.That is to say that primary memory receives WR/CA, and be not after decoding WR/CA, it to be repeated to secondary store.
Fig. 9 comprises graphic extension according to the download of embodiment of the invention grouping with upload the sequential chart of the processing of grouping.Download grouping and can be and comprise from the main frame to the primary memory or to the order of secondary store and the grouping of write data.Upload grouping and can be the grouping that comprises from primary memory or secondary store to the read data of main frame.Download grouping and comprise two unit groupings, when write operation is represented in the order of carrying out, comprise C/A signal or C/A signal and write data WR.Upload grouping and comprise two read data RD unit groupings.The size of unit grouping is determined by comprising how many positions in the one-period of CLK_ref signal.Write clock WCLK and be used to control the processing sequential of downloading grouping, read clock RCLK and be used to control the processing sequential of uploading grouping.
Figure 10 comprises the schematic illustrations according to the download C/A grouping of the embodiment of the invention.According to the present invention, download the C/A grouping and comprise first order that to be carried out by one of the secondary store of being advocated peace and will be by another second order carried out synchronously in the secondary store of advocating peace.First order is meant the prospect order at this, and second order is meant background command at this.Hierarchical structure, priority or the classification of any type of ordering do not advised in this term.Selected term, that is, prospect and background are used for simplifying and are easy to and describe.
The C/A that comprises prospect operation and background operation that Figure 10 comprises according to the embodiment of the invention downloads the schematic illustrations of grouping.In this particular illustration explanation, to Pin7, transmit eight ten words at eight pin Pin0.Position B1-B5 is used for the prospect operation, and position B6-B10 is used for background operation.During first semiperiod of reference clock CLK_ref, transmit the position that is used for the prospect operation, and during second semiperiod of reference clock CLK_ref, transmit the position that is used for background operation.
With reference to Figure 10, the position B1 of pin Pin0-Pin3 limits four bit field FOP3-FOP0, is used to discern the prospect operation with being performed.The position B6 of pin Pin0-Pin3 limits four bit field BOP3-BOP0, is used to discern the background operation with being performed.The background operation that prospect operation that field FOP3-FOP0 limits and field BOP3-BOP0 limit is identified in Figure 13, and Figure 13 comprises according to the identification prospect of the embodiment of the invention and the table of background operation.Should be noted that from Figure 13 the cache memory enable command is included as one of prospect order.The cache memory enable command is meant the use of the cache memory that comprises in the primary memory.To be explained in more detail this below.
The position B1 identification prospect FEXIT order of Pin4, and the position B6 identification background BEXIT order of Pin4.These orders are not relate to the type that reads or writes storage access.In FEXIT or BEXIT order, when the position was effective, storer existed its previous outage or self-refresh state.
The position B1 of pin Pin6 and Pin7 limits two bit field CS0-CS1, is used to discern which memory column (rank), and promptly one of primary memory or a plurality of secondary stores will the execution prospect be operated.Figure 11 comprises the table according to the qualification of CS0-CS 1 field value of the embodiment of the invention.
The position B6 of pin Pin5-Pin7 limits three bit field RS0-RS2, is used to discern which memory column and will carries out background operation.Figure 12 comprises the table according to the qualification of the RS0-RS2 field value of the embodiment of the invention.
With reference to Figure 10, remaining bit is used to limit the storage address A0-A14 and the B0-B4 of memory access command at this.Should be noted that herein that the term " RFU " that uses is meant to using in the future keeps.
Figure 14 comprises the schematic block diagram according to the accumulator system 350d of the embodiment of the invention.The 350d of normal memory system comprises primary memory 322 (referring to RANK0), and it is connected to controller or main frame 366.The first secondary store 324a is connected to primary memory 322, the second secondary store 324b and is connected to the first secondary store 324a.This embodiment of the present invention illustrates the present invention and can be applicable to the accumulator system that has primary memory 322 and have the secondary store 324 of any amount at RANK1,2,3... at RANK0.
Figure 15 comprises the table of graphic extension according to the example of the C/A packet command of the embodiment of the invention.With reference to Figure 10,11,12,13,14 and 15, the order of Figure 15 illustrates and wherein carries out the sample situation that reading of RANK1 storer 324a carried out other two row (that is, RANK0 storer 322 and RANK2 storer 326a) outages simultaneously.CS0/CS1 field with value 10 represents that RANK1 storer 324a will the operation of execution prospect.RS0/1/2 field with value 101 represents that RANKO storer 322 and RANK2 storer 326a will carry out background operation.FOP0-FOP3 field with value 0100 represents that the prospect operation that RANK1 storer 324a carries out is the READ operation.BOP0-BOP3 with value 0001 represents that the background operation that RANK0 storer 322 and RANK2 storer 326a carry out is a power operation.
When RANK0 storer 322 received the C/A packet command, whether its decoding CS0/CS1 and RS0/1/2 field should work by operation of execution prospect or background operation so that determine it.This situation is used for RANK0 storer 322 background operations, and RANK0 storer 322 enters power-down mode.And the RANK0 storer is to the order of RANK1 storer 324a repeated packets.
When RANK1 storer 324a received C/A packet command from RANK0 storer 322, whether its decoding CS0/CS1 and RS0/1/2 field should work by operation of execution prospect or background operation so that determine it.This situation is used for RANK1 storer 324a background operation, and RANK1 storer 324a reads its memory cell data by the address information appointment in the C/A packet command.RANK1 storer 324a repeats the C/A packet command to RANK2 storer 326a.When RANK2 storer 326a received command packet, it responded in the mode identical with 322 responses of RANK0 storer, except it does not repeat the C/A packet command, because it is in the top column of storer.
After stand-by period, RANK1 storer 324a outputs to the RANK0 storer with read data at the CAS that is similar to 10ns.Be in outage even should be noted that RANK0, the transmission of its receiving port RFD and duplicator or driving port TTC still are switched on so that read data is sent to controller 366.
Figure 16 comprises the table of graphic extension according to another example of the C/A packet command of the embodiment of the invention.The order of Figure 16 illustrates the sample situation of reading of wherein carrying out RANK0 and RANK1 with the individual command grouping continuously.In this sample situation, RANK0 receives packet command and decoding CS0/CS1 and RS0/1/2 field, so that determine whether to carry out background or prospect operation.This situation is used for the operation of RANK0 prospect, and RANK0 uses prospect operation address information to read suitable read data R0.It is also to the order of RANK1 repeated packets.
When RANK1 received command packet from RANK0, whether its decoding CS0/CS1 and RS0/1/2 field carried out background operation or prospect operation so that determine it.In this case, RANK1 will carry out background operation, and it reads the suitable memory cell read data R1 by the appointment of background operation address.It also divides into groups to the RANK2 iterated command.
Not respond packet order of RANK2 is because CS0/CS1 and RSO/1/2 field nonrecognition RANK2.After stand-by period, RANK1 outputs to RANK0 with read data R1 at the CAS that is similar to 10ns.Afterwards, memory data is sent to controller 366 to postpone (two times the repeater delay) at twice duplicator.
Figure 17 comprises above the graphic extension sequential chart of the operation that the example command just described in conjunction with Fig. 16 carries out.Notice that the digital 1-5 in the sequential chart of Figure 17 in the circle is corresponding to the same numbers of mark on the block scheme of the accumulator system 350d among Figure 14.With reference to Figure 14 and 17, show controller 366 and receive R0 and R1 data continuously from primary memory.Therefore, for individual command, accessing main memory and secondary store.
Figure 18 comprises the table of graphic extension according to the command packet form of memory write order of the present invention.Figure 19 comprises the table of graphic extension according to the form of the packet after the write order grouping of Figure 18 of the present invention.With reference to Figure 18, notice that write order does not have background operation in this embodiment.The storer of FOP field identification by access to write data designated.With reference to Figure 19, the data packet format hypothesis writes 64 data in the single clock period.The packet of Figure 19 can be just after the write order grouping of Figure 18.
Figure 20-22 comprises the schematic block diagram of accumulator system 450 according to another embodiment of the present invention.The system 450 of Figure 20-22 comprises master (P) storer 422 and one or more auxilliary (S) storer 424 that is connected to primary memory 422 that is connected to main frame or controller 466.In this embodiment, interface between main frame 466 and the primary memory 422 and agreement are different from the interface and the agreement of advocating peace between the secondary store.Particularly, RANK0 primary memory 422 is that serialization links SB with interface between the RANK1 secondary store 424.On the contrary, linking between main frame 466 and the primary memory 422 is parallel link (PB).As shown in figure 20, link PB can comprise quantity X bar line, and the link SB between the storer can comprise quantity Y bar line, and wherein X is different with Y.Just, X can be N or M bar line, and Y can be K or L bar line.The line that there is shown these quantity in Figure 21 and 22.For example, N=8, M=8, K=4 and L=4.In this embodiment, the storer beyond the primary memory can have than primary memory pin still less.The difficulty of this signal route between can minimizing memory also can be avoided the increase of the package dimension of more secondary stores.In addition, the serial link between the storer provides better signal integrity by the noise source that minimizes between the adjacent signals.Just, reduced crosstalking between the signal wire.
The top description of the embodiment of the invention also is applicable to the embodiment shown in Figure 20-22.Just, the use of being carried out by prospect in a plurality of storeies of individual command startup and background operation can be applicable to the embodiment of Figure 20-22.For example, as shown in figure 21, can the execution prospect operate, can carry out background operation by secondary store 424 (dotted line 429) simultaneously by primary memory 422 (dotted line 427).As shown in figure 22, for example, can carry out prospect or background operation by secondary store 424 (dotted line 431).
Figure 23 is the schematic block diagram of the main memory system 422 shown in Figure 20-22 according to the embodiment of the invention.The element of block scheme of Figure 23 of element that is similar to Fig. 8 B on the function is with identical Reference numeral mark.The detailed description of these elements will no longer be repeated.
The block scheme of Figure 23 comprises and being used for the serializer circuit 413 repetition WR/CA signals of secondary store and the deserializing circuit 415 that is used for read data is repeated to from secondary store main frame 466.
Read data (xL) is received by read port RFD 451 and is passed to read data input buffer 453, on this read data input buffer 453 online 473 read data RD is sent to deserializer 415.Under control from the repeat control signal of mode register 467, deserializer 415 deserializing read datas, and the read data of deserializing is delivered to output buffer 468, it is passed to deserializer 415 on online 477.Under the control from the control signal of stand-by period and BL circuit 364 on online 475, output buffer 468 is selected the read data of deserializings from deserializer 415, so that send out the data as xM by TTC port 456 from storer 422.
Sentence the xN form at RFC port 454 and receive the WR/CA signal.By command decoder and the input buffer 357 WR/CA signal of decoding.When secondary store was repeated the WR/CA signal, the repeat control signal that mode register 467 suitably is provided with on the line 477 was set to appropriate value.The WR/CA signal is passed to serialiser 413, and 413 pairs of WR/CA signals of serialiser carry out serialization.Under the control of repeat control signal 477, serialiser is delivered to duplicator 469 with serialized WR/CA signal then.Duplicator is delivered to the TTD port with serialized WR/CA signal, and this TTD port is sent to secondary store with the xK form with serialized WR/CA signal.For example, in this exemplary embodiment, N=8, K=4, L=4 and M=8.
Enable serialiser 413, be used for the duplicator 469 of repetition WR/CA and be used for the deserializer 415 of duplicate reading certificate by the MRS operation according to the position of PTP link structure.If storer is used as the storer beyond the PTP link structure top, then enable serialiser 413, duplicator 469 and deserializer 415 by repeat control signal from mode register output.If storer is used as PTP link structure top, then do not enable serialiser 413, duplicator 469 and deserializer 415 by repeat control signal.Repeat control signal also is applied to read data input buffer 453.
Figure 24 A and 24B comprise the table of the form of the serialized according to an embodiment of the invention example WR/CA signal of expression.In this example embodiment, 8 WR/CA signals are serialized as 4 signals.Figure 24 A shows the form of original WR/CA signal.As shown, during the single cycle of clock signal clk _ ref, transmit whole eight.Figure 24 B shows the form of the serialization version of WR/CA signal.As shown, the serialization signal is four bit wides, rather than original eight.During two cycles of clock signal clk _ ref, transmit the signal of serialization version.This serialization grouping is repeated secondary store as mentioned above.
Figure 25-28 comprises the schematic block diagram of each embodiment of the accumulator system of wherein using serialization of the present invention and background and prospect operation.In these embodiments, only primary memory repeats the WR/CA signal.Just, secondary store does not have repeat function, so secondary store may be not too complicated.This by carrying out the WR/CA order a plurality of serializations and each serialization version directly is sent to secondary store just can realizes.Secondary store is duplicate reading certificate not each other also.On the contrary, they each their read datas are separately directly turned to primary memory, primary memory is to main frame duplicate reading certificate then.
With reference to Figure 25, in accumulator system 520, main frame 566 sends to primary memory 522 with the xN form with the WR/CA grouping.In this example, primary memory generates three serialization WR/CA groupings and they directly is sent to secondary store 524a, 524b and the 524c that they are correlated with.The transmit port that primary memory 522 sends signal can have the 3xK form.For example, K can be 2.In this case, use three secondary stores, for the secondary store that receives the serialization signal, K can be 2.And each among secondary store 524a, 524b and the 524c directly is sent to primary memory with the xL form with its read data separately.
With reference to Figure 26, accumulator system 650 comprises main frame 666, primary memory 622 and secondary store 624a, 624b and 624c.In the accumulator system 650 of Figure 26, use discrete C/A and WR bus to replace the combination WR/CA bus of describing so far.As in the embodiment of Figure 26, in this embodiment, primary memory 622 produces a plurality of serialization C/A and WR from the WR/CA grouping, and they directly are sent to suitable secondary store 624a, 624b and 624c.The data that secondary store reads them directly are sent to primary memory 622.
Figure 27 and 28 is similar to Figure 25 and 26 respectively, except in Figure 27 and 28, and the grouping of the serialization that primary memory is carried out one of serialization on width.This configuration has reduced crosstalking between the serialization signal substantially, makes signal line by simpler, has reduced the amount of space that system and assembly thereof occupy, and has reduced I/O amount and reduced power consumption.Figure 29 comprises the table that graphic extension can be applicable to the accumulator system 750 and 850 the serialization command packet of Figure 27 and 28.
Figure 30 comprises the schematic block diagram of accumulator system 950 according to another embodiment of the present invention.In this embodiment, primary memory 922 comprises integrated high-speed memory buffer or impact damper 901 on the plate.All embodiment of the present invention described herein can be applicable to this embodiment of the present invention.In this embodiment, the information from secondary store 924a and 924b can be stored in the high-speed buffer 901 in advance.This has reduced the access amount to secondary store 924a and 924b of being undertaken by main frame 966, in one embodiment, background read operation by to the secondary store of preserving desired data can be written into high-speed buffer 901 with the frequent data that require of one or more secondary stores.As the result of storage data in high-speed buffer 901, can increase the handling capacity of accumulator system.
Figure 31 is the schematic block diagram according to the primary memory 922 shown in Figure 30 of the embodiment of the invention.Be similar to element in the block scheme of Figure 31 of Fig. 8 B and 23 element on the function with identical Reference numeral mark.No longer repeat the detailed description of these elements.
The block scheme of Figure 31 comprises high-speed buffer 901, serialiser 913 and the deserializer 915 that is used to save from secondary store 924a and 924b reading of data.If command decoder and input buffer 957 decoding prospects operation FOP fields (referring to Figure 13) enable (1110) as cache memory, then demoder 957 outputs to DEMUX 923 with control signal.In response, DEMUX 923 sends to high-speed buffer 901 with read data from secondary store 924a, 924b.
The schematic block diagram that Figure 32 comprises according to another embodiment of the present invention, wherein primary memory and secondary store comprise the accumulator system of high-speed buffer.As shown in the figure, in this embodiment, primary memory 1022 comprises high-speed buffer 1001, and secondary store 1024a comprises high-speed buffer 1002.In the high- speed buffer 1001,1002 one or two can be used to store the data from other storeies.Again, this method has increased the handling capacity of system 1050 basically.Should be noted that any among secondary store 1024a, the 1024b... or all can comprise high-speed buffer in the scope of this embodiment.
Figure 33 is the graphic extension schematic block diagram of accumulator system according to another embodiment of the present invention.Description about other embodiments of the invention is applicable to this embodiment above, and not conflict.The configuration of storer is any configuration described herein.In this embodiment, accumulator system 1150 comprises memory module with primary memory 1122 and secondary store 1124 and the cache memory 1151 with high-speed buffer.By cache memory 1151 all groupings are sent to storer from main frame 1166.In prospect and background read operation, can will be written into cache memory by the controller 1166 frequent data that require.Therefore, greatly improved the handling capacity of this accumulator system 1151.
Should be noted that in whole description related memory member can be the DRAM memory member.And all connections between the storer can be connections differential (differential) or single-ended.
Although illustrate and described the present invention with reference to exemplary embodiment of the present invention, but those of ordinary skill in the art is to be understood that, under the situation that does not deviate from principle of the present invention and spirit, can make amendment in these embodiments, scope of the present invention is limited by claim and equivalent thereof.
Claims (34)
1. accumulator system comprises:
Controller is used to generate control signal;
Primary memory is used to receive the control signal of self-controller; With
Be couple to the secondary store of primary memory, this secondary memory being adapted receives the control signal of autonomous memory, wherein
Described control signal limits and will and will be operated by the prospect of another execution in the secondary store of advocating peace by the background operation of an execution in the secondary store of advocating peace.
2. accumulator system as claimed in claim 1, wherein, when the target output port of one of the secondary store of advocating peace was not operated, background operation was by an execution in the secondary store of advocating peace.
3. accumulator system as claimed in claim 2, wherein, described background operation is one of power operation, precharge operation and self refresh operation.
4. accumulator system as claimed in claim 1, wherein, when one of prospect and background operation are read operation, in the data of controller place reception from secondary store.
5. accumulator system as claimed in claim 3 wherein, is sent to controller from the data of secondary store by primary memory.
6. accumulator system as claimed in claim 1, wherein, described primary memory is the DRAM storer.
7. accumulator system as claimed in claim 1, wherein, described secondary store is the DRAM storer.
8. accumulator system as claimed in claim 1, wherein, being connected between described controller and the primary memory is differential connection.
9. accumulator system as claimed in claim 1, wherein, being connected between described controller and the primary memory is single-ended connection.
10. accumulator system as claimed in claim 1, wherein, being connected between described primary memory and the secondary store is differential connection.
11. accumulator system as claimed in claim 1, wherein, being connected between described primary memory and the secondary store is single-ended connection.
12. accumulator system as claimed in claim 1, wherein, described primary memory and secondary store are linked by point-to-point link.
13. an accumulator system comprises:
Controller;
Be couple to the primary memory of controller, make and between primary memory and controller, can use first signal transfer protocol to transmit signal; With
Be couple to the secondary store of primary memory, make and between primary memory and secondary store, can use the secondary signal host-host protocol to transmit data, the described first and second signal transfer protocol differences.
14. accumulator system as claimed in claim 13, wherein, described first signal transfer protocol basic synchronization ground transmission first number of bits, and secondary signal host-host protocol basic synchronization ground transmission second number of bits, the described first and second quantity differences.
15. accumulator system as claimed in claim 13, wherein, the partial continuous version that described secondary signal host-host protocol is first signal transfer protocol at least.
16. accumulator system as claimed in claim 13, wherein, described primary memory is the DRAM storer.
17. accumulator system as claimed in claim 13, wherein, described secondary store is the DRAM storer.
18. accumulator system as claimed in claim 13, wherein, being connected between described controller and the primary memory is differential connection.
19. accumulator system as claimed in claim 13, wherein, being connected between described controller and the primary memory is single-ended connection.
20. accumulator system as claimed in claim 13, wherein, being connected between described primary memory and the secondary store is differential connection.
21. accumulator system as claimed in claim 13, wherein, being connected between described primary memory and the secondary store is single-ended connection.
22. accumulator system as claimed in claim 13, wherein, described primary memory and secondary store are linked by point-to-point link.
23. an accumulator system comprises:
Controller is used to generate control signal;
Primary memory is used to receive the control signal from described controller;
Be couple to the secondary store of primary memory, primary memory and secondary store are linked by point-to-point link; With
Be couple to the cache memory of primary memory, this cache memory is configured to store the information from secondary store.
24. accumulator system as claimed in claim 23, wherein, described cache memory is in the inside of primary memory.
25. accumulator system as claimed in claim 24, wherein, described cache memory is in the outside of primary memory.
26. accumulator system as claimed in claim 23, wherein, described cache memory is in the inside of secondary store.
27. accumulator system as claimed in claim 26, wherein, described cache memory is in the outside of secondary store.
28. accumulator system as claimed in claim 23, wherein, described cache memory is in the inside of primary memory, and second cache memory is in the inside of secondary store.
29. accumulator system as claimed in claim 23, wherein, described primary memory is the DRAM storer.
30. accumulator system as claimed in claim 23, wherein, described secondary store is the DRAM storer.
31. accumulator system as claimed in claim 23, wherein, being connected between described controller and the primary memory is differential connection.
32. accumulator system as claimed in claim 23, wherein, being connected between described controller and the primary memory is single-ended connection.
33. accumulator system as claimed in claim 23, wherein, being connected between described primary memory and the secondary store is differential connection.
34. accumulator system as claimed in claim 23, wherein, being connected between described primary memory and the secondary store is single-ended connection.
Applications Claiming Priority (5)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR84813/05 | 2005-09-12 | ||
| KR1020050084813A KR100717113B1 (en) | 2005-09-12 | 2005-09-12 | Semiconductor Memory Modules and Semiconductor Memory Systems |
| US60/716,587 | 2005-09-13 | ||
| KR87212/05 | 2005-09-20 | ||
| US11/451,802 | 2006-06-13 |
Publications (1)
| Publication Number | Publication Date |
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| CN1933018A true CN1933018A (en) | 2007-03-21 |
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| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CNA2006101536308A Pending CN1933018A (en) | 2005-09-12 | 2006-09-12 | Memory system and method having point-to-point link |
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| KR (1) | KR100717113B1 (en) |
| CN (1) | CN1933018A (en) |
Families Citing this family (1)
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| KR100916215B1 (en) | 2005-09-20 | 2009-09-08 | 삼성전자주식회사 | Protocol memory, memory module and protocol memory system and control method thereof. |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| US5544347A (en) | 1990-09-24 | 1996-08-06 | Emc Corporation | Data storage system controlled remote data mirroring with respectively maintained data indices |
| US5900011A (en) | 1996-07-01 | 1999-05-04 | Sun Microsystems, Inc. | Integrated processor/memory device with victim data cache |
| JP3092558B2 (en) * | 1997-09-16 | 2000-09-25 | 日本電気株式会社 | Semiconductor integrated circuit device |
| US6445624B1 (en) * | 2001-02-23 | 2002-09-03 | Micron Technology, Inc. | Method of synchronizing read timing in a high speed memory system |
| KR100387529B1 (en) * | 2001-06-11 | 2003-06-18 | 삼성전자주식회사 | semiconductor memory device having memory cell arrays capable of accomplishing random access |
| KR100606242B1 (en) * | 2004-01-30 | 2006-07-31 | 삼성전자주식회사 | Volatile Memory Device for buffering between non-Volatile Memory and host, Multi-chip packaged Semiconductor Device and Apparatus for processing data using the same |
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- 2005-09-12 KR KR1020050084813A patent/KR100717113B1/en not_active IP Right Cessation
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| KR20070030056A (en) | 2007-03-15 |
| KR100717113B1 (en) | 2007-05-10 |
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