CN1967817A - 半导体封装结构及其制造方法 - Google Patents
半导体封装结构及其制造方法 Download PDFInfo
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- CN1967817A CN1967817A CNA200610143623XA CN200610143623A CN1967817A CN 1967817 A CN1967817 A CN 1967817A CN A200610143623X A CNA200610143623X A CN A200610143623XA CN 200610143623 A CN200610143623 A CN 200610143623A CN 1967817 A CN1967817 A CN 1967817A
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Abstract
在一个实施例中,通过向封装基片的期望部分添加一层微粒而形成半导体封装。这层微粒形成了裂隙的矩阵,这些裂隙提供了用于机械锁定或接合包装材料的微观锁特征部件。
Description
技术领域
本发明一般涉及半导体器件,特别涉及半导体封装结构及其制造方法。
背景技术
塑料包装器件是半导体工业中使用的典型封装器件。在塑料包装器件中,半导体芯片或器件被附接在层压基片或导电金属引线架上。芯片是使用例如热固性环氧树脂、焊料合金,或通过低共熔浸湿(eutectic wetting)而附接的。然后用导线结合器和/或导电夹片结构将半导体芯片连接到导电引线上。然后用环氧模塑化合物(epoxy moldcompound)包装组件,并将其分成独立的封装单元。
改善环氧模塑化合物和引线架或基片之间的粘附一直是半导体封装中的主要难题。当环氧模塑化合物开始从引线架或基片表面脱离时,器件的长期可靠性就有危险。这种脱离可以对半导体芯片引发应力,而该应力可以导致芯片从引线架或者基片上脱离,或导致芯片本身断裂。另外,当环氧模塑化合物脱离时,产生了潮湿气体或其它污染物的通道,这会进一步影响封装器件的可靠性。
人们已经尝试用各种技术来改善环氧模塑化合物的粘附特性。这些技术包括:在环氧模塑化合物中使用助粘添加剂;对引线架或基片进行喷珠、激光烧蚀或蚀刻以从其表面去除材料;去除材料以形成模锁(mold lock)结构,或在诸如导线结合器的引线架上添加伪结构。然而,这些方法获得了有限的成功,而粘附问题仍然存在,并且继续是塑料包装插件中的问题。
因此,需要一种进一步改善环氧模塑化合物和导电引线架和/或层压基片之间的粘附的结构和组装方式。
附图说明
图1图解了根据本发明的一个实施例的半导体结构的放大横截面视图;
图2图解了图1中的半导体结构的一部分在制造过程的早期阶段中的顶视图;
图3图解了根据本发明的一个实施例的子组件的一部分在制造过程中的局部侧视图;
图4图解了根据本发明的另一个实施例的子组件的一部分在制造过程中的局部侧视图;以及
图5图解了根据本发明的半导体结构的制造工艺流程。
具体实施方式
为了易于理解,附图中的各元素不一定是按比例绘制的,并且在所有这些附图中适当的地方使用相同的元素编号。虽然图1中示出的实施例是方形扁平无引线封装(QFN,quad flat pack no lead)结构,但是本领域技术人员应该明白,本发明与任何使用导电基片和塑料环氧树脂的塑料包装电子封装都相关。其它相关的封装包括具有可供形成用于接合塑料包装层的特征部件(feature)的表面积的封装。这类封装包括,但不限于,QFP、DFN、DIP、SOIC、和PLCC封装。
总体来讲,本发明涉及一种电子封装结构和制造方法,其中,通过向支撑基片的表面添加或嵌入材料而改变了支撑基片的表面形貌。在优选实施例中,所添加或嵌入的材料包括微粒,这些微粒形成形状、裂隙或空腔的矩阵(matrix)。在模塑或包装过程中,液态环氧模塑化合物填充这些裂隙,从而在环氧模塑化合物凝固时形成机械锁特征部件。特别是,当环氧模塑化合物凝固时,提供了机械锁特征部件。这就使得改善了环氧模塑化合物和支撑基片之间的粘附。现在通过图1至图5来进一步理解本发明。
图1示出了根据本发明的一个实施例的半导体或电子封装结构或器件10的放大横截面视图。器件10包括以基片、或导电基片、或引线架11。在所示出的实施例中,基片11包括衬板(flag)、或管芯附接板(die attach paddle)、或管芯附接部分13,以及导电引线或多个引线16,这些引线16与衬板13彼此隔开或相邻。衬板13包括相反两侧的主表面131和133,其中电子芯片14通过管芯附接层18而附接或上覆在主表面131上。引线16也包括相反两侧的主表面161和162。
电子芯片14上的导电焊盘19通过导电连接结构与引线16电连接,所述导电连接结构包括例如导线结合器21和/或导电带条(strap)或夹子(clip)22。在替换实施例中,导电连接结构是导电焊盘19上的导电块或柱,并且电子芯片14以倒装芯片(flip chip)方式安装在基片11上。作为例子,电子芯片14包括功率MOSFET、双极功率晶体管、绝缘栅极双极晶体管、半导体闸流管、二极管、传感器、光学器件等,并且可以包括其它诸如逻辑和/或存储部件或电路的功能性。
模塑包装或钝化(passivating)层31覆盖并保护封装10的各部分。作为例子,包装层31包括环氧树脂塑料材料,并通过传统的模塑技术形成。作为例子,衬板13和引线16包括诸如铜合金(例如TAMAC5或CDA194)、镀铜的铁/镍合金(例如镀铜合金42)、经过电镀的铝、经电镀的塑料等的材料。电镀材料包括铜、银,或多层电镀这样的镍-钯和金。
根据本发明,器件10还包括微粒的矩阵,即添加到、上覆、部分嵌入衬板13的主表面131和引线16的主表面161的微粒41的涂层。更具体地说,微粒41的涂层包括形成于主表面131和/或161上的局域化微粒群体,这些微粒的形状是对称和/或随机。在本发明中,微粒41的涂层不是通过从主表面131和/或161上去除材料而形成的,而是通过在这些表面上以微粒的形式添加更多的材料而形成的。
作为例子,微粒41是金属和/或陶瓷微粒的涂层,这些微粒在主表面131和/或161上形成网状、多孔、或裂隙状的特征部件,从而与包装层31接合或机械锁定。在一个实施例中,微粒41包括铜、镍、或镍陶瓷。在一个实施例中,微粒41的平均直径或尺寸是从大约2.0×10-6米到大约2.50×10-5米。如果基片11有足够的表面积来形成网状结构,则微粒尺寸还可以更大。在另一个实施例中,微粒41被淀积在封装10上有剥离倾向的那些区域,比如衬板13上围绕电子芯片14的周边附近的区域。这在尺寸约束使得无法使用诸如蚀刻或压印模锁凹槽的其它技术时是有其优势的。
图2示出了引线架或基片11在制造过程中将微粒41淀积在衬板13和引线16各自的主表面131和161上之前的早期阶段的局部顶视图。在此阶段,掩蔽层210和211被放置在引线架11上,以覆盖或保护衬板13和引线16上那些不应淀积微粒41的部分。作为例子,这样的区域包括将在衬板13上附接电子芯片14的部分、以及将在引线16上结合或附接导电连接结构21和22的部分。作为例子,掩蔽层210和211包括聚合物保护带、光致抗蚀剂层、或其它保护材料。
图3和图4示出了将微粒41淀积在引线架或基片11上的优选方法的局部侧视图。图3中,在基片11的主表面上淀积烧结材料(例如,粉末状金属和/或陶瓷),经过加热的机械压具310施加向下的力(由箭头311表示)和热(由箭头312表示),以将微粒41和基片11烧结在一起。作为例子,当基片11包括铜时,微粒41则包括铜片或铜粉。根据本发明,当微粒41和基片11在压力和热的作用下被挤压在一起时,微粒41就结合在基片11上,并在基片11上形成了多孔矩阵或裂隙。
图4示出了热、等离子体、或冷喷射过程。在热或等离子体喷射过程中,用高压气体/空气来雾化已被加热的微粒41,并通过喷嘴410将其推向(由箭头411表示)基片11,其中微粒41撞击基片11的主表面(例如,如图1和图2所示的主表面131和/或161),并扁平化或变形成为不规则形状且与基片11结合在一起,从而根据本发明在基片11上形成多孔矩阵或裂隙。在冷喷射过程中,高压气体推动被加热到一定温度的微粒41的粉末,在该温度下,当微粒41与基片11撞击时会变形为不规则形状、与基片11结合、并形成根据本发明的涂层。在基片11上形成或涂覆的微粒41的密度由微粒的尺寸以及在主表面的单位面积上淀积的微粒量来控制。
图5示出了根据本发明的半导体封装的制造工艺流程或制造方法的例子。在步骤1001中,提供基片如基片11以进行涂覆。在这一步骤中,在基片11的主表面上添加可选掩蔽层,以使微粒41只积淀在期望的位置上。或者,对基片11的所有主表面都进行处理。在步骤1002中,微粒41的涂层被淀积或形成在、上覆、或部分地嵌入基片11中。作为例子,可以用结合图3和图4描述的涂覆工艺之一来淀积微粒41以形成网状层、微粒多孔矩阵、或裂隙状层面。
接下来,在步骤1003中,使用管芯附接层18将电子芯片14附接在基片11上。作为例子,管芯附接层18包括软焊料、导电环氧树脂、或低共熔焊料层。在步骤1004中,使用传统的导线结合或附接技术将导电连接结构21和/或22附接在电子芯片14和相应的引线16上,以形成子组件结构。接下来,将子组件结构放置在模塑设备中,用环氧模塑化合物来形成包装层31。根据这一步骤,包装层31与微粒41机械锁定或接合,以增强塑料模塑化合物与基片11的粘附。换句话说,在模塑过程中包装层31形成于或流入微粒41的多孔矩阵中,从而改善了包装层31和封装上有微粒41与之相结合的部分之间的粘附。然后在接下来的步骤1006中,将包装好的结构分成独立的塑料包装的半导体封装,例如图1所示的半导体封装10。
鉴于所有以上所述内容,很明显,提供了一种可以改善诸如封装基片的封装材料和包装层之间的粘附的半导体封装结构和制造方法。通过向封装基片上期望的位置添加一层微粒,本发明形成了这样的形状或裂隙的矩阵,其提供用于与包装层形成机械锁的结构。
虽然参照其具体实施例描述和图解说明了本发明,但是并不期望将本发明局限于这些意图为举例说明的实施例。本领域技术人员会认识到,在不脱离本发明的精神的情况下,可以进行修改和变化。因此,期望本发明包括所有那些落入所附权利要求的范围中的修改或变化。
Claims (10)
1.一种半导体封装结构器件:
具有主表面的基片;
附接在主表面一部分上的电子芯片;
上覆主表面其它部分而形成的微粒多孔矩阵;以及
覆盖基片的包装层,其中包装层在微粒多孔矩阵内部。
2.根据权利要求1的结构,其中所述基片包括:
附接所述电子芯片的导电衬板;以及
多个导电引线,其与导电衬板彼此隔开,其中微粒矩阵是上覆导电衬板的部分而形成的。
3.根据权利要求2的结构,其中微粒矩阵形成在多个导电引线的部分上。
4.根据权利要求1的结构,其中微粒多孔矩阵包括一层形状不规则且直径在从大约2.0×10-6米到大约2.5×10-5米的范围中的微粒。
5.根据权利要求1的结构,其中微粒多孔矩阵包括金属或陶瓷之一。
6.一种半导体封装器件,包括:
具有第一主表面的导电管芯附接板;
具有第二主表面的导电引线,其中导电引线与导电管芯附接板相邻;
附接在第一主表面的部分上的半导体器件;
将半导体器件电连接到导电引线上的导电连接结构;
结合到第一主表面的其它部分的微粒多孔矩阵;以及
在导电管芯附接板和半导体器件上形成的塑料包装层,其中微粒多孔矩阵与塑料包装层相接合,从而增强了导电管芯附接板和塑料包装层之间的粘附。
7.根据权利要求6的器件,其中各形状的多孔矩阵包括一层不规则形状的金属微粒,所述金属微粒的直径在从大约2.0×10-6米到2.5×10-5米的范围中。
8.根据权利要求6的部件,其中微粒多孔矩阵包括铜。
9.一种用于形成半导体封装器件的方法,包括以下步骤:
提供具有主表面的基片、和形成在所述主表面的部分上的微粒多孔矩阵;
将电子芯片附接在所述主表面的另一部分上;
形成覆盖所述基片的塑料包装层,其中塑料包装层在微粒多孔矩阵内部。
10.根据权利要求9的方法,其中提供基片的步骤包括以下步骤:
掩蔽基片的部分;以及
将微粒多孔矩阵淀积在基片上未被掩蔽的部分上。
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CN102856219A (zh) * | 2011-06-30 | 2013-01-02 | 英飞凌科技股份有限公司 | 用于把金属表面附着到载体的方法以及包装模块 |
CN102347252B (zh) * | 2010-07-21 | 2017-04-12 | 半导体元件工业有限责任公司 | 键合结构和方法 |
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US7759775B2 (en) * | 2004-07-20 | 2010-07-20 | Alpha And Omega Semiconductor Incorporated | High current semiconductor power device SOIC package |
JP4676277B2 (ja) * | 2005-08-16 | 2011-04-27 | ルネサスエレクトロニクス株式会社 | 半導体装置 |
US7808088B2 (en) * | 2006-06-07 | 2010-10-05 | Texas Instruments Incorporated | Semiconductor device with improved high current performance |
KR100830574B1 (ko) * | 2006-09-21 | 2008-05-21 | 삼성전자주식회사 | 반도체 소자 패키지 |
JP5776381B2 (ja) * | 2011-07-03 | 2015-09-09 | トヨタ自動車株式会社 | 半導体装置及びその製造方法 |
US9532448B1 (en) * | 2016-03-03 | 2016-12-27 | Ford Global Technologies, Llc | Power electronics modules |
US9917039B2 (en) * | 2016-04-20 | 2018-03-13 | Amkor Technology, Inc. | Method of forming a semiconductor package with conductive interconnect frame and structure |
CN109690759B (zh) * | 2016-09-08 | 2020-05-22 | 住友电木株式会社 | 半导体装置的制造方法 |
US10186478B2 (en) * | 2016-12-30 | 2019-01-22 | Texas Instruments Incorporated | Packaged semiconductor device with a particle roughened surface |
US10914018B2 (en) * | 2019-03-12 | 2021-02-09 | Infineon Technologies Ag | Porous Cu on Cu surface for semiconductor packages |
IT201900009501A1 (it) * | 2019-06-19 | 2020-12-19 | St Microelectronics Srl | Procedimento di die attachment per dispositivi a semiconduttore e dispositivo a semiconduttore corrispondente |
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TWI234250B (en) * | 2004-02-24 | 2005-06-11 | Stack Devices Corp | Semiconductor packaging element capable of avoiding electromagnetic interference and its manufacturing method |
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CN102347252B (zh) * | 2010-07-21 | 2017-04-12 | 半导体元件工业有限责任公司 | 键合结构和方法 |
CN102856219A (zh) * | 2011-06-30 | 2013-01-02 | 英飞凌科技股份有限公司 | 用于把金属表面附着到载体的方法以及包装模块 |
CN102856219B (zh) * | 2011-06-30 | 2016-04-27 | 英飞凌科技股份有限公司 | 用于把金属表面附着到载体的方法以及包装模块 |
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