CN1956177A - Chip structure, chip package structure and its process - Google Patents
Chip structure, chip package structure and its process Download PDFInfo
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- CN1956177A CN1956177A CN 200510114618 CN200510114618A CN1956177A CN 1956177 A CN1956177 A CN 1956177A CN 200510114618 CN200510114618 CN 200510114618 CN 200510114618 A CN200510114618 A CN 200510114618A CN 1956177 A CN1956177 A CN 1956177A
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/11—Manufacturing methods
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Abstract
A chip structure is prepared as setting lug on metal layer, covering protective layer and elastic layer on active surface of chip, setting an opening separately on protective layer and elastic layer and utilizing them to expose top surface of welding pads, enabling to add lug on elastic layer and jointing said lug with contact of base plate by heat pressing means, using polyimide or some other high polymer as material of elastic layer.
Description
Technical field
The present invention relates to a kind of semiconductor technology and structure, and be particularly related to a kind of chip package process and structure thereof.
Background technology
In chip encapsulation technology, thin-film package (Tape Carrier Package, TCP) be the packaged type of main in recent years LCD device drive chip (IC), but because the restriction of winding material and architectural characteristic, when utilizing more tiny interior pin joint chip, the manufacturing of winding and follow-up chip join technology are all very difficult, so stress gently in future, under thin, short, the little demand, cover brilliant film (Chip on Film, COF) and crystal grain and glass substrate bond package (Chip on Glass COG) arises at the historic moment.The packaged type of COF utilizes anisotropy conductiving glue (AnisotropicConductive Film at present, ACF) vertical conducting engages, utilizes projection hot pressing to produce eutectic bond and utilizes non-conductive adhesive (Non-Conductive Polymer, the contraction that NCP/NCF) produces behind hot-press solidifying joint.
Please refer to Fig. 1, it is the known schematic diagram that utilizes the encapsulating structure of anisotropy conductiving glue vertical conducting joint.Anisotropy conductiving glue 100 main functions provide the electrically conducting of golden projection 110 and contact 120 vertical direction, it utilizes conducting particles 102 to be out of shape the effect that produces conduction after pressing, as for 104 tool insulation effect of horizontal direction colloid, and must be pressed onto the conducting particles 102 of sufficient amount between golden projection 110 and the contact 120, to obtain lower contact impedance.The particle diameter of conducting particles 102 can be little of about 3～5 microns at present, its at random being distributed in the colloid 104, thereby highdensity conducting particles 102 probably accumulates in the zone of 110 of golden projections and causes the bridge joint short circuit, or causes open circuit or contact impedance difference because of conducting particles 102 uneven distributions.Therefore, the electrical characteristics after the distributing homogeneity of conducting particles 102 and density will influence golden projection 110 and contact 120 engages.
Then, please refer to Fig. 2, it is the known schematic diagram that utilizes the encapsulating structure of eutectic bond.Eutectic bond mainly is to utilize uniform heating and pressurization that golden projection 110 is combined because of eutectic with block tin 122.Because the intensity of eutectic bond is high and the reliability height, and can not produce the bridge joint problem of short-circuit, thereby can be applicable in the encapsulating structure of small contact spacing.
Then, please refer to Fig. 3, it is the known schematic diagram that utilizes non-conductive adhesive to shrink the encapsulating structure that engages.The convergent force that non-conductive adhesive 130 produces after by hot-press solidifying own, so that keep certain contact stress and conducting between golden projection 110 and the contact 120, the phenomenon but non-conductive adhesive 130 meeting generation heat in the environment of high temperature rises, make the contact stress between golden projection 110 and the contact 120 obviously descend, and contact impedance also rise thereupon.Therefore, the electrical characteristics after the characteristic of non-conductive adhesive 130 rising-heat contracting-colds will directly influence golden projection 110 and contact 120 engages.
In view of the foregoing, how in the existing chip encapsulation technology, improve the joint reliability between golden projection and the contact, to avoid problems such as bridge joint short circuit or colloid rising-heat contracting-cold and the electrical characteristics after influencing golden projection and contact engaging are the task of top priority.
Summary of the invention
Purpose of the present invention just provides a kind of chip structure and projection technology thereof, has the elastic layer of stress buffer and/or elasticity shot-like particle in the bottom of projection, to improve the joint reliability of projection.
Another object of the present invention provides a kind of chip-packaging structure and technology thereof, has the elastic layer of stress buffer and/or elasticity shot-like particle in the bottom of projection, to improve projection and electrical characteristics and reliability after contact engages.
The present invention proposes a kind of chip structure, comprises chip, protective layer, elastic layer and metal level.Chip has active surface, and chip has at least one weld pad, and it is arranged at active surface.Protective layer covers active surface, and protective layer has at least one first opening, its corresponding surface that exposes weld pad.In addition, the elastic layer protective mulch, and elastic layer has at least one second opening, its corresponding first opening that exposes.In addition, metal level covers this surface of weld pad at least.
Described according to one embodiment of the invention, the material of elastic layer for example is a macromolecule polymeric material, and metal level also can correspondingly connect golden projection or solder projection, and the top of golden projection or solder projection protrudes in outside second opening.Wherein, the material of metal level for example is selected from gold, titanium, tungsten, chromium, copper and alloy thereof.
Described according to one embodiment of the invention, chip structure also can comprise at least one block, and it is arranged at second around openings of elastic layer.In addition, chip structure also comprises a plurality of elasticity shot-like particles, protrudes in second around openings of elastic layer, and metal level also covers these elasticity shot-like particles.Wherein, the elasticity shot-like particle for example is arranged between second opening and block of elastic layer.
The present invention proposes a kind of chip structure in addition, comprises chip, protective layer, a plurality of elasticity shot-like particle and metal level.Chip has active surface, and chip has at least one weld pad, and it is arranged at active surface.Protective layer covers active surface, and protective layer has at least one opening, its corresponding surface that exposes weld pad.In addition, a plurality of elasticity shot-like particles are arranged at around openings, and metal level covers surface and these elasticity shot-like particles of weld pad at least.Wherein, chip structure also can comprise at least one block, and it is arranged at the periphery of opening and these elasticity shot-like particles of protective layer.
Described according to one embodiment of the invention, the material of elastic layer for example is a macromolecule polymeric material, and metal level also can correspondingly connect golden projection or solder projection, and the top of golden projection or solder projection protrudes in outside the opening.Wherein, the material of metal level for example is selected from gold, titanium, tungsten, chromium, copper and alloy thereof.
Described according to one embodiment of the invention, the top of golden projection has depressed part and convex surfaces, and the depressed part correspondence is positioned at the opening top, and the shape of corresponding these elasticity shot-like particles of the shape of convex surfaces.
The present invention proposes a kind of projection technology, and comprising the following steps: at first provides wafer, and this wafer comprises a plurality of chips and protective layer, and each chip has at least one weld pad, and it is exposed in first opening of protective layer.Form elastic layer on protective layer, elastic layer has at least one second opening, its corresponding first opening that exposes.Form metal level in first opening and second opening, this metal level covers weld pad at least.Afterwards, form projection on metal level.In addition, form in the step of elastic layer, also can comprise forming at least one block in second around openings of elastic layer.
The present invention proposes a kind of projection technology in addition, and comprising the following steps: at first provides wafer, and this wafer comprises a plurality of chips and protective layer, and each chip has at least one weld pad, and it is exposed in the opening of protective layer.Form a plurality of elasticity shot-like particles in the around openings of protective layer.Form metal level in opening, this metal level covers weld pad and these elasticity shot-like particles at least.Afterwards, form projection on metal level.In addition, this projection is made and can be comprised that also at least one block of formation is in the periphery of opening and these elasticity shot-like particles of protective layer.
The present invention proposes a kind of chip-packaging structure, comprises substrate, chip, metal level, at least one projection and colloid.Substrate has at least one contact, and chip is arranged on the substrate, and chip has at least one weld pad and elastic layer, and this elastic layer has opening, and it exposes the surface of weld pad.In addition, metal level covers this surface of weld pad at least, and projection is arranged on the metal level, and hot pressing connects contact.In addition, colloid coats projection.Wherein, colloid for example is an anisotropy conductiving glue, and it has a plurality of conducting particless, is electrically connected between projection and the contact.The material of elastic layer is a macromolecule polymeric material for example, and the material of metal level for example is selected from gold, titanium, tungsten, chromium, copper and alloy thereof.
Described according to one embodiment of the invention, chip-packaging structure also can comprise at least one block, and it is arranged at the around openings of elastic layer.In addition, chip-packaging structure also can comprise a plurality of elasticity shot-like particles, protrudes in the around openings of elastic layer, and metal level also covers these elasticity shot-like particles.Wherein, the elasticity shot-like particle for example is arranged between the opening and block of elastic layer.
The present invention proposes a kind of chip-packaging structure in addition, comprises substrate, chip, a plurality of elasticity shot-like particle, metal level, at least one projection and colloid.Substrate has at least one contact, and chip is arranged on the substrate, and chip has at least one weld pad and protective layer, and this protective layer has opening, and it exposes the surface of weld pad.In addition, a plurality of elasticity shot-like particles are arranged at around openings, and metal level covers this surface and these elasticity shot-like particles of weld pad at least.In addition, projection is arranged on the metal level, and hot pressing connects contact.Moreover colloid coats projection.Wherein, colloid for example is an anisotropy conductiving glue, and it has a plurality of conducting particless, is electrically connected between projection and the contact.The material of elasticity shot-like particle is a macromolecule polymeric material for example, and the material of metal level for example is selected from gold, titanium, tungsten, chromium, copper and alloy thereof.
Described according to one embodiment of the invention, chip-packaging structure also comprises at least one block, and it is arranged at the periphery of opening and these elasticity shot-like particles of protective layer.
The present invention proposes a kind of chip package process, and comprising the following steps: at first provides substrate, and substrate has at least one contact.Provide chip, and the chip correspondence has projection and elastic layer, wherein projection is arranged in the opening of elastic layer.Form colloid on substrate, this colloid covers contact.Afterwards, hot press projection and contact, and solidify colloid.Wherein, provide in the step of chip, also comprise forming at least one block in the around openings of elastic layer.
The present invention proposes a kind of chip package process in addition, and comprising the following steps: at first provides substrate, and substrate has at least one contact.Provide chip, and the chip correspondence has projection and elastic layer, wherein projection is arranged in the opening of this elastic layer, and opening around have a plurality of elasticity shot-like particles, be positioned at projection bottom.Form colloid on substrate, and colloid covers contact.Afterwards, hot press projection and contact, and solidify colloid.Wherein, provide in the step of chip, also comprise forming at least one block in the periphery of opening and these elasticity shot-like particles.
The present invention has the chip structure and the projection technology thereof of elastic layer and/or elasticity shot-like particle because of employing, so that the electrical characteristics after projection and the contact hot press, can be improved by the stress buffer of elastic layer and/or elasticity shot-like particle, keeping preferable contact stress, and improve the joint reliability of projection.
For above and other objects of the present invention, feature and advantage can be become apparent, preferred embodiment cited below particularly, and conjunction with figs. are described in detail below.
Description of drawings
Fig. 1 is the known schematic diagram that utilizes the encapsulating structure of anisotropy conductiving glue vertical conducting joint.
Fig. 2 is the known schematic diagram that utilizes the encapsulating structure of eutectic bond.
Fig. 3 is the known schematic diagram that utilizes non-conductive adhesive to shrink the encapsulating structure that engages.
Fig. 4 and Fig. 5 are a kind of generalized section with projection cube structure of elastic layer of first embodiment of the invention.
Fig. 6 and Fig. 7 are a kind of generalized section with projection cube structure of elastic layer of another embodiment of the present invention.
Fig. 8 is a kind of generalized section with projection cube structure of elasticity shot-like particle of one embodiment of the invention.
Fig. 9 is a kind of generalized section with projection cube structure of elasticity shot-like particle of another embodiment of the present invention.
Figure 10 and Figure 11 are respectively the elasticity shot-like particle and are arranged at parameatal schematic top plan view.
Figure 12 A～Figure 12 I is respectively a kind of schematic flow sheet with projection technology of elastic layer of one embodiment of the invention.
Figure 13 A～Figure 13 D is respectively a kind of schematic flow sheet that utilizes the chip package process of anisotropy conductiving glue vertical conducting of one embodiment of the invention.
Figure 14 is a kind of schematic diagram that utilizes non-conductive adhesive to shrink the chip-packaging structure that engages of another embodiment of the present invention.
Figure 15 A～Figure 15 H is respectively a kind of schematic flow sheet with projection technology of elasticity shot-like particle of one embodiment of the invention.
Figure 16 A～Figure 16 D is respectively a kind of schematic flow sheet that utilizes the chip package process of anisotropy conductiving glue vertical conducting of one embodiment of the invention.
Figure 17 is a kind of schematic diagram that utilizes non-conductive adhesive to shrink the chip-packaging structure that engages of another embodiment of the present invention.
The main element description of symbols
10: thermal head
100: anisotropy conductiving glue
102: conducting particles
104: colloid
110: golden projection
120: contact
122: block tin
130: non-conductive adhesive
200: chip structure
210: chip
212: weld pad
214: active surface
220: protective layer
216: opening
230: elastic layer
232,270: block
234: the elasticity shot-like particle
240: metal level
250: projection
252: depressed part
254: protrusion surface
260: solder projection
300,500: wafer
310,510: chip
312,512: weld pad
320,520: protective layer
322,522: the first openings
330: elastic layer
332: the second openings
334: block
340,540: metal level
342,542: photoresist
340a, 540a: metal level
350,550: golden projection
400,600: substrate
402,602: contact
410,610: anisotropy conductiving glue
412,612: conducting particles
414,614: colloid
420,620: non-conductive adhesive
530: the elasticity shot-like particle
Embodiment
Please refer to Fig. 4 and Fig. 5, it is a kind of generalized section with projection cube structure of elastic layer of first embodiment of the invention.The chip structure 200 of Fig. 4 mainly comprises chip 210, protective layer 220, elastic layer 230 and metal level 240, and projection 250 also can be arranged on the metal level 240, in order to be electrically connected the weld pad 212 of chip 210.Chip 210 has active surface 214, and protective layer 220 and elastic layer 230 cover the active surface 214 of chip 210 respectively, and protective layer 220 has opening 216 respectively with elastic layer 230, in order to appear the upper surface of weld pad 212.In addition, metal level 240 is except the upper surface that covers weld pad 212, but also ladder covers the inwall of opening 216 and the upper surface of elastic layer 230.In the present embodiment, the material of metal level 240 can be selected from gold, titanium, tungsten, chromium, copper and alloy thereof, and the material of weld pad 212 for example is copper or aluminium.Metal level 240 can increase the bond strength of weld pad 212 and projection 250, to resist the destruction that the thermal stress effect is produced.
From the above, in the application of golden projection, elastic layer 230 can increase golden projection 250 hot press in the electrical characteristics of the contact (not shown) of substrate, and the material of elastic layer 230 for example is polyimides (polyimide) or other high molecular polymer.The application of relevant elastic layer 230 on chip encapsulation technology will describe in detail in subsequent technique.In addition, the height of gold projection 250 can be controlled in 10～15 microns, the depressed part 252 suitable with opening 216 sizes can be formed on the top of gold projection 250, and the relative projection of the circumferential surface of depressed part 252, can make after the contact hot pressing of golden projection 250 and substrate because of deformation engages, to improve the reliability that engages.
Moreover, please refer to Fig. 5, the upper surface of elastic layer 230 also can be provided with one or more blocks 232, be adjacent to projection 250 around, the purpose of block 232 is conducting particles (not shown) bridge joint conductings of preventing anisotropy conductiving glue between two adjacent golden projections 250.The application of relevant block on chip encapsulation technology will describe in detail in subsequent technique.
Above-mentioned elastic layer 230 and block 232 also can simultaneously or separately be applied on the solder projection, as Figure 6 and Figure 7.The chip structure 200 of Fig. 6 mainly comprises chip 210, protective layer 220, elastic layer 230 and metal level 240, and solder projection 260 can be arranged on the metal level 240, to be electrically connected the weld pad 212 of chip 210.Wherein, the material of solder projection 260 for example is leypewter or lead-free solder, and the fusing point of solder projection 260 is lower, therefore can be welded on the contact (not shown) of substrate by high temperature reflow operation.The material of elastic layer 230 for example is polyimides (polyimide) or other high molecular polymer, but elastic buffer chip 210 is subjected to the destruction of thermal stress, to improve the reliability that engages.In addition, in the chip structure 200 of Fig. 7, also can comprise one or more blocks 270, be positioned at the upper surface of elastic layer 230, and be adjacent to solder projection 260 around, in order to increase the intensity of chip 210 opposing thermal stress.
Please refer to Fig. 8, it is for a kind of generalized section with projection cube structure of elasticity shot-like particle of one embodiment of the invention.In the present embodiment, identical member represents with identical mark, please refer to the explanation of Fig. 5 as for the setting of chip 210, protective layer 220, elastic layer 230 and metal level 240, is not described in detail in this.Different with first embodiment is, the bottom of projection 250 also has a plurality of elasticity shot-like particles 234, be distributed in the around openings of elastic layer 230, its material for example material with elastic layer 230 is identical, also can increase the electrical characteristics of projection 250 hot press in the contact (not shown) of substrate.Wherein, elasticity shot-like particle 234 is covered by metal level 240, and the top of projection 250 has protrusion surface 254 corresponding to elasticity shot-like particle 234, and its shape is equivalent to the shape of elasticity shot-like particle 234.Also, the projection 250 and the contact hot pressing deflection afterwards of substrate are increased, and then improve the reliability of joint owing to the change of projection 250 top shape.
Moreover, please refer to the chip structure of Fig. 9, the bottom of projection 250 has a plurality of elasticity shot-like particles 234 equally, but elasticity shot-like particle 234 directly is arranged at around the opening 216 of protective layer 220, but not be arranged at the around openings of elastic layer 230 as shown in Figure 8.Same principle, projection 250 top shape change because of elasticity shot-like particle 234, the projection 250 and the contact hot pressing deflection afterwards of substrate are increased, and then improve the reliability that engages.
Please refer to Figure 10 and Figure 11, it is respectively the elasticity shot-like particle and is arranged at parameatal schematic top plan view.The technology of applying nano level exposure imaging; the upper surface of above-mentioned protective layer 220 or elastic layer 230 can form nano-micro structure; its be distributed in opening 216 around, and the nano-micro structure of these spot distribution and proper alignment is above-mentioned elasticity shot-like particle 234, as shown in figure 10.In addition, nano-micro structure (being elasticity shot-like particle 234) shown in Figure 11 then is distributed in around the opening 216 in staggered mode.Certainly, the mode of other execution mode or arrangement also can be applicable in the manufacturing of elasticity shot-like particle 234, can not limit protection scope of the present invention because of making difference.
Please refer to Figure 12 A～Figure 12 I, it is respectively a kind of schematic flow sheet with projection technology of elastic layer of one embodiment of the invention.At first, please refer to Figure 12 A, provide wafer 300, and wafer 300 has a plurality of chips 310 and protective layer 320, and each chip 310 has at least one weld pad 312, it is exposed in first opening 322 of protective layer 320.Then, please refer to Figure 12 B, form elastic layer 330 on protective layer 320, elastic layer 330 has at least one second opening 332, its corresponding first opening 322 that exposes.Then, please refer to Figure 12 C, sputter or evaporated metal layer 340, and metal level 340 also can outwards cover the upper surface of elastic layer 330 except the upper surface that covers weld pad 312.
Afterwards, please refer to the technology of the electrogilding projection of Figure 12 D～Figure 12 G, elder generation's spin coating photoresist 342 is on elastic layer 330, and photoresist 342 is through forming suitable opening 344 after the exposure imaging, to expose the metal level 340 of weld pad 312 tops, electroplate as plating seed layer with metal level 340 afterwards, so that golden projection 350 is grown up in photoresist opening 344.At last, photoresist 342 is removed, can obtain golden projection 350 with solvent.In addition, in Figure 12 H, remove the part metals layer 340 on elastic layer 330 surfaces, and only keep the metal level 340a of projection 350 bottoms with etching solution.In the present embodiment, though form golden projection 350 or other solder projection in the mode of electroplating, other projection manufacturing technology also can be used, not as limit.
At last, please refer to Figure 12 I, also at least one block 334 can be arranged at projection 350 around, and the shape of block 334 and arrangement mode can suitably change, and are not described in detail in this.Relevant follow-up chip package process and structure please refer to the explanation of Figure 13 A～Figure 13 D.
Figure 13 A～Figure 13 D is respectively a kind of schematic flow sheet that utilizes the chip package process of anisotropy conductiving glue vertical conducting of one embodiment of the invention.At first, please refer to Figure 13 A, substrate 400 is provided, and be coated with anisotropy conductiving glue 410 on the contact 402 of substrate 400, and the conducting particles 412 of anisotropy conductiving glue 410 is evenly distributed in the colloid 414.Then, please refer to Figure 13 B～Figure 13 C, with the back side that thermal head (bonding head) 10 is drawn chip 310, the active surface that makes chip 310 is towards substrate 400, and with the contact 402 of the golden projection 350 on the chip 310, to carry out the step of hot press corresponding to substrate 400.Wherein, thermal head 10 descends and bestows pressure on chip 310, so that golden projection 350 and contact 402 pressings, and conducting particles 412 is out of shape after pressing to produce the effect of vertical conduction.Also because the top of golden projection 350 has depressed part 352, can catch more conducting particles 412 in wherein, thereby the contact impedance between golden projection 350 and the contact 402 can reduce.In addition, also can make the reliability of chip-packaging structure obviously improve around the golden projection 350 of chip 310 by the problem that a plurality of blocks 332 prevent conducting particles 412 bridge joint conductings is set.
At last, please refer to Figure 13 D, when finishing the entire chip packaging technology, and solidify after the anisotropy conductiving glue 410, because being arranged at the bottom of golden projection 350, elastic layer 330 can increase golden projection 350 hot press in the zygosity of contact 402, when running into variation of ambient temperature, though colloid 414 meeting rising-heat contracting-colds own, make the spacing of 402 of golden projection 350 and contacts produce slight variations, but elastic layer 330 also can produce reaction force with variation of ambient temperature, to offset the expansive force or the convergent force of colloid 414.Therefore, the reliability of chip-packaging structure obviously improves.
Moreover, please refer to Figure 14, it is a kind of schematic diagram that utilizes non-conductive adhesive to shrink the chip-packaging structure that engages of another embodiment of the present invention.In the technology of above-mentioned Figure 13 A～Figure 13 D, if can obtain the chip-packaging structure of Figure 14 when replacing anisotropy conductiving glues 410 with non-conductive adhesive 420.Because golden projection 350 hot pressing are on contact 402, and can bestow ultrasonic oscillation and make the top distortion of golden projection 350 and engage, elastic layer 330 also can produce reaction force with variation of ambient temperature simultaneously, to offset the expansive force of non-conductive adhesive 420.Therefore, the reliability of chip-packaging structure obviously improves.
Please refer to Figure 15 A～Figure 15 H, it is respectively a kind of schematic flow sheet with projection technology of elasticity shot-like particle of one embodiment of the invention.At first, please refer to Figure 15 A, provide wafer 500, and wafer 500 has a plurality of chips 510 and protective layer 520, and each chip 510 has at least one weld pad 512, it is exposed in the opening 522 of protective layer 520.Then, please refer to Figure 15 B, form a plurality of elasticity shot-like particles 530 around the opening 522 of protective layer 520.Then, please refer to Figure 15 C, sputter or evaporated metal layer 540, and metal level 540 also can outwards cover the upper surface of elasticity shot-like particle 530 and protective layer 520 except the upper surface that covers weld pad 512.
Afterwards, please refer to the technology of the electrogilding projection of Figure 15 D～Figure 15 F, elder generation's spin coating photoresist 542 is on metal level 540, and photoresist 542 is through forming suitable opening 544 after the exposure imaging, to expose the metal level 540 of weld pad 512 tops, electroplate as plating seed layer with metal level 540 afterwards, so that golden projection 550 is grown up in opening 544.At last, photoresist 542 is removed, can obtain golden projection 550 with solvent.In addition, in Figure 15 G, remove a part of metal level 540 on protective layer 520 surfaces, and only keep the metal level 540a of projection 550 bottoms with etching solution.In the present embodiment, though form projection 550 in the mode of electroplating, other projection manufacturing technology also can be used, not as limit.
At last, please refer to Figure 15 H, also at least one block 532 can be arranged at projection 550 around, and the shape of block 532 and arrangement mode can suitably change, and are not described in detail in this.Relevant follow-up chip package process and structure please refer to the explanation of Figure 16 A～Figure 16 D.
Figure 16 A～Figure 16 D is respectively a kind of schematic flow sheet that utilizes the chip package process of anisotropy conductiving glue vertical conducting of one embodiment of the invention.At first, please refer to Figure 16 A, substrate 600 is provided, and be coated with anisotropy conductiving glue 610 on the contact 602 of substrate 600, and the conducting particles 612 of anisotropy conductiving glue 610 is evenly distributed in the colloid 614.Then, please refer to Figure 16 B～Figure 16 C, with the back side that thermal head (bonding head) 10 is drawn chip 510, the golden projection 550 that makes chip 510 is towards substrate 600, and with the contact 602 of the golden projection 550 on the chip 510, to carry out the step of hot press corresponding to substrate 600.Wherein, thermal head 10 descends and bestows pressure on chip 510, so that golden projection 550 and contact 602 pressings, and conducting particles 612 is out of shape after pressing to produce the effect of vertical conduction.Also because the top of golden projection 550 has depressed part 552 and protuberate 554, can catch more conducting particles 612 in wherein, and the deflection of the end face of golden projection 550 also increases because of the setting of elasticity shot-like particle 530, thereby the contact impedance between golden projection 550 and the contact 602 can reduce.In addition, also can make the reliability of chip-packaging structure obviously improve around the golden projection 550 of chip 510 by the problem that a plurality of blocks 532 prevent conducting particles 612 bridge joint conductings is set.
At last, please refer to Figure 16 D, when finishing the entire chip packaging technology, and solidify after the anisotropy conductiving glue 610, because being arranged at the bottom of golden projection 550, elasticity shot-like particle 530 can increase golden projection 550 hot press in the zygosity of contact 602, when running into variation of ambient temperature, though colloid 614 meeting rising-heat contracting-colds own, make the spacing of 602 of golden projection 550 and contacts produce slight variations, but elasticity shot-like particle 530 also can produce reaction force with variation of ambient temperature, to offset the expansive force or the convergent force of colloid 614.Therefore, the reliability of chip-packaging structure obviously improves.
Moreover, please refer to Figure 17, it is a kind of schematic diagram that utilizes non-conductive adhesive to shrink the chip-packaging structure that engages of another embodiment of the present invention.In the technology of above-mentioned Figure 16 A～Figure 16 D, if can obtain the chip-packaging structure of Figure 17 when replacing anisotropy conductiving glues 610 with non-conductive adhesive 620.Because golden projection 550 hot pressing are on contact, and can bestow ultrasonic oscillation and make the top distortion of golden projection 550 and engage, elasticity shot-like particle 530 also can produce reaction force with variation of ambient temperature simultaneously, to offset the expansive force of non-conductive adhesive 620.Therefore, the reliability of chip-packaging structure obviously improves.
In sum, the present invention can be applicable on the encapsulation technology of LCD device drive chip, it adopts chip structure and the projection technology thereof with elastic layer and/or elasticity shot-like particle, so that the electrical characteristics after projection and the contact hot press, can be improved by the stress buffer of elastic layer and/or elasticity shot-like particle, keeping preferable contact stress, and improve the joint reliability of projection.Moreover, chip-packaging structure also can be provided with block and prevent that highdensity conducting particles from accumulating in the zone between projection and cause the bridge joint short circuit, especially the spacing between the adjacent golden projection is when microminiaturization develops, the phenomenon of known bridge joint conducting will be more obvious, so the effect of block makes the reliability of chip-packaging structure obviously improve.
Though the present invention discloses as above with preferred embodiment; right its is not in order to limit the present invention; any person of ordinary skill in the field; without departing from the spirit and scope of the present invention; when can doing a little change and improvement, so protection scope of the present invention is as the criterion when looking the claim person of defining.
Claims (20)
1. chip structure is characterized in that comprising:
Chip has active surface, and this chip has at least one weld pad, is arranged at this active surface;
Protective layer covers this active surface, and this protective layer has at least one first opening, the corresponding surface that exposes this weld pad;
Elastic layer covers this protective layer, and this elastic layer has at least one second opening, corresponding this first opening that exposes; And
Metal level, cover at least this weld pad this surface and the part this elastic layer.
2. chip structure according to claim 1 is characterized in that also comprising golden projection, and its bottom connects this metal level, and the top protrudes in outside this second opening.
3. chip structure according to claim 2 is characterized in that the top of this gold projection has depressed part, and correspondence is positioned at this second opening top.
4. chip structure according to claim 1 is characterized in that the material of this metal level is selected from gold, titanium, tungsten, chromium, copper and alloy thereof.
5. chip structure according to claim 1 is characterized in that also comprising solder projection, and its bottom connects this metal level, and the top protrudes in outside this second opening.
6. chip structure according to claim 1, the material that it is characterized in that this elastic layer is a macromolecule polymeric material.
7. chip structure according to claim 1 is characterized in that also comprising at least one block, is arranged at this second around openings of this elastic layer.
8. chip structure according to claim 1 is characterized in that also comprising a plurality of elasticity shot-like particles, protrudes in this second around openings of this elastic layer, and this metal level also covers above-mentioned these elasticity shot-like particles.
9. projection technology is characterized in that comprising:
Wafer is provided, and this wafer comprises a plurality of chips and protective layer, and each above-mentioned these chip has at least one weld pad, and it is exposed in first opening of this protective layer;
Form elastic layer on this protective layer, this elastic layer has at least one second opening, its corresponding this first opening that exposes;
Form metal level in this first opening and this second opening, this metal level covers this weld pad and this elastic layer of part at least; And
Form projection on this metal level.
10. projection technology according to claim 9 is characterized in that the mode that forms this projection comprises:
Form photoresist on this elastic layer, this photoresist has at least one photoresist opening, its corresponding this second opening and this metal level of exposing;
Electroplate, to form this projection in this photoresist opening; And
Remove this photoresist.
11. projection technology according to claim 9 is characterized in that the mode that forms this elastic layer comprises coating, and this elastic layer of patterning is to form this second opening.
12. projection technology according to claim 9 is characterized in that forming in the step of this elastic layer, also comprises forming at least one block in this second around openings of this elastic layer.
13. projection technology according to claim 9, it is characterized in that forming in the step of this elastic layer, also comprise forming a plurality of elasticity shot-like particles, and in the step that forms this metal level, this metal level also covers above-mentioned these elasticity shot-like particles in this second around openings of this elastic layer.
14. a chip-packaging structure is characterized in that comprising:
Substrate has at least one contact;
Chip is arranged on this substrate, and this chip has at least one weld pad and elastic layer, and this elastic layer has opening, and it exposes the surface of this weld pad;
Metal level, cover at least this weld pad this surface and the part this elastic layer;
At least one projection is arranged on this metal level, and hot pressing connects this contact; And
Colloid coats this projection.
15. chip-packaging structure according to claim 14 is characterized in that this colloid is an anisotropy conductiving glue, it has a plurality of conducting particless, is electrically connected between this projection and this contact.
16. chip-packaging structure according to claim 14 is characterized in that this colloid is a non-conductive adhesive.
17. chip-packaging structure according to claim 14 it is characterized in that the material of this projection comprises gold, and the height of this projection is between 10～15 microns.
18. chip-packaging structure according to claim 14, the material that it is characterized in that this elastic layer is a macromolecule polymeric material.
19. chip-packaging structure according to claim 14 is characterized in that also comprising at least one block, is arranged at this around openings of this elastic layer.
20. chip-packaging structure according to claim 14 is characterized in that also comprising a plurality of elasticity shot-like particles, protrudes in this around openings of this elastic layer, and this metal level also covers above-mentioned these elasticity shot-like particles.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN 200510114618 CN100492627C (en) | 2005-10-24 | 2005-10-24 | Chip structure, chip package structure and its process |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN 200510114618 CN100492627C (en) | 2005-10-24 | 2005-10-24 | Chip structure, chip package structure and its process |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN1956177A true CN1956177A (en) | 2007-05-02 |
| CN100492627C CN100492627C (en) | 2009-05-27 |
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| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN 200510114618 Expired - Fee Related CN100492627C (en) | 2005-10-24 | 2005-10-24 | Chip structure, chip package structure and its process |
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| Country | Link |
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| CN (1) | CN100492627C (en) |
Cited By (8)
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| CN102593023A (en) * | 2012-02-22 | 2012-07-18 | 苏州晶方半导体科技股份有限公司 | Bulge encapsulating structure and bulge encapsulating method |
| CN102835194A (en) * | 2010-04-08 | 2012-12-19 | 英特尔公司 | Designed debond interconnect structures |
| CN102931145A (en) * | 2011-08-09 | 2013-02-13 | 中芯国际集成电路制造(上海)有限公司 | Method for forming pad structure |
| CN105934816A (en) * | 2014-02-03 | 2016-09-07 | 迪睿合株式会社 | Connection body |
| CN106170852A (en) * | 2014-02-27 | 2016-11-30 | 迪睿合株式会社 | Connector, the manufacture method of connector and inspection method |
| CN107644810A (en) * | 2016-07-20 | 2018-01-30 | 全球能源互联网研究院 | A kind of front electrode processing method of compression joint type IGBT/FRD chips |
| CN111554582A (en) * | 2020-06-11 | 2020-08-18 | 厦门通富微电子有限公司 | Chip packaging method and chip packaging device |
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- 2005-10-24 CN CN 200510114618 patent/CN100492627C/en not_active Expired - Fee Related
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| CN102835194A (en) * | 2010-04-08 | 2012-12-19 | 英特尔公司 | Designed debond interconnect structures |
| US9269686B2 (en) | 2010-04-08 | 2016-02-23 | Intel Corporation | Debond interconnect structures |
| US9461010B2 (en) | 2010-04-08 | 2016-10-04 | Intel Corporation | Debond interconnect structures |
| CN102931145A (en) * | 2011-08-09 | 2013-02-13 | 中芯国际集成电路制造(上海)有限公司 | Method for forming pad structure |
| CN102593023A (en) * | 2012-02-22 | 2012-07-18 | 苏州晶方半导体科技股份有限公司 | Bulge encapsulating structure and bulge encapsulating method |
| CN105934816A (en) * | 2014-02-03 | 2016-09-07 | 迪睿合株式会社 | Connection body |
| CN106170852A (en) * | 2014-02-27 | 2016-11-30 | 迪睿合株式会社 | Connector, the manufacture method of connector and inspection method |
| CN107644810A (en) * | 2016-07-20 | 2018-01-30 | 全球能源互联网研究院 | A kind of front electrode processing method of compression joint type IGBT/FRD chips |
| CN107644810B (en) * | 2016-07-20 | 2024-05-31 | 全球能源互联网研究院 | Front electrode processing method of crimping IGBT/FRD chip |
| CN111554582A (en) * | 2020-06-11 | 2020-08-18 | 厦门通富微电子有限公司 | Chip packaging method and chip packaging device |
| CN111554582B (en) * | 2020-06-11 | 2022-07-15 | 厦门通富微电子有限公司 | Chip packaging method and chip packaging device |
| CN113851437A (en) * | 2020-06-28 | 2021-12-28 | 京东方科技集团股份有限公司 | Flip chip and chip packaging structure |
| WO2022001465A1 (en) * | 2020-06-28 | 2022-01-06 | 京东方科技集团股份有限公司 | Flip chip and chip packaging structure |
| US20220367328A1 (en) * | 2020-06-28 | 2022-11-17 | Chengdu Boe Optoelectronics Technology Co., Ltd. | Flip chip and chip packaging structure |
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| CN100492627C (en) | 2009-05-27 |
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