CN1945838A - TET LCD array substrate structure and its producing method - Google Patents
TET LCD array substrate structure and its producing method Download PDFInfo
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- CN1945838A CN1945838A CNA2006101498823A CN200610149882A CN1945838A CN 1945838 A CN1945838 A CN 1945838A CN A2006101498823 A CNA2006101498823 A CN A2006101498823A CN 200610149882 A CN200610149882 A CN 200610149882A CN 1945838 A CN1945838 A CN 1945838A
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Abstract
This invention discloses a TFT LCD array base plate structure including: a base plate, a grid, grid scanning lines and a public electrode, in which, the public electrode is a base electrode of the storage capacitance, a grid insulation layer, an active layer and a channel on it, a data scanning line, source and drain, a top electrode of the storage capacitor formed above the grid insulation layer, a passivation layer and its through hole or groove formed above the drain and the storage capacitor top electrode, pixel electrode formed on the passivation layer and connected with the drain and the top electrode of the storage capacitor via the passivation layer through hole or groove. This invention also discloses a manufacturing method for said array base plate structure, which can reduce the area of light strips and the overlapped area between the light strip and pixel electrode, the publick electrode and the transparent electrode so as to increase the open-end rate and storage capacitance.
Description
Technical field
The present invention relates to Thin Film Transistor-LCD (TFT LCD), relate in particular to TFT-LCD array substrate structure and manufacture method thereof.
Background technology
TFT LCD has characteristics low in energy consumption, that manufacturing cost is relatively low and radiationless, has occupied leading position in flat panel display market at present.Matrix type public electrode structure has been avoided electrode signal difference and crosstalk (Cross-Talk) that cause, flicker (Flicker) and horizontal white line etc. are bad.But, the structure of matrix type public electrode, although making improvement aspect the signal homogeneity, this structure has loss to aperture ratio of pixels.TFT LCD device stores electric capacity is the main means of keeping the pixel electrode current potential after the picture element scan signal ended, and unification increases the storage capacitance of pixel, can improve the homogeneity of picture effectively.Prior art adopts pixel electrode folded mutually with public electrode mostly, middle interval constitutes storage capacitance with insulating barrier, therefore to improve the storage capacitance of pixel, the one, increase the overlapping area, as use the matrix type structure, include shield bars in a storage capacitance part, transparent pixels electrode and shield bars are overlapped mutually, and realize the interconnected of public electrode, its advantage is the locus that makes full use of shield bars, make the functional diversities of shield bars, public electrode is interconnected simultaneously, also is the improvement to renovation technique, be a kind of TFT LCD array base-plate structure vertical view and sectional view in the prior art as shown in Figures 1 to 4, this structure comprises one group of controlling grid scan line 1 and parallel with it public electrode 13, and one group of vertical with it data scanning line 5, and adjacent controlling grid scan line and data scanning line have defined pixel region.Each pixel packets contains a TFT switching device, transparent pixels electrode 10, twice shield bars 12 and part public electrode 13, public electrode 13 and shield bars 12 couple together and are integrative-structure, and the transparent pixels lead-in wire 15 by public electrode is connected the shield bars 12 of pixel at the passivation layer via hole place 14 of public electrode up and down.The TFT device is made up of gate electrode 2, grid electrode insulating layer 4, active layer 3 and source electrode 6 and drain electrode 7.Transparent pixels electrode 10 is connected with the drain electrode 7 of TFT by passivation layer via hole 9.Passivation layer 8 covers on primary electrode 6 and the drain electrode 7.United States Patent (USP) technology 6,600,523 has designed redundant public electrode cabling and has improved renovation technique, and principle is similar.But the common weak point of said structure has been to cause the decline of aperture opening ratio.The 2nd, change insulating layer material, as the oxide of use aluminium or the oxide of tantalum, change the dielectric constant of storage capacitance insulation.Just be primarily aimed at the size that the change insulating layer material comes control store electric capacity in the United States Patent (USP) technology 6,953,715, its advantage is not change on the structure, and weak point is employed material, and the technology manufacturing process needs change.United States Patent (USP) technology 6,661,477 has designed the isolated island gate electrode, pixel electrode is linked to each other with the source electrode layer metal, reduces the drain-source electrode capacitance, with this improve crosstalk bad, though be that pixel electrode is linked to each other with the source electrode layer metal on the structure yet, do not relate to storage capacitance and improve part.
Summary of the invention
The objective of the invention is provides a kind of increase aperture opening ratio in order to overcome the defective of prior art, improves storage capacitance, improves the TFT LCD array base-plate structure and the manufacture method thereof of the display quality of TFT LCD.
To achieve these goals, the invention provides a kind of TFT LCD array base-plate structure, comprising:
One substrate;
One gate electrode, controlling grid scan line and public electrode all are formed on the described substrate, and wherein public electrode is the hearth electrode of storage capacitance;
A gate insulation layer is formed on described gate electrode, controlling grid scan line, public electrode and the substrate;
One active layer and on raceway groove, be formed on the described gate electrode;
One data scanning line, source electrode and drain electrode all are formed on the described gate insulation layer;
One storage capacitance top electrode is formed on the described gate insulation layer;
One passivation layer is formed on described gate insulation layer, data scanning line, source electrode, drain electrode and the storage capacitance top electrode, and forms passivation layer via hole or groove on described drain electrode and storage capacitance top electrode;
One pixel electrode is formed on the described passivation layer, and is connected with drain electrode and storage capacitance top electrode by described passivation layer via hole or groove.
Wherein, said structure also can comprise a shield bars, be positioned on the described substrate, under the gate insulation layer and near with parallel described data scanning line.And described public electrode and shield bars are structure as a whole.
In the such scheme, described storage capacitance top electrode is parallel and face public electrode.Described storage capacitance top electrode is parallel and face public electrode and shield bars part.Described parallel and storage capacitance top electrode that face public electrode and shield bars part is structure as a whole.Be electrically connected by lead between described public electrode and the shield bars.The material of described lead is identical with the pixel electrode material.The material of described controlling grid scan line, public electrode and shield bars is one of aluminium, chromium, tungsten, tantalum, titanium, molybdenum and aluminium nickel or combination in any.Described controlling grid scan line, public electrode and shield bars are for finishing the same material part of making in same plated film, mask lithography and etching process.The material of described gate insulation layer can be silicon nitride, aluminium oxide.Described storage capacitance top electrodes, data scanning line, source electrode and drain electrode material are one of aluminium, chromium, tungsten, tantalum, titanium, molybdenum and aluminium nickel or combination in any.Finish the same material part of making in described storage capacitance top electrodes, data scanning line, source electrode and electric leakage very same plated film, mask lithography and the etching process.
To achieve these goals, the present invention provides a kind of manufacture method of TFT LCD array base-plate structure simultaneously, comprising:
Wherein, public electrode and the shield bars that forms in the described step 1 is structure as a whole.Forming the storage capacitance top electrodes in the described step 3 comprises parallel and faces the public electrode part.Forming the storage capacitance top electrodes in the described step 3 comprises parallel and faces the shield bars part.
Compare with existing patented technology, array base-plate structure of the present invention can dwindle the shield bars area, shield bars and transparent pixels electrode have been dwindled, overlapping area between public electrode and the transparency electrode, thereby increased aperture opening ratio and/or improved storage capacitance, and further improved the display quality of TFT LCD.
Below in conjunction with the drawings and specific embodiments the present invention is further described in detail.
Description of drawings
Fig. 1 is a prior art TFT LCD array base-plate structure vertical view;
Fig. 2 is an A-A partial cross sectional view among Fig. 1;
Fig. 3 is a B-B partial cross sectional view among Fig. 1;
Fig. 4 is a C-C partial cross sectional view among Fig. 1;
Fig. 5 is a prior art pixel storage capacitor structural base public electrode vertical view;
Fig. 6 is a TFT LCD array base-plate structure vertical view of the present invention;
Fig. 7 is a D-D schematic cross-section among Fig. 6;
Fig. 8 is an E-E schematic cross-section among Fig. 6;
Fig. 9 is a F-F schematic cross-section among Fig. 6;
Figure 10 is a storage capacitor construction of the present invention bottom public electrode vertical view;
Figure 11 is a G-G sectional view among Figure 10;
Figure 12 is a storage capacitor construction top electrodes vertical view of the present invention (after the passivation layer etching);
Figure 13 is a H-H sectional view among Figure 12;
Figure 14 is an I-I sectional view among Figure 12;
Figure 15 is a J-J sectional view among Figure 12;
Figure 16 is a TFT LCD array base-plate structure vertical view of the present invention (passivation layer groove structure);
Figure 17 is a K-K sectional view among Figure 16;
Figure 18 is a L-L sectional view among Figure 16.
Mark among the figure: 1, controlling grid scan line; 2, gate electrode; 3, active layer; 4, grid electrode insulating layer; 5, data scanning line; 6, source electrode; 7, drain electrode; 8, passivation layer; 9, passivation layer via hole; 10, transparent pixels electrode; 12, shield bars, 13, public electrode; 14, the passivation layer via hole of public electrode; 15, the transparent pixels of public electrode lead-in wire; 16, storage capacitance top electrodes; 17, the passivation layer via hole of storage capacitance top electrodes; 18, the passivation layer groove of storage capacitance top electrodes.
Embodiment
Figure 6 shows that TFT LCD array base-plate structure vertical view of the present invention.To shown in Figure 9, one group of controlling grid scan line 1 and parallel with it public electrode 13 are arranged on this TFT LCD array base palte as Fig. 6, and one group of vertical with it data scanning line 5, adjacent controlling grid scan line and data scanning line have defined pixel region.Each pixel packets contains a TFT switching device, transparent pixels electrode 10, twice shield bars 12 and part public electrode 13, public electrode 13 and shield bars 12 couple together and are integrative-structure, and the transparent pixels lead-in wire 15 by public electrode is connected the shield bars 12 of pixel at the passivation layer via hole place 14 of public electrode up and down.The TFT device is made up of gate electrode 2, grid electrode insulating layer 4, active layer 3 and source electrode 6 and drain electrode 7.Transparent pixels electrode 10 is connected with the drain electrode 7 of TFT by passivation layer via hole 9.Passivation layer 8 is formed on primary electrode 6 and the drain electrode 7.Identical with top with the TFT dot structure of prior art matrix type public electrode.TFT LCD dot structure difference part of the present invention is, same layer metal (finishing with source electrode 6 same coating process) with source electrode 6 made storage capacitance top electrodes 16, and storage capacitance top electrodes 16 is parallel and face public electrode 13 and shield bars 12 parts.By storage capacitance top electrodes passivation layer via hole 17, storage capacitance top electrodes 16 is linked to each other with transparent pixels electrode 10.Storage capacitance top electrodes 16 and the same material part for finishing such as source electrode 6 and drain electrode 7 in same mask lithography technology, the passivation layer via hole 17 of storage capacitance top electrodes is finished in same mask lithography technology with the passivation layer via hole 9 of drain electrode 7, as Figure 12, and Figure 13, Figure 14, shown in Figure 15.
In the foregoing description, controlling grid scan line 1, gate electrode 2, public electrode 13 and shield bars 12 all have same structure and a material part what same plated film mask lithography etching technics was finished, material is one of aluminium, chromium, tungsten, tantalum, titanium, molybdenum and aluminium nickel etc. or combination in any, and structure can be individual layer or composite bed.Grid electrode insulating layer 4 material can be silicon nitride, aluminium oxide.Storage capacitance top electrodes 16, data scanning line 5, source electrode 6 and drain electrode 7 are for finishing the same structure and the material part of making in same plated film, mask lithography and the etching process, material is one of aluminium, chromium, tungsten, tantalum, titanium, molybdenum and aluminium nickel or combination in any, and structure also can be individual layer or composite bed.
As shown in figure 10, shield bars and public electrode area can dwindle in the present embodiment, therefore can increase aperture opening ratio.The theoretical foundation that this area dwindles is, storage capacitance top electrodes 16 of the present invention is finished by source, drain electrode layer metal, constitute the structure of storage capacitance top electrodes before comparing by the transparent pixels electrode, the distance at electric capacity the two poles of the earth shortens, when not changing the overlapping area, it is big that capacity becomes, or on the guaranteed capacity basis of invariable, the overlapping area can diminish, and has increased aperture opening ratio or/and increase the storage capacitance capacity.
In addition, the passivation layer via hole 17 that forms storage capacitance top electrodes of the present invention is the passivation layer groove of storage capacitance top electrodes also, this via hole or groove also or other structures are the passages that connect storage capacitance top electrodes and transparent pixels electrode, sectional view such as Figure 14, Figure 15, Figure 17, shown in Figure 180.
Above-mentioned pixel is a kind of typical application structure that the present invention is fit to, and also can carry out various accommodations, only covers public electrode top or shield bars top as the pre-portion of storage capacitance electrode; The storage capacitance top electrodes branch that covers public electrode top and shield bars top is arranged; The via hole that transparent pixels electrode storage capacitance top electrodes is linked to each other changes that groove etc. is similar to be leaked metal level by the source and make the storage capacitance hearth electrode into, and will increase the storage capacitance capacity surely or improve the various structures of aperture opening ratio, all meets the scope of the invention.
Describe TFT dot structure of the present invention and process for making thereof in detail below in conjunction with accompanying drawing.
At first, use magnetically controlled sputter method, preparation one layer thickness is at the grid metallic film of 1000 to 7000 on glass substrate.The grid metal material uses metals such as molybdenum, aluminium, alumel, molybdenum and tungsten alloy, chromium or copper usually.By exposure technology and chemical etching technology, on certain zone of glass substrate, form the pattern of controlling grid scan line 1 and gate electrode 2 and public electrode 13 and shield bars 12 with the gate mask version.Figure 10, shown in Figure 11, gate electrode, public electrode and shield bars have the angle of gradient after identical thickness and the corrosion.
Then, utilize chemical vapor deposited method consecutive deposition 1000 amorphous silicon membrane 3 on array base palte to the grid electrode insulating layer film 4 of 6000 and 1000 to 6000 .Grid electrode insulating layer 4 material are silicon nitride normally, also can use silica and silicon oxynitride, also can be oxide of aluminium etc.With the mask of the active layer back of exposing amorphous silicon is carried out etching, form the semiconductor layer raceway groove 3 of having chance with.And the insulating barrier 4 between grid metal and the amorphous silicon plays the effect that stops etching, as the dielectric of storage capacitance, improves technological parameter simultaneously, can improve the dielectric property of dielectric.
Subsequently, adopt and the grid metal species like the preparation method, the thickness that deposit one deck is similar to the grid metal on array base palte to 7000 metallic films, uses metals such as molybdenum, aluminium, alumel, molybdenum and tungsten alloy, chromium or copper at 1000 usually.As shown in figure 12, the mask by source-drain electrode 7 forms data scanning line 5, source electrode 6, drain electrode 7 and storage capacitance top electrodes 16 in certain zone.
Next, with and prepare grid electrode insulating layer and the similar method of active layer, on whole permutation substrate, deposit a layer thickness at the passivation layer 8 of 1000 to 6000 , its material is silicon nitride normally.Mask by passivation layer, utilize exposure and etching technics to form the passivation layer via hole 9 of drain electrode part and the passivation layer via hole 14 of shield bars part, form storage capacitance top electrodes passivation layer via hole 17 simultaneously, as Figure 14, shown in Figure 15, via hole yardstick and shape are decided on demand, can be hole or groove, as Figure 17, Figure 18.
At last, use magnetically controlled sputter method to form transparency electrode, transparency electrode commonly used is a tin indium oxide etc., and thickness is between 100 to 1000 .By technologies such as mask lithography chemical corrosions, form pixel electrode 10 and lead 15.
Its typical technological process can be summarized as follows:
Spatter film forming-the mask lithography of metal-etching (controlling grid scan line, gate electrode, bottom public electrode and shield bars)
The grid electrode insulating layer, the film forming-mask lithography-etching (storage capacitance dielectric, active layer and raceway groove) of the layer of having chance with
Spatter film forming-the mask lithography of metal-etching (source electrode, drain electrode, data scanning line and storage capacitance top electrodes)
Film forming-the mask lithography of passivation layer-etching (passivation layer via hole of passivation layer, public electrode via hole, passivation layer via hole and storage capacitance top electrodes)
Spatter film forming-the mask lithography of pixel electrode layer-etching (pixel electrode and public electrode lead-in wire).
The above embodiment that proposes is a kind of specific implementation method, other implementation method also can be arranged, as adopt 4 photoetching techniques or 3 photoetching skills; Select different material or combination of materials; Or adopt difform dot structure to finish; The passivation layer via hole 17 of storage capacitance top electrodes is designed to the passivation layer groove of storage capacitance top electrodes, realizes that channel form connects, as Figure 16, Figure 17, shown in Figure 180.
It should be noted that at last, above embodiment is only unrestricted in order to technical scheme of the present invention to be described, although the present invention is had been described in detail with reference to preferred embodiment, those of ordinary skill in the art should can use different materials and equipment to realize it as required, promptly can make amendment or be equal to replacement, and not break away from the spirit and scope of technical solution of the present invention technical scheme of the present invention.
Claims (17)
1, a kind of TFT LCD array base-plate structure is characterized in that, comprising:
One substrate;
One gate electrode, controlling grid scan line and public electrode all are formed on the described substrate, and wherein public electrode is the hearth electrode of storage capacitance;
A gate insulation layer is formed on described gate electrode, controlling grid scan line, public electrode and the substrate;
One active layer and on raceway groove, be formed on the described gate electrode;
One data scanning line, source electrode and drain electrode all are formed on the described gate insulation layer;
One storage capacitance top electrode is formed on the described gate insulation layer;
One passivation layer is formed on described gate insulation layer, data scanning line, source electrode, drain electrode and the storage capacitance top electrode, and forms passivation layer via hole or groove on described drain electrode and storage capacitance top electrode;
One pixel electrode is formed on the described passivation layer, and is connected with drain electrode and storage capacitance top electrode by described passivation layer via hole or groove.
2, array base-plate structure according to claim 1 is characterized in that: also comprise a shield bars, be positioned on the described substrate, under the gate insulation layer and near with parallel described data scanning line.
3, array base-plate structure according to claim 2 is characterized in that: described public electrode and shield bars are structure as a whole.
4, according to the arbitrary described array base-plate structure of claim 1 to 3, it is characterized in that: described storage capacitance top electrode is parallel and face public electrode.
5, according to claim 2 or 3 described array base-plate structures, it is characterized in that: described storage capacitance top electrode is parallel and face public electrode and shield bars part.
6, array base-plate structure according to claim 5 is characterized in that: described parallel and storage capacitance top electrode that face public electrode and shield bars part is structure as a whole.
7, array base-plate structure according to claim 6 is characterized in that: be electrically connected by lead between described public electrode and the shield bars.
8, array base-plate structure according to claim 7 is characterized in that: the material of described lead is identical with the pixel electrode material.
9, array base-plate structure according to claim 1 is characterized in that: the material of described controlling grid scan line, public electrode and shield bars is one of aluminium, chromium, tungsten, tantalum, titanium, molybdenum and aluminium nickel or combination in any.
10, array base-plate structure according to claim 9 is characterized in that: described controlling grid scan line, public electrode and shield bars are for finishing the same material part of making in same plated film, mask lithography and etching process.
11, array base-plate structure according to claim 1 is characterized in that: the material of described gate insulation layer can be silicon nitride, aluminium oxide.
12, array base-plate structure according to claim 1 is characterized in that: the material of described storage capacitance top electrodes, data scanning line, source electrode and drain electrode is one of aluminium, chromium, tungsten, tantalum, titanium, molybdenum and aluminium nickel or combination in any.
13, array base-plate structure according to claim 12 is characterized in that: the same material part of finishing making in described storage capacitance top electrodes, data scanning line, source electrode and electric leakage very same plated film, mask lithography and the etching process.
14, a kind of manufacture method of TFT LCD array base-plate structure is characterized in that, comprising:
Step 1, depositing metal films on substrate by photoetching process and chemical etching technology, forms controlling grid scan line, gate electrode, public electrode and shield bars;
Step 2, consecutive deposition grid electrode insulating layer film and amorphous silicon membrane on the substrate of completing steps 1 by photoetching process and chemical etching technology, form the raceway groove of semiconductor active layer and top thereof;
Step 3, depositing metal film on the substrate of completing steps 2 by photoetching process and chemical etching technology, forms data scanning line, source electrode, drain electrode and storage capacitance top electrodes;
Step 4, depositing metal thin film deposition passivation layer film on the substrate of completing steps 3, by photoetching process and chemical etching technology, form the passivation layer via hole of drain electrode part, passivation layer via hole and the storage capacitance top electrodes passivation layer via hole or the groove of shield bars part;
Step 5, deposit transparent pixels electrode layer on the substrate of completing steps 4 by photoetching process and chemical etching technology, forms pixel electrode and the lead that is connected between public electrode.
15, manufacture method according to claim 14 is characterized in that: the public electrode and the shield bars that form in the described step 1 are structure as a whole.
16, manufacture method according to claim 14 is characterized in that: form the storage capacitance top electrodes in the described step 3 and comprise parallel and face the public electrode part.
17, manufacture method according to claim 14 is characterized in that: form the storage capacitance top electrodes in the described step 3 and comprise parallel and face the shield bars part.
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