CN1833399B

CN1833399B - Rijndael block cipher apparatus and encryption/decryption method thereof

Info

Publication number: CN1833399B
Application number: CN2004800224469A
Authority: CN
Inventors: 李允京; 朴永秀; 金荣世; 李尚佑; 全星翼
Original assignee: Electronics and Telecommunications Research Institute ETRI
Current assignee: Electronics and Telecommunications Research Institute ETRI
Priority date: 2003-06-16
Filing date: 2004-06-01
Publication date: 2010-09-22
Anticipated expiration: 2024-06-01
Also published as: CN1833399A; KR20040108311A; KR100710455B1

Abstract

A rijndael block cipher apparatus including an operational unit that efficiently performs a round operation for encrypting/decrypting a rijndael block cipher and an encryption/decryption method thereof are disclosed. The rijndael block cipher apparatus is mounted in a mobile terminal such as a cellular phone and a PDA or a smart card, which requires a high-rate and small-sized cipher processor, and can encrypt and decrypt important data that requires security at high speed and perform the round operation with respect to upper 64 bits and lower 64 bits which are divided from 128-bit input data. Thus, the cipher apparatus can reduce the time required for encryption/decryption of the rijndael block cipher and the size of the apparatus.

Description

Rijndael block cipher apparatus and encrypting/decrypting method thereof

Technical field

The present invention relates generally to auspicious grace Dorr (rijndael) block encryption (cipher) device and encrypting/decrypting method thereof, relate in particular to be installed in cell phone, PDA, the smart card etc. and can high-speed encryption and deciphering require the rijndael cipher apparatus and the encrypting/decrypting method thereof of the significant data of safety.

Background technology

The Rijndael algorithm is a kind of symmetric key encryption algorithm of being encrypted developer Joan Daemen and Vincent Rijmen exploitation by Belgium, is selected as new AES (Advanced Encryption Standard) in October, 2000 or its front and back by America NI ST (national standard and technical body) then.

The rijndael algorithm is supported the variable block length of SPN (replacement-permutation network) structure, and makes it possible to use 128 bits, 192 bits and 256 bit keys about each block length.

The number of bout in the rijndael algorithm (round) is determined by key length, and under the situation of using 128 bit blocks, is recommended to use 10,12 and 14 bouts respectively about 128 bits, 192 bits and 256 bit keys.

Known recently, even use 128 bit keys, the rijndael algorithm does not produce safety problem yet, and therefore, the hard-wired research of rijndael algorithm of key that use is had 128 bit lengths is underway.

Because the rijndael algorithm is used for rijndael block encryption/decrypted data by repeating bout operation encrypt/decrypt, and is in particular the variable block length of supporting the SPN structure and provides, the ciphering process of rijndael block encryption is different from its decrypting process.Usually, the bout operation that is used for the ciphering process of rijndael block encryption comprises four conversion: displacement (substitution), row displacement (shift_row), mix row (mixcolumn) and add bout key (add-round-key), and the bout operation that is used for decrypting process comprises four conversion: anti-capable displacement, decommutation, add the bout key and row are closed in back mixing.According to the method for carrying out these conversion, the time of bout action need that is used for the rijndael block encryption is different with the hardware resource that will use, and it is most important to the performance of rijndael cipher processor further to carry out the method for conversion.Therefore, importantly reduce the time of realizing that bout is operated the amount of hardware resources that requires and carried out bout operation requirement.

Summary of the invention

Therefore, the applicant has developed rijndael cipher apparatus and the encrypting/decrypting method thereof that comprises operating unit, and this operating unit is carried out the bout operation that is used for encrypt/decrypt rijndael block encryption effectively.

The objective of the invention is to solve the problem that relates in the prior art and a kind of rijndael cipher apparatus and encrypting/decrypting method thereof are provided, this device is installed in portable terminal such as cell phone and PDA or the smart card, it requires two-forty and undersized cipher processor, and it can high-speed encryption and deciphering require the significant data of fail safe.

To achieve these goals, rijndael cipher apparatus according to the embodiment of the invention comprises: the bout operating unit, be used for 128 bits input key is converted to the 128 bit bout keys that are used to encrypt or decipher, and after input encryption or decryption oprerations commencing signal and mode signal, import bout operation commencing signal, rounds signal and bit select signal to be used for that 128 bits input data are divided into high 64 bits and low 64 bits and when selecting high or low 64 bits, store 128 bit bout keys according to the value of mode signal, by 128 bits input data being divided into high 64 bits and low 64 bits, and by respectively high 64 bits and the low 64 bits execution of cutting apart being comprised the row displacement, displacement, mix the bout operation that is listed as and adds the bout key conversion, encrypt 128 bits input data, and by 128 bits input data being divided into high 64 bits and low 64 bits, and by respectively high 64 bits and the low 64 bits execution of cutting apart being comprised anti-row displacement, decommutation, add the bout operation of bout key and anti-row mixing transformation, decipher 128 bits input data; The bout operation control unit, when being used for from input encryption or decryption oprerations commencing signal and mode signal, be divided into high 64 bits and low 64 bits and select the bit of high or low 64 bits to select signal, bout operation commencing signal and rounds signal to send to the bout operating unit by being used for that 128 bits are imported data, control the bout operation of bout operating unit; 64 Bit data registers are used to store the intermediate cryptographic or the data decryption of the high 64 bits input data of each bout operating period generation of being carried out by the bout operating unit; And 128 Bit data register, be used to store the intermediate cryptographic of the low 64 bits input data that each bout operating period of being carried out by the bout operating unit produces or data decryption low 64 bits, and storage produces and is stored in encryption in the 64 Bit data registers or data decryption high 64 Bit datas as it as the result of last bout operation as it.

To achieve these goals, rijndael block encryption method according to first embodiment of the invention comprises following steps: if by after bus input encryption or decryption oprerations commencing signal and the mode signal, import four clock bouts operation commencing signal and rounds signal from the bout operation control unit, the value of the mode signal of importing by bus when becoming ' 1 ' according to first clock so from bout operation commencing signal, the bout key generation unit of bout operating unit is converted to 128 bit bout keys with 128 bits input key and is used for encrypting, and stores 128 bit bout keys in inner 128 bit bout cipher key register; If import four clock bouts operation commencing signal and bit selection signal from the bout operation control unit, so when first clock becomes ' 1 ', the byte shift by high 64 Bit datas of the 128 bits input data of bus input is carried out in row displacement/anti-capable shift transformation unit, and high 64 Bit datas by first multiplexer output byte displacement, and displacement/decommutation converter unit is carried out the displacement of high 64 Bit datas continuously, high 64 Bit datas of output displacement are to first demodulation multiplexer, and high 64 Bit datas of storage displacement in 64 Bit data registers; When second clock of bout operation commencing signal becomes ' 1 ', the row mixing of exporting and being stored in high 64 Bit datas in the 64 Bit data registers by the encryption output of first demodulation multiplexer is carried out in row mixing/anti-row mixing transformation unit, high 64 Bit datas to the second demodulation multiplexer of output row mixing transformation, and high 64 Bit datas of memory row mixing transformation in 64 Bit data registers, row displacement/anti-capable shift transformation unit is carried out the byte shift by low 64 Bit datas of the 128 bits input data of bus input simultaneously, and low 64 Bit datas by first multiplexer output byte displacement, and displacement/decommutation converter unit is carried out the displacement of low 64 Bit datas continuously, low 64 Bit datas of output displacement are to first demodulation multiplexer, and low 64 Bit datas of storage displacement in low 64 bits of 128 Bit data registers; When the 3rd clock of bout operation commencing signal becomes ' 1 ', add bout key conversion unit and will be added to the high 64 bit bout keys that produce by bout key generation unit by the encryption output output of second demodulation multiplexer and high 64 Bit datas that are stored in the 64 Bit data registers, and high 64 Bit datas of storage addition in high 64 bits of 128 Bit data registers, and row mixing/anti-row mixing transformation unit is carried out the row mixing of exporting and being stored in low 64 Bit datas in the 128 Bit data registers by the encryption output of first demodulation multiplexer simultaneously, low 64 Bit datas to the second demodulation multiplexer of output row mixing transformation, and in low 64 bits of 128 Bit data registers low 64 Bit datas of memory row mixing transformation; And when the 4th clock of bout operation commencing signal becomes ' 1 ', adding bout key conversion unit will be added to the low 64 bit bout keys that produced by bout key generation unit by the encryption output output of second demodulation multiplexer and low 64 Bit datas that are stored in the 128 Bit data registers, and low 64 Bit datas of storage addition in low 64 bits of 128 Bit data registers.

To achieve these goals, rijndael piece decryption method according to first embodiment of the invention comprises following steps: if by after bus input encryption or decryption oprerations commencing signal and the mode signal, import four clock bouts operation commencing signal and rounds signal from the bout operation control unit, the value of the mode signal of importing by bus when becoming ' 1 ' according to first clock so from bout operation commencing signal, the bout key generation unit of bout operating unit is converted to 128 bit bout keys with 128 bits input key and is used for encrypting, and stores 128 bit bout keys in inner 128 bit bout cipher key register; If import four clock bouts operation commencing signal and bit selection signal from the bout operation control unit, so when first clock becomes ' 1 ', the anti-byte shift by high 64 Bit datas of the 128 bits input data of bus input is carried out in row displacement/anti-capable shift transformation unit, and export high 64 Bit datas of anti-byte shift by first multiplexer, and displacement/decommutation converter unit is carried out the decommutation of high 64 Bit datas continuously, high 64 Bit datas of output decommutation arrive first demodulation multiplexer, and store high 64 Bit datas of decommutation in 64 Bit data registers; When second clock of bout operation commencing signal becomes ' 1 ', add bout key conversion unit and will be added to the high 64 bit bout keys that produce by bout key generation unit by the deciphering output output of first demodulation multiplexer and high 64 Bit datas that are stored in the 64 Bit data registers, three demodulation multiplexers of high 64 Bit datas to the of output addition, and high 64 Bit datas of storage addition in 64 Bit data registers, row displacement/anti-capable shift transformation unit is carried out the byte backward shift position by low 64 Bit datas of the 128 bits input data of bus input simultaneously, and low 64 Bit datas by first multiplexer output byte backward shift position, and displacement/decommutation converter unit is carried out the decommutation of low 64 Bit datas continuously, low 64 Bit datas of output decommutation arrive first demodulation multiplexer, and store low 64 Bit datas of decommutation in low 64 bits of 128 Bit data registers; When the 3rd clock of bout operation commencing signal becomes ' 1 ', the anti-row mixing of exporting and being stored in high 64 Bit datas in the 64 Bit data registers by the deciphering output of the 3rd demodulation multiplexer is carried out in row mixing/anti-row mixing transformation unit, export high 64 Bit datas of anti-row mixing transformation by second demodulation multiplexer, and high 64 Bit datas of the anti-row mixing transformation of storage in high 64 bits of 128 Bit data registers, and add bout key conversion unit and will be added to the low 64 bit bout keys that produce by bout key generation unit by the deciphering output output of first demodulation multiplexer and low 64 Bit datas that are stored in the 128 Bit data registers simultaneously, by low 64 Bit datas of the 3rd demodulation multiplexer output addition, and low 64 Bit datas of storage addition in low 64 bits of 128 Bit data registers; And when the 4th clock of bout operation commencing signal becomes ' 1 ', the anti-row mixing of exporting and being stored in low 64 Bit datas in the 128 Bit data registers by the deciphering output of the 3rd demodulation multiplexer is carried out in row mixing/anti-row mixing transformation unit, export low 64 Bit datas of anti-row mixing transformation by second demodulation multiplexer, and in low 64 bits of 128 Bit data registers, store low 64 Bit datas of anti-row mixing transformation.

To achieve these goals, rijndael block encryption method according to second embodiment of the invention comprises following steps: if by after bus input encryption or decryption oprerations commencing signal and the mode signal, import three clock bouts operation commencing signal and rounds signal from the bout operation control unit, the value of the mode signal of importing by bus when becoming ' 1 ' according to first clock so from bout operation commencing signal, the bout key generation unit of bout operating unit is converted to 128 bit bout keys with 128 bits input key and is used for encrypting, and stores 128 bit bout keys in inner 128 bit bout cipher key register; If import three clock bouts operation commencing signal and bit selection signal from the bout operation control unit, so when first clock becomes ' 1 ', the byte shift by high 64 Bit datas of the 128 bits input data of bus input is carried out in row displacement/anti-capable shift transformation unit, and high 64 Bit datas by first multiplexer output byte displacement, and displacement/decommutation converter unit is carried out the displacement of high 64 Bit datas continuously, high 64 Bit datas of output displacement are to first demodulation multiplexer, and high 64 Bit datas of storage displacement in 64 Bit data registers; When second clock of bout operation commencing signal becomes ' 1 ', the row mixing of exporting and being stored in high 64 Bit datas in the 64 Bit data registers by the encryption output of first demodulation multiplexer is carried out in row mixing/anti-row mixing transformation unit, and high 64 Bit datas to the second demodulation multiplexer of output row mixing transformation, add bout key conversion unit and continuously these high 64 Bit datas are added to the high 64 bit bout keys that produced by bout key generation unit, and high 64 Bit datas of storage addition in 64 Bit data registers, row displacement/anti-capable shift transformation unit is carried out the byte shift by low 64 Bit datas of the 128 bits input data of bus input simultaneously, and low 64 Bit datas by first multiplexer output byte displacement, and displacement/decommutation converter unit is carried out the displacement of low 64 Bit datas continuously, low 64 Bit datas of output displacement are to first demodulation multiplexer, and low 64 Bit datas of storage displacement in low 64 bits of 128 Bit data registers; And when the 3rd clock of bout operation commencing signal becomes ' 1 ', 64 Bit datas that addition is stored in the 64 Bit data registers then are stored in high 64 bits of 128 Bit data registers, row mixing/anti-row mixing transformation unit is carried out the row mixing of exporting and being stored in low 64 Bit datas in the 128 Bit data registers by the encryption output of first demodulation multiplexer simultaneously, and low 64 Bit datas to the second demodulation multiplexer of output row mixing transformation, and add bout key conversion unit and will hang down 64 Bit datas continuously and be added to the low 64 bit bout keys that produce by bout key generation unit, and low 64 Bit datas of storage addition in low 64 bits of 128 Bit data registers.

To achieve these goals, rijndael piece decryption method according to second embodiment of the invention comprises following steps: if by after bus input encryption or decryption oprerations commencing signal and the mode signal, import three clock bouts operation commencing signal and rounds signal from the bout operation control unit, the value of the mode signal of importing by bus when becoming ' 1 ' according to first clock so from bout operation commencing signal, the bout key generation unit of bout operating unit is converted to 128 bit bout keys with 128 bits input key and is used for encrypting, and stores 128 bit bout keys in inner 128 bit bout cipher key register; If import three clock bouts operation commencing signal and bit selection signal from the bout operation control unit, so when first clock becomes ' 1 ', the anti-byte shift by high 64 Bit datas of the 128 bits input data of bus input is carried out in row displacement/anti-capable shift transformation unit, and export high 64 Bit datas of anti-byte shift by first multiplexer, and displacement/decommutation converter unit is carried out the decommutation of high 64 Bit datas continuously, high 64 Bit datas of output decommutation arrive first demodulation multiplexer, and store high 64 Bit datas of decommutation in 64 Bit data registers; When second clock of bout operation commencing signal becomes ' 1 ', add bout key conversion unit and will be added to the high 64 bit bout keys that produce by bout key generation unit by the deciphering output output of first demodulation multiplexer and high 64 Bit datas that are stored in the 64 Bit data registers, and three demodulation multiplexers of high 64 Bit datas to the of output addition, the anti-row that row mixing/anti-row mixing transformation unit is carried out high 64 Bit datas of addition continuously mix, export high 64 Bit datas of anti-row mixing transformation by second demodulation multiplexer, and high 64 Bit datas of the anti-row mixing transformation of storage in 64 Bit data registers, row displacement/anti-capable shift transformation unit is carried out the byte backward shift position by low 64 Bit datas of the 128 bits input data of bus input simultaneously, and low 64 Bit datas by first multiplexer output byte backward shift position, and displacement/decommutation converter unit is carried out the decommutation of low 64 Bit datas continuously, low 64 Bit datas of output decommutation arrive first demodulation multiplexer, and store low 64 Bit datas of decommutation in low 64 bits of 128 Bit data registers; And when the 3rd clock of bout operation commencing signal becomes ' 1 ', add bout key conversion unit and will be added to the low 64 bit bout keys that produce by bout key generation unit by the deciphering output output of first demodulation multiplexer and low 64 Bit datas that are stored in the 128 Bit data registers, and low three demodulation multiplexers of 64 Bit datas to the of output addition, the anti-row that row mixing/anti-row mixing transformation unit is carried out low 64 Bit datas of addition continuously mix, export low 64 Bit datas of anti-row mixing transformation by second demodulation multiplexer, and low 64 Bit datas of the anti-row mixing transformation of storage in low 64 bits of 128 Bit data registers, high 64 Bit datas that will be stored in simultaneously in the 64 Bit data registers are stored in high 64 bits of 128 Bit data registers.

To achieve these goals, rijndael block encryption method according to third embodiment of the invention comprises following steps: if by after bus input encryption or decryption oprerations commencing signal and the mode signal, import two clock bouts operation commencing signal and rounds signal from the bout operation control unit, the value of the mode signal of importing by bus when becoming ' 1 ' according to first clock so from bout operation commencing signal, the bout key generation unit of bout operating unit is converted to 128 bit bout keys with 128 bits input key and is used for encrypting, and stores 128 bit bout keys in inner 128 bit bout cipher key register; If import two clock bouts operation commencing signal and bit selection signal from the bout operation control unit, so when first clock becomes ' 1 ', the byte shift by high 64 Bit datas of the 128 bits input data of bus input is carried out in row displacement/anti-capable shift transformation unit, and high 64 Bit datas by first multiplexer output byte displacement, displacement/decommutation converter unit is carried out the displacement of high 64 Bit datas continuously, high 64 Bit datas of output displacement are to first demodulation multiplexer, and high 64 Bit datas by first demodulation multiplexer output displacement, the row that row mixing/anti-row mixing transformation unit is carried out by high 64 Bit datas of the encryption output output of first demodulation multiplexer mix, and high 64 Bit datas to the second demodulation multiplexer of output row mixing transformation, and add bout key conversion unit and continuously these high 64 Bit datas are added to the high 64 bit bout keys that produce by bout key generation unit, and high 64 Bit datas of storage addition in 64 Bit data registers; And when second clock of bout operation commencing signal becomes ' 1 ', the byte shift by low 64 Bit datas of the 128 bits input data of bus input is carried out in row displacement/anti-capable shift transformation unit, and low 64 Bit datas by first multiplexer output byte displacement, and displacement/decommutation converter unit is carried out the displacement of low 64 Bit datas continuously, and low 64 Bit datas of output displacement are to first demodulation multiplexer, the row that row mixing/anti-row mixing transformation unit is carried out low 64 Bit datas continuously mix, and low 64 Bit datas to the second demodulation multiplexer of output row mixing transformation, add bout key conversion unit and continuously these low 64 Bit datas are added to the low 64 bit bout keys that produced by bout key generation unit, and low 64 Bit datas of storage addition in low 64 bits of 128 Bit data registers, high 64 Bit datas that will be stored in simultaneously in the 64 Bit data registers are stored in high 64 bits of 128 Bit data registers.

To achieve these goals, rijndael piece decryption method according to second embodiment of the invention comprises following steps: if by after bus input encryption or decryption oprerations commencing signal and the mode signal, import two clock bouts operation commencing signal and rounds signal from the bout operation control unit, the value of the mode signal of importing by bus when becoming ' 1 ' according to first clock so from bout operation commencing signal, the bout key generation unit of bout operating unit is converted to 128 bit bout keys with 128 bits input key and is used for encrypting, and stores 128 bit bout keys in inner 128 bit bout cipher key register; If import two clock bouts operation commencing signal and bit selection signal from the bout operation control unit, so when first clock becomes ' 1 ', the anti-byte shift by high 64 Bit datas of the 128 bits input data of bus input is carried out in row displacement/anti-capable shift transformation unit, and export high 64 Bit datas of anti-byte shift by first multiplexer, displacement/decommutation converter unit is carried out the decommutation of high 64 Bit datas continuously, and high 64 Bit datas of output decommutation are to first demodulation multiplexer, add bout key conversion unit and will be added to the high 64 bit bout keys that produce by bout key generation unit by high 64 Bit datas that the deciphering output of first demodulation multiplexer is exported continuously, and three demodulation multiplexers of high 64 Bit datas to the of output addition, and the anti-row that row mixing/anti-row mixing transformation unit is carried out high 64 Bit datas of addition continuously mix, export high 64 Bit datas of anti-row mixing transformation by second demodulation multiplexer, and in 64 Bit data registers, store high 64 Bit datas of anti-row mixing transformation; And when second clock of bout operation commencing signal becomes ' 1 ', the byte backward shift position by low 64 Bit datas of the 128 bits input data of bus input is carried out in row displacement/anti-capable shift transformation unit, and low 64 Bit datas by first multiplexer output byte backward shift position, displacement/decommutation converter unit is carried out the decommutation of low 64 Bit datas continuously, and low 64 Bit datas of output decommutation are to first demodulation multiplexer, add bout key conversion unit and will be added to the low 64 bit bout keys that produce by bout key generation unit by low 64 Bit datas that the deciphering output of first demodulation multiplexer is exported continuously, and low three demodulation multiplexers of 64 Bit datas to the of output addition, the anti-row that row mixing/anti-row mixing transformation unit is carried out low 64 Bit datas of addition continuously mix, export low 64 Bit datas of anti-row mixing transformation by second demodulation multiplexer, and low 64 Bit datas of the anti-row mixing transformation of storage in low 64 bits of 128 Bit data registers, high 64 Bit datas that will be stored in simultaneously in the 64 Bit data registers are stored in high 64 bits of 128 Bit data registers.

Description of drawings

By preferred embodiments of the invention will now be described with reference to the accompanying drawings, it is more obvious that above-mentioned purpose of the present invention, further feature and advantage will become, in the accompanying drawings:

Fig. 1 is the view of explanation according to the structure of rijndael cipher apparatus of the present invention.

Fig. 2 is the view of the structure of explanation bout operating unit.

Fig. 3 is the view of the structure of explanation bout key generation unit.

Fig. 4 is explanation first sequential chart according to the method for encryption rijndael block encryption of the present invention.

Fig. 5 is explanation first sequential chart according to the method for deciphering rijndael block encryption of the present invention.

Fig. 6 is second sequential chart of explanation according to the method for encryption rijndael block encryption of the present invention.

Fig. 7 is second sequential chart of explanation according to the method for deciphering rijndael block encryption of the present invention.

Fig. 8 is three sequential chart of explanation according to the method for encryption rijndael block encryption of the present invention.

Fig. 9 is three sequential chart of explanation according to the method for deciphering rijndael block encryption of the present invention.

Embodiment

Now, will describe rijndael cipher apparatus and encrypting/decrypting method thereof according to the preferred embodiment of the invention with reference to the accompanying drawings in detail.

With reference to figure 1, be according to the main intention of rijndael cipher apparatus of the present invention: carry out all bouts operations, being used for 64 bits is the input data that encrypted in units and deciphering are used for rijndael block encryption/deciphering; And produce the bout key that the bout operation requires when carrying out the bout operation.

For rijndael block encryption/deciphering, from import encryption or decryption oprerations commencing signal " " and mode signal by bus 200 after, input bout operation commencing signal Round_start, rounds signal Round_number and bit select signal sel to be used for that 128 bits input data are divided into high 64 bits and low 64 bits and when each bout operation selected high or low 64 bits, bout operating unit 100 is converted to 128 bit bout key RK with 128 bits input key and is used for encrypting or deciphering, and stores 128 bit bout keys according to the value of mode signal.

If the value of mode signal indication ' 0 ', by 128 bits input data being divided into high 64 bits and low 64 bits, and carry out the bout operation that comprises row displacement (shift_row), displacement, is listed as the conversion that mixes and add bout key (add-round-key) respectively with low 64 bits about high 64 bits of cutting apart, bout operating unit 100 is encrypted 128 bits input data.

If the value of mode signal indication ' 1 ', by 128 bits input data being divided into high 64 bits and low 64 bits, and carry out the bout operation that comprises anti-capable displacement, decommutation, adds bout key and anti-row mixing transformation respectively about high 64 bits and low 64 bits cut apart, bout operating unit 100 deciphering 128 bits input data.

If encrypt or decryption oprerations commencing signal and mode signal by bus 200 inputs, during so from input encryption or decryption oprerations commencing signal and mode signal, select signal to be used for 128 bits input data being divided into high 64 bits and hanging down 64 bits and high or low 64 bits are selected in each bout operation, the bout operation of bout operation control unit 300 control bout operating units 100 by send it back closing operation commencing signal Round_start, rounds signal Round_number and bit to bout operating unit 100.

400 storages of 64 Bit data registers are by the intermediate cryptographic or the data decryption of the high 64 bits input data of each bout operating period generation of bout operating unit 100 execution.

The intermediate cryptographic of the low 64 bits input data that each bout operating period that the storage of 128 Bit data registers 500 is carried out by bout operating unit 100 produces or data decryption be as its low 64 bits, and storage produces and be stored in encryption in the 64 Bit data registers 400 or data decryption high 64 bits as it as the result of last one bout operation.

With reference to figure 2, if from single 300 input bout operation commencing signal and the rounds signals of bout operation control, the bout key generation unit 110 of bout operating unit 100 is converted to 128 bit bout key RK according to the value of the mode signal of importing by bus 200 with 128 bits input key so, and stores 128 bit bout keys in inner 128 bit bout cipher key register.

If select signal from single 300 input bout operation commencing signals of bout operation control and bit, the row displacement of bout operating unit 100 so/shift transformation unit 120 bases of instead going are passed through the value of the mode signal of bus 200 inputs, execution is from high 64 bits of cutting apart by the 128 bits input data of bus 200 inputs and the different numbers of byte shift that hang down 64 bits, and, select the value of signal to control the output of this multiplexer according to bit by high 64 bits and low 64 bits of first multiplexer 121 output bytes displacement.

The displacement of bout operating unit 100/decommutation converter unit 130, use relative byte input that the displacement box (S-box) or the decommutation box (SI-box) of a byte output are provided, carry out from row displacement/high 64 Bit datas of anti-capable shift transformation unit 120 outputs and the displacement or the decommutation of low 64 Bit datas.

First demodulation multiplexer (demultiplexer) 140 of bout operating unit 100 be according to the value of mode signal, by it encryption output ' 0 ' and its deciphering output ' 1 ' in any one output from high 64 Bit datas of displacement/decommutation converter unit 130 outputs or hang down 64 Bit datas.

Row mixing/anti-row mixing transformation the unit 150 of bout operating unit 100, " row of 0 ' high 64 Bit datas of importing or low 64 Bit datas mix, the anti-row mixing of perhaps carrying out high 64 Bit datas that added the bout key conversion or hanging down 64 Bit datas to carry out the encryption output that passes through first demodulation multiplexer 140.

Second demodulation multiplexer 160 of bout operating unit 100 be according to the value of mode signal, by it encryption output ' 0 ' and its deciphering output ' 1 ' in any one output from high 64 Bit datas of row mixings/anti-row mixing transformation unit 150 outputs or hang down 64 Bit datas.

High 64 Bit datas or low 64 Bit datas of encryption output ' 0 ' input that adds deciphering output ' 1 ' that bout key conversion unit 170 will be by first demodulation multiplexer 140 or second demodulation multiplexer 160 of bout operating unit 100 are added to from the 128 bit bout key RK that are used to encrypt or decipher of bout key generation unit 110 outputs.

The 3rd demodulation multiplexer 180 of bout operating unit 100 be according to the value of mode signal, by it encryption output ' 0 ' and its deciphering output ' 1 ' in high 64 Bit datas or low 64 Bit datas of any one output from adding 170 outputs of bout key conversion unit.

With reference to figure 3, pre-cipher key register 111 storages of 128 bits of bout key generation unit 110 are by the pre-key of 128 bits input key conduct of bus 200 inputs, be used for 128 bits input key is converted to the 128 bit bout key RK that are used to encrypt or decipher, and store the pre-key of 128 bit bout key RK conduct that produces after each bout operation, be used for producing the bout key that next bout operation is used.

The 128 bit bout key RK that 128 bit bout cipher key register 111a of bout key generation unit 110 are used to encrypt or decipher for each bout operation store.In Fig. 3, after each bout operation, the 128 bit bout key RK that are stored among the 128 bit bout cipher key register 111a are backuped to the pre-cipher key register 111 of 128 bits, and are used as the bout key (that is pre-key) of the previous bout in the next bout operation.

The constant memory cell 112 storage constant value Rcon of bout key generation unit 110, this constant value determines that according to the rank (order) of the bout of being indicated by the rounds signal this rounds signal is from 300 inputs of bout operation control unit.Preferably constant memory cell 112 comprises ROM.

According to second multiplexer 113 of the value control bout key generation unit 110 of the mode signal by bus 200 input, and select and output from any one of 32 bit keys that are used for encrypting or deciphering of pre-cipher key register 111 of 128 bits and 128 bit bout cipher key register 111a input.

114 pairs of 32 bit keys by 113 inputs of second multiplexer of the shift unit of bout key generation unit 110 are carried out the cyclic shift to the first from left byte.

The displacement transformation unit 115 of bout key generation unit 110 comprises the displacement box (S-box) that is used to carry out replacement operator, and to carrying out displacement by 32 bit keys of shift unit 114 displacements.

First XOR gate 116 of bout key generation unit 110 is carried out the most significant byte and the xor operation that is stored in the constant value the constant memory cell 112 of 32 bit keys of 115 outputs from the displacement transformation unit.

The bout xor operation unit 117 of bout key generation unit 110, be added to 32 bit values that residue 24 bits except the most significant byte of displacement transformation unit 115 obtain by using by output bit with first XOR gate 116, be stored in the 128 bit bout keys (being pre-key) of the previous bout in the pre-cipher key register 111 of 128 bits, and the 128 bit bout key RK that are stored in the New Round among the 128 bit bout cipher key register 111a, carry out xor operation, come each bout for the bout operation, new generation will be stored in the 128 bit bout key RK that are used to encrypt or decipher among the 128 bit bout cipher key register 111a.

Second XOR gate 118 of bout xor operation unit 117 is by carrying out following both xor operation, produce the highest effective 32 bit bout key RK0 of 128 bit bout keys, be used for the encryption or the deciphering of New Round: be added to 32 bit values that residue 24 bits except the most significant byte of displacement transformation unit 115 obtain by output bit with first XOR gate 116; And the highest effective 32 bit bout key PK0 of 128 bit bout keys of previous bout.

The 3rd XOR gate 118a of bout xor operation unit 117 is by carrying out following both xor operation, 32 bits that produce 128 bit bout keys (promptly, 64 bits of the 95th bit to the) bout key RK1, be used for the encryption of New Round: the highest effective 32 bits of 128 bit bout keys of New Round (i.e. 96 bits of the 127th bit to the) bout key RK0, and 32 bits (that is 64 bits of the 95th bit to the) the bout key PK1 of the highest effective 32 bits that is right after 128 bit bout keys of previous bout.

The 3rd XOR gate 118a of bout xor operation unit 117 is by carrying out following both xor operation, 32 bits that also produce 128 bit bout keys (promptly, 64 bits of the 95th bit to the) bout key RK1, be used for the deciphering of New Round: the highest effective 32 bits of 128 bit bout keys of previous bout (promptly, 96 bits of the 127th bit to the) bout key PK0, and 32 bits (that is 64 bits of the 95th bit to the) the bout key PK1 that is right after the highest effective 32 bits.

Control the 3rd multiplexer 119 of bout xor operation unit 117 according to the value of the mode signal of importing by bus 200, and optionally determine the input signal of the 3rd XOR gate 118a.

The 4th XOR gate 118b of bout xor operation unit 117 is by carrying out following both xor operation, 32 bits that produce 128 bit bout keys (promptly, 32 bits of the 63rd bit to the) bout key RK2, be used for the encryption of New Round: 32 bits of 128 bit bout keys of New Round (promptly, 64 bits of the 95th bit to the) bout key RK1, and 32 bits (that is 32 bits of the 63rd bit to the) the bout key PK2 of 128 bit bout keys of previous bout.

The 4th XOR gate 118b is by carrying out following both xor operation, 32 bits that also produce 128 bit bout keys (promptly, 32 bits of the 63rd bit to the) bout key RK2, be used for the deciphering of New Round: 32 bits of 128 bit bout keys of previous bout (promptly, 64 bits of the 95th bit to the) bout key PK1, and ensuing 32 bits (that is 32 bits of the 63rd bit to the) bout key PK2.

Control the 4th multiplexer 119a of bout xor operation unit 117 according to the value of the mode signal of importing by bus 200, and optionally determine the input signal of the 4th XOR gate 118b.

The 5th XOR gate 118c of bout xor operation unit 117 is by carrying out following both xor operation: 32 bits of 128 bit bout keys of New Round (promptly, 32 bits of the 63rd bit to the) bout key RK2, and 32 bits of 128 bit bout keys of previous bout (promptly, 0 bit of the 31st bit to the) bout key PK3,32 bits that produce 128 bit bout keys (promptly, 0 bit of the 31st bit to the) bout key RK3 is used for the encryption of New Round.

The 5th XOR gate 118c is by carrying out following both xor operation: 32 bits of 128 bit bout keys of previous bout (promptly, 32 bits of the 63rd bit to the) bout key PK2, and ensuing 32 bits (promptly, 0 bit of the 31st bit to the) bout key PK3,32 bits that also produce 128 bit bout keys (promptly, 0 bit of the 31st bit to the) bout key RK3 is used for the deciphering of New Round.

Control the 5th multiplexer 119b of bout xor operation unit 117 according to the value of the mode signal of importing by bus 200, and optionally determine the input signal of the 5th XOR gate 118c.

It is as follows that the rijndael cipher apparatus of as above constructing according to the present invention is carried out the encryption and decryption process:

At first, the encryption and decryption operation of rijndael cipher apparatus will be described with reference to Fig. 1 and 2.

If bout operation beginning carry out bout key production process so when importing key to bout key generation unit 100 by 128 initial bits of bus 200 inputs, and 128 bits input data is input to row displacement/anti-capable shift transformation unit 120.

At this moment, as defining displacement/backward shift position that the row displacement/different byte numbers are carried out in anti-capable shift transformation unit 120 in the rijndael block cipher algorithm.

If bout operation control unit 300 sends the signal of selecting high 64 bits (sel=' 1 '), row displacement so/instead go shift transformation unit 120 by high 64 bits of first multiplexer 121 outputs, if and bout operation control unit 300 sends the signal of selecting low 64 bits (sel=' 0 '), row displacement so/instead go shift transformation unit 120 by low 64 bits of first multiplexer 121 outputs.

Carry out after aforesaid byte row displacement/anti-capable shifting function, high or low 64 Bit datas are input to displacement/decommutation converter unit 130, and are carried out the displacement or the decommutation of data by displacement box (S-box) or decommutation box (SI-box).At this moment, S-box and SI-box define in the standard as the rijndael algorithm as the displacement transformation unit, byte output of its relative byte input and output.Similarly, just enough because displacement/decommutation the converter unit 130 that proposes according to the present invention is once only handled 64 Bit datas, so it only requires 8 S-boxes or 8 SI-boxes.

If import the mode signal of selecting ciphering process (pattern=' 0 ') by bus 200 after carrying out aforesaid displacement/decommutation operation, so high or low 64 Bit datas are input to row mixing/anti-row mixing transformation unit 150 by the encryption output ' 0 ' of first demodulation multiplexer 140, if and select the mode signal of decrypting processes (pattern=' 1 ') by bus 200 input, the deciphering output ' 1 ' of so high or low 64 Bit datas by first demodulation multiplexer 140 is input to and adds bout key conversion unit 170 by being listed as mixing/anti-row mixing transformation unit 150.

If select the mode signal of ciphering process (pattern=' 0 ') by bus 200 inputs, so be input to and added bout key conversion unit 170 through 64 Bit datas of the row mixing/anti-row mixing transformation unit encryption output ' 0 ' by second demodulation multiplexer 160, if import the mode signal of selecting decrypting processes (pattern=' 1 '), export the result data that 64 Bit datas are operated as bout by the deciphering output ' 1 ' of second demodulation multiplexer 160 so and pass through bus 200.

Similarly, if select the mode signal of ciphering process (pattern=' 0 ') by bus 200 inputs, result's output of operating as bout by the encryption output ' 0 ' of the 3rd demodulation multiplexer 180 through 64 Bit datas that add bout key conversion unit 170, if import the mode signal of selecting decrypting processes (pattern=' 1 ') and pass through bus 200,64 Bit datas are input to row mixing/anti-row mixing transformation unit 150 by the deciphering output ' 1 ' of the 3rd demodulation multiplexer 180.

As mentioned above, be: by sharing the use that element shared in ciphering process and the decrypting process reduces hardware resource, so each converter unit has the function of encryption and decryption because the invention is intended to.

Simultaneously, will require according to the encryption and decryption operation of rijndael cipher apparatus of the present invention and the generation of the bout key encrypting or decipher by bout key generation unit 100 being used to of carrying out with reference to figure 3 explanation.

If import 4 clocks or 3 clock bouts operation commencing signal and rounds signal to bout operating unit 100 from bout operation control unit 300, bout operation beginning so.

If bout operation beginning, bout key generation unit 110 uses the 128 bit bout keys (that is, pre-key) that are stored in the previous bout in the pre-cipher key register 111 of 128 bits so, begins to produce the bout key RK of New Round.

If select to encrypt the mode signal of (pattern=' 0 ') by bus 200 inputs, minimum effective 32 bits (PK3) of 128 bit bout keys of the previous bout of the pre-cipher key register 111 of 128 bits are input to shift unit 114 by second multiplexer 113 so.

By contrast, if select the mode signal of deciphering (pattern=' 1 ') by bus 200 inputs, the 5th XOR gate 118c carries out the low 64 bit PK2 of bout key of previous bout and the xor operation of PK3 so, and 32 bits of temporary transient storing X OR are as minimum effective 32 bit RK3 of New Round key.Simultaneously, this value RK3 is input to shift unit 114 by second multiplexer 113.

32 bit keys that are input to shift unit 114 byte that moves to left is then by displacement transformation unit 115 displacements that comprise 4 S-boxes.

As mentioned above, the highest effective 8 bit keys of 32 bit keys of displacement transformation are by first XOR gate 116 and constant value Rcon XOR (XOR), and this constant value is according to being determined by the rank of the bout of indicating from the rounds signal of bout operation control unit 300 inputs.Be added to 115 residue 24 bits of exporting from consequent 8 bits of first XOR gate 116 outputs, and the bit after the addition is input to second XOR gate 118 of bout xor operation unit 117 from the displacement transformation unit.

Especially the constant value by the wherein relevant rounds of restriction can obtain the effect that hardware size reduces during bout key production process and the part of high 8 bit XORs of having passed through 32 Bit datas of displacement transformation unit 115.For this reason, the rijndael algorithmic specification such structure: generate the constant value of the relevant rounds of 32 bits by ' 0 ' to the 8 bit constant value of filling 24 bits, carry out 32 bit constant values then and passed through the xor operation of 32 bit values of displacement transformation unit 115.

Then, second XOR gate 118 carried out following both xor operation: by 32 bits that will obtain from the residue 24 bit additions of consequent 8 bits of first XOR gate 116 outputs and 115 outputs from the displacement transformation unit, and the highest effective 32 bit PK0 of the bout key of previous bout, and the end value of storing X OR operation is as the highest effective 32 bit bout key RK0 of New Round.

Produce as mentioned above after the encryption of New Round or the highest effective 32 bit bout key RK0 that deciphering requires, the 3rd XOR gate 118a under the situation of ciphering process by carrying out following both xor operation: high 32 bits (64 bits of the 95th bit to the) the bout key PK1 of the highest effective 32 bit bout key RK0 of New Round and previous bout produces the ensuing 32 bit bout key RK1 of New Round.Under the situation of decrypting process, the 3rd XOR gate 118a is by carrying out following both xor operation: the highest effective 32 bit bout key PK0 of previous bout, and the ensuing high 32 bit bout key PK1 of previous bout, the ensuing 32 bit bout key RK1 of generation New Round.

At this moment, according to the mode signal by bus 200 inputs and indication ciphering process or decrypting process, the 3rd multiplexer 119 determined the input value of the 3rd XOR gate 118a.

Produce as mentioned above after the 32 bit bout key RK1 of the highest effective 32 bit bout key RK0 be right after New Round, produce ensuing 32 bit bout key RK2 and minimum effective 32 bit bout key RK3 are used for encrypting or deciphering by the 4th the XOR gate 118b that operates in the same manner with the 3rd XOR gate 118a and the 5th XOR gate 118c.The 4th multiplexer 119a determines the input value of the 4th XOR gate 118b, and the 5th multiplexer 119b determines the input value of the 5th XOR gate 118c.

Particularly, with 32 bits be unit produce time that 128 bit bout keys of New Round require under the situation of ciphering process corresponding to whole 4 clock cycle from the bout operation commencing signal of bout operation control unit 300 inputs, and under the situation of decrypting process corresponding to whole 2 clock cycle.

In fact, when first clock of encrypting bout operation commencing signal becomes ' 1 ', produce the highest effective 32 bit bout key RK0 of New Round by second XOR gate 118, and when no matter when second, the 3rd and the 4th clock become ' 1 ', produce 32 bit bout key RK1, RK2 and the RK3 of New Round respectively by the 3rd XOR gate 118a, the 4th XOR gate 118b and the 5th XOR gate 118c.Similarly, when first clock of deciphering bout operation commencing signal becomes ' 1 ', produce the highest effective 32 bit bout key PK0 of New Round by second XOR gate 118, and when second clock becomes ' 1 ', produce 32 bit bout key RK1, RK2 and the RK3 of New Round simultaneously by the 3rd XOR gate 118a, the 4th XOR gate 118b and the 5th XOR gate 118c.

Operating commencing signal under the situation of bout operating unit 100 from bout operation control unit 300 inputs 3 clock bouts, bout key generation unit 110 produced during 2 clock cycle encrypts the bout key.

At this moment, when first clock of bout operation commencing signal becomes ' 1 ', carry out the process of the highest effective 32 bits (that is 96 bits of the 127th bit to the) bout key RK0 of the 128 bit bout keys that produce New Round.

If second clock of bout operation commencing signal becomes ' 1 ', so by carrying out following both xor operation: the highest effective 32 bits of 128 bit bout keys of New Round (promptly, 96 bits of the 127th bit to the) bout key RK0 and the 32 bit bout key PK1 of the highest effective 32 bits that are right after 128 bit bout keys of previous bout, 32 bits (that is 64 bits of the 95th bit to the) the bout key RK1 that the 3rd XOR gate 118a produces 128 bit bout keys is used for the encryption of New Round.

Simultaneously, by carrying out following both xor operation: end value (RK0

PK1)---this end value is by the highest effective 32 bits of 128 bit bout keys of New Round (promptly, 96 bits of the 127th bit to the) 32 bits of bout key RK0 and the highest effective 32 bit bout keys of the 128 bit bout keys that are right after previous bout (promptly, 64 bits of the 95th bit to the) xor operation of the 3rd XOR gate of bout key PK1 obtains---and 32 bits of previous bout are (promptly, 32 bits of the 63rd bit to the) bout key PK2,32 bits (that is 32 bits of the 63rd bit to the) the bout key RK2 that the 4th XOR gate 118b produces 128 bit bout keys is used for the encryption of New Round.

Simultaneously, by carrying out following both xor operation: end value (RK0

PK1)---this end value is by by the 3rd XOR gate 118a XOR, the highest effective 32 bits of 128 bit bout keys of New Round (promptly, 96 bits of the 127th bit to the) bout key RK0, with 32 bits of the highest effective 32 bit bout keys of the 128 bit bout keys that are right after previous bout (promptly, 64 bits of the 95th bit to the) bout key PK1, the xor operation that carries out the 4th XOR gate obtains---and 32 bits of previous bout are (promptly, 32 bits of the 63rd bit to the) bout key PK2, thereby the end value (RK0 of generation xor operation

PK1

PK2), then by execution result value (RK0

PK1

PK2) and 32 bits of previous bout (promptly, 0 bit of the 31st bit to the) xor operation of bout key PK3,32 bits (that is 0 bit of the 31st bit to the) the bout key RK3 that the 5th XOR gate 118c produces 128 bit bout keys is used for the encryption of New Round.

Operating commencing signal under the situation of bout operating unit 100 from bout operation control unit 300 inputs 2 clock bouts, bout key generation unit 110 produced during a clock cycle encrypts the bout key.

At this moment, when input bout operation commencing signal and clock are in ' 0 ' state simultaneously, carry out the process of the highest effective 32 bits (that is 96 bits of the 127th bit to the) bout key RK0 of the 128 bit bout keys that produce New Round by second XOR gate 118.

If first clock of bout operation commencing signal becomes ' 1 ', so by carrying out following both xor operation: the highest effective 32 bits of 128 bit bout keys of New Round (promptly, 96 bits of the 127th bit to the) bout key RK0 and the 32 bit bout key PK1 of the highest effective 32 bits that are right after 128 bit bout keys of previous bout, 32 bits (that is 64 bits of the 95th bit to the) the bout key RK1 that the 3rd XOR gate 118a produces 128 bit bout keys is used for the encryption of New Round.

Simultaneously, by carrying out following both xor operation: end value (RK0 PK1)---this end value is by the highest effective 32 bits of 128 bit bout keys of New Round (promptly, 96 bits of the 127th bit to the) 32 bits of bout key RK0 and the highest effective 32 bit bout keys of the 128 bit bout keys that are right after previous bout (promptly, 64 bits of the 95th bit to the) xor operation of the 3rd XOR gate of bout key PK1 obtains---and 32 bits of previous bout are (promptly, 32 bits of the 63rd bit to the) bout key PK2,32 bits (that is 32 bits of the 63rd bit to the) the bout key RK2 that the 4th XOR gate 118b produces 128 bit bout keys is used for the encryption of New Round.

Simultaneously, by carrying out following both xor operation: end value (RK0 PK1)---this end value is by by the 3rd XOR gate 118a XOR, the highest effective 32 bits of 128 bit bout keys of New Round (promptly, 96 bits of the 127th bit to the) bout key RK0, with 32 bits of the highest effective 32 bit bout keys of the 128 bit bout keys that are right after previous bout (promptly, 64 bits of the 95th bit to the) bout key PK1, the xor operation that carries out the 4th XOR gate obtains---and 32 bits of previous bout are (promptly, 32 bits of the 63rd bit to the) bout key PK2, thereby the end value (RK0 of generation xor operation

PK1 PK2), then by execution result value (RK0 PK1

Operating commencing signal under the situation of bout operating unit 100 from bout operation control unit 300 inputs 2 clock bouts, bout key generation unit 110 produces deciphering bout key during a clock cycle.

If first clock of bout operation commencing signal becomes ' 1 ', so by carrying out following both xor operation: the ensuing high 32 bit PK1 of the highest effective 32 bit PK0 of previous bout and previous bout, the 3rd XOR gate 118a produces the ensuing 32 bit bout key RK1 of New Round, and next the 4th XOR gate 118b and the 5th the XOR gate 118c that operates in the same manner with the 3rd XOR gate 118a produces the ensuing 32 bit bout key RK2 and the minimum effective 32 bit bout key RK3 that are used to decipher.During first clock cycle, carry out these processes simultaneously.

Now, the clock number according to the bout operation commencing signal that is input to bout operating unit 100 from bout operation control unit 300 will illustrate in greater detail the operation of the rijndael cipher apparatus of carrying out the encryption and decryption process as mentioned above.

With reference to figure 4, if from bout operation control unit 300 input four clock bouts operation commencing signal and rounds signal to bout operating unit 100 (step S400), become for ' 1 ' the moment so at first clock, high 64 Bit datas about 128 bit bouts operation input data, carry out byte shift conversion and replacement operator (step S401) continuously, and these two processes are carried out in a clock.The result of these processes is stored in the 64 Bit data registers 400.Similarly, first clock of operating commencing signal at bout becomes for ' 1 ' the moment, uses 128 bit bout key production processes of 128 bit bouts input key to begin (step S401a).

Second clock at bout operation commencing signal becomes for ' 1 ' the moment, the row mixing transformation that use is stored in 64 Bit datas in the 64 Bit data registers 400 utilizes its end value that is stored in the 64 Bit data registers 400 to carry out (step S402), carries out the byte shift conversion and the replacement operator (step S402) of low 64 Bit datas of bout operation input data simultaneously continuously.These two processes are carried out in a clock.Equally, the result data of the byte shift conversion of low 64 Bit datas and replacement operator is stored in low 64 bit positions of 128 Bit data registers 500 of storage bout operating result.

The 3rd clock at bout operation commencing signal becomes for ' 1 ' the moment, being stored in 64 bits in the 64 Bit data registers 400 is input to and adds bout key conversion unit 170, so that be added to high 64 bits of the bout key that produces by bout key generation unit 110, and end value is stored in high 64 bit positions (step S403) of 128 Bit data registers 500.And low 64 Bit datas of 128 Bit data registers 500 are also carried out the row mixing transformation, and end value is stored in low 64 bit positions (step S403) of 128 Bit data registers 500.

The 4th clock at bout operation commencing signal becomes for ' 1 ' the moment, low 64 bits of 128 Bit data registers 500 are input to and add bout key conversion unit 170, so that be added to low 64 bits of the bout key that is produced by bout key generation unit 110, and end value is stored in low 64 bit positions (step S404) of 128 Bit data registers 500.

Therefore, in the rijndael cipher apparatus of carrying out above-mentioned ciphering process, 128 Bit datas of 128 Bit data registers 500 are as the 128 bit bouts operation input data of next bout, and the bout key RK that is stored in then among the 128 bit bout cipher key register 111a by the 110 new generations of bout key generation unit also is stored in the 128 bit bouts input key that is used as next bout in the pre-cipher key register 111 of 128 bits.Therefore, in the cycle of four clocks, finish the cryptographic operation of one bout.

Carried out by rijndael cipher apparatus according to the present invention as under the situation of encryption method illustrated in fig. 4, bout key generation unit 110 is finished bout key production process in the cycle of four clocks of bout operation commencing signal.That is, as shown in Figure 4, after the 3rd clock of bout operation beginning, execution adds bout key conversion process (step S403), and it is the process with high 64 Bit datas and the addition of bout key.After second clock of bout operation beginning, only produce the high 64 bit bout keys of New Round, and this moment is because only use high 64 bit bout keys, so it is no problem to carry out the cryptographic operation of bout operation.Similarly, because it is consistent with the time point that produces all 128 bit bout keys to be used for the 3rd clock the 4th time point that clock begins afterwards of bout operation, so it is no problem that execution adds bout key conversion process (step S404), this process will be hanged down 64 Bit datas and low 64 bit bout key additions.

Similarly, in the rijndael cipher apparatus of carrying out above-mentioned ciphering process, 64 Bit data registers 400 are as the memory space of the intermediate data that produces during the ciphering process, and therefore the result of the byte shift conversion of high 64 Bit datas does not influence the byte shift conversion of low 64 Bit datas.Similarly, because high 64 Bit datas and the conversion simultaneously of low 64 Bit datas, but not conversion in the same manner during the identical clock cycle, so the number of the hardware module that conversion requires can reduce by half.Particularly, be updated to the data of each clock generating and be stored in the memory space, therefore do not require extra memory space.That is the such structure of this situation guiding: it is used pipeline organization but is not required extra hardware, and this structure will be applied to the method for the encryption and decryption rijndael block encryption according to other embodiments of the present invention that will illustrate subsequently in the same manner.

With reference to figure 5, if from bout operation control unit 300 input four clock bouts operation commencing signal and rounds signal to bout operating unit 100 (step S500), become for ' 1 ' the moment so at first clock, high 64 Bit datas about 128 bit bouts operation input data are carried out byte backward shift bit map and decommutation operation (step S501) continuously, and these two processes are carried out in a clock.At this moment, result data is stored in the 64 Bit data registers 400.Similarly, if first clock of bout operation commencing signal becomes ' 1 ', use 128 bit bout key production processes of 128 bit bouts input key to begin (step S501a).

Second clock at bout operation commencing signal becomes for ' 1 ' the moment, execution adds the bout key conversion, the high 64 bit additions that are used for being stored in 64 Bit datas of 64 Bit data registers 400 and pass through the bout key of bout key generation unit 110 generations, and result data is stored in the 64 Bit data registers 400 (step S502).Carry out simultaneously the byte backward shift bit map and the decommutation of low 64 Bit datas of bout operation input data continuously, and result data is stored in low 64 bit positions (step S502) of 128 Bit data registers.

The 3rd clock at bout operation commencing signal becomes for ' 1 ' the moment, 64 Bit datas that are stored in the 64 Bit data registers 400 are input to row mixing/anti-row mixing transformation unit 150, and the result data of anti-row mixing transformation is stored in high 64 bit positions (step S503) of 128 Bit data registers 500.Carry out simultaneously and add the bout key conversion, be used for will be low 64 Bit datas and the bout key addition that produces from bout key generation unit 110 by the decommutation operation, and result data is stored in low 64 bit positions (step S503) of 128 Bit data registers.

The 4th clock at bout operation commencing signal becomes for ' 1 ' the moment, be input to row mixing/anti-row mixing transformation unit 150 and carry out anti-row mixing transformation, and result data is stored in low 64 bit positions (step S504) of 128 Bit data registers 500 by low 64 Bit datas that add the bout key conversion.

At this moment, 128 Bit datas of 128 Bit data registers 500 are as the 128 bit bouts operation input data of next deciphering bout operation, and the result's who produces as the bout key 128 bit bout key RK are stored in the pre-cipher key register 111 of 128 bits, so that as the 128 bit bouts input key of next bout operation.Therefore, in the cycle of four clocks, finish the decryption oprerations of one bout.

Carried out by rijndael cipher apparatus according to the present invention as under the situation of decryption method illustrated in fig. 5, bout key generation unit 110 is finished bout key production process in the cycle of two clocks of bout operation commencing signal.Promptly, as shown in Figure 5, because after second clock of bout operation beginning, execution adds bout key conversion process, it is the process (step S502) with high 64 bit bout keys and 64 Bit data additions, so the time point at second clock has produced all 128 bit bout keys, it is no problem therefore to carry out the bout operation.

With reference to figure 6, if from bout operation control unit 300 input three clock bouts operation commencing signal and rounds signal to bout operating unit 100 (step S600), become for ' 1 ' the moment so at first clock, carry out the byte shift operation and the replacement operator of high 64 Bit datas continuously, and result data is stored in the 64 Bit data registers (step S601).Similarly, carry out bout key production process (step S601a) simultaneously.

Second clock at bout operation commencing signal becomes for ' 1 ' the moment, and the row mixing transformation is stored in 64 Bit datas in the 64 Bit data registers 400, is added to the high 64 bit bout keys of the result data of bout key conversion unit 110 then.The result data that adds the bout key conversion is stored in the 64 Bit data registers 400 (step S602).Simultaneously, carry out the byte shift conversion and the replacement operator of low 64 Bit datas continuously, and result data is stored in low 64 bit positions (step S602) of 128 Bit data registers 500.

The 3rd clock at bout operation commencing signal becomes for ' 1 ' the moment, be stored in 64 Bit datas in the 64 Bit data registers 400 and be input to high 64 bit positions of 128 Bit data registers 500, and low 64 Bit datas of row mixing transformation 128 Bit data registers 500 are added to the low 64 bit bout keys by the bout key of bout key generation unit 110 generations then.Result data is stored in low 64 bit positions (step S603) of 128 Bit data registers 500.

At this moment, 128 Bit datas of 128 Bit data registers 500 are as the 128 bit bouts operation input data of next bout operation, and the bout key RK that is produced by bout key generation unit 110 is stored in the pre-cipher key register 111 of 128 bits, imports key as 128 bit bouts of next bout then.Therefore, in the cycle of three clocks, finish the cryptographic operation of one bout.

Carried out by rijndael cipher apparatus according to the present invention as under the situation of encryption method illustrated in fig. 6, bout key generation unit 110 is finished bout key production process in the cycle of two clocks of bout operation commencing signal.Promptly, as shown in Figure 6, because after second clock of bout operation beginning, execution adds bout key conversion process (step S602), it is the process with high 64 bit bout keys and high 64 Bit data additions, so the time point at second clock has produced all 128 bit bout keys, it is no problem therefore to carry out the bout operation.

With reference to figure 7, if from bout operation control unit 300 input three clock bouts operation commencing signal and rounds signal to bout operating unit 100 (step S700), become for ' 1 ' the moment so at first clock, high 64 Bit datas about 128 bit bouts operation input data are carried out byte backward shift bit map and decommutation operation continuously, and result data is stored in the 64 Bit data registers 400 (step S701).Similarly, bout key production process and these conversion begin (step S701a) simultaneously.

When second clock of bout operation commencing signal becomes ' 1 ', execution adds the bout key conversion, be used for to be stored in the high 64 bit bout key additions of 64 Bit datas with the bout key that produces by bout key generation unit 110 of 64 Bit data registers 400, and result data is input to row mixing/anti-row mixing transformation unit 150.The storage of anti-row mixing transformation is in 64 Bit data registers 400 (step S702).Simultaneously, carry out the byte backward shift bit map and the decommutation conversion of low 64 Bit datas of bout operation input data continuously, and result data is stored in low 64 bit positions (step S702) of 128 Bit data registers.

The 3rd clock at bout operation commencing signal becomes for ' 1 ' the moment, be stored in 64 Bit datas in the 64 Bit data registers 400 and be stored in high 64 bit positions of 128 Bit data registers 500, and execution adds the bout key conversion, is used for the low 64 bit bout key additions with low 64 Bit datas and the bout key generation unit 110 of 128 Bit data registers 500.Then, anti-row mixing transformation adds the result data of bout key conversion, and the result data of anti-row mixing transformation is stored in low 64 bit positions (step S703) of 128 Bit data registers.

At this moment, 128 Bit datas of 128 Bit data registers 500 are as the 128 bit bouts operation input data of next bout operation, and the 128 bit bout key RK that produced by bout key generation unit 110 are stored in the pre-cipher key register 111 of 128 bits, so that import key as 128 bit bouts of next bout operation.Therefore, in the cycle of three clocks, finish the decryption oprerations of one bout.

Carried out by rijndael cipher apparatus according to the present invention as under the situation of decryption method illustrated in fig. 7, bout key generation unit 110 is finished bout key production process in the cycle of two clocks of bout operation commencing signal.Promptly, as shown in Figure 7, because after second clock of bout operation beginning, execution adds bout key conversion process (step S702), be used for high 64 bit bout keys and high 64 Bit data additions, so the time point at second clock has produced all 128 bit bout keys, it is no problem therefore to carry out the bout operation.

With reference to figure 8, if from bout operation control unit 300 input two clock bouts operation commencing signal and rounds signal to bout operating unit 100 (step S800), so when first clock becomes ' 1 ', high 64 Bit datas about bout input data are carried out byte shift conversion, displacement transformation, row mixing transformation continuously and are added the bout key conversion, and result data is stored in the 64 Bit data registers 400 (step S801).Carry out bout key production process (step S801a) simultaneously, and the high 64 bit bout keys of the bout key that carry out to produce add the bout key conversion.These processes were carried out in the cycle of a clock.

When second clock of bout operation commencing signal becomes ' 1 ', low 64 Bit datas about bout input data are carried out byte shift conversion, displacement transformation, row mixing transformation continuously and are added the bout key conversion, and result data is stored in hanging down in 64 bit positions (step S802) of 128 Bit data registers 500.Similarly, carry out the bout key that produces in the bout key production process low 64 bit bout keys add the bout key conversion.At this moment, 64 Bit datas that are stored in the 64 Bit data registers 400 are stored in high 64 bit positions of 128 Bit data registers 500, and the 110 new 128 bit bout key RK that produce are stored among the 128 bit bout cipher key register 111a by bout key generation unit, and backup is in the pre-cipher key register 111 of 128 bits.Therefore, in the cycle of two clocks, finish the cryptographic operation of one bout.

Carried out by rijndael cipher apparatus according to the present invention as under the situation of encryption method illustrated in fig. 8, bout key generation unit 110 is finished bout key production process in the cycle of a clock of bout operation commencing signal.Promptly, as shown in Figure 8, because after first clock of bout operation beginning, execution adds bout key conversion process (step S801), be used for high 64 bit bout keys and high 64 Bit data additions, so the time point at first clock has produced all 128 bit bout keys, it is no problem therefore to carry out the bout operation.

In fact, use RK0 to produce RK1, use RK1 to produce RK2 as bout key generation unit 110 illustrated in fig. 3.Bout key generation unit 110 does not use RK2 to produce RK3, but produces RK0 in following state: input bout operation commencing signal and clock become ' 0 ' simultaneously.When first clock became ' 1 ', bout key generation unit 110 produced RK1 by XOR RK0 and PK1 simultaneously, by XOR RK0 and PK1 and PK2 generation RK2, and by XOR RK0 and PK1, PK2 and PK3 generation RK3.

With reference to figure 9, if from bout operation control unit 300 input two clock bouts operation commencing signal and rounds signal to bout operating unit 100 (step S900), so when first clock becomes ' 1 ', high 64 Bit datas about bout input data are carried out byte backward shift bit map, decommutation conversion continuously, are added bout key conversion and anti-row mixing transformation, and result data is stored in the 64 Bit data registers 400 (step S901).These processes were carried out in the cycle of a clock.Carry out bout key production process (step S901a) simultaneously and be used for deciphering, and carry out the bout key that produces by bout key generation unit 110 high 64 bit bout keys add the bout key conversion.

When second clock of bout operation commencing signal becomes ' 1 ', low 64 Bit datas about bout input data are carried out byte backward shift bit map, decommutation conversion continuously, are added bout key conversion and anti-row mixing transformation, and result data is stored in hanging down in 64 bit positions (step S902) of 128 Bit data registers 500.These processes were carried out in the cycle of a clock.Similarly, the low 64 bit bout keys of the bout key that is produced by bout key generation unit 110 before clock are used to add the bout key conversion.At this moment, 64 Bit datas that are stored in the 64 Bit data registers 400 are stored in high 64 bit positions of 128 Bit data registers 500, and the 110 new 128 bit bout key RK that produce are stored among the 128 bit bout cipher key register 111a by bout key generation unit, and backup is in the pre-cipher key register 111 of 128 bits.Therefore, in the cycle of two clocks, finish the decryption oprerations of one bout.

Carried out by rijndael cipher apparatus according to the present invention as under the situation of decryption method illustrated in fig. 9, bout key generation unit 110 is finished bout key production process in the cycle of a clock of bout operation commencing signal.Promptly, as shown in Figure 9, after first clock of bout operation beginning, execution adds bout key conversion process (step S901), be used for high 64 bit bout keys and high 64 Bit data additions, but the time point at first clock has produced all 128 bit bout keys, and it is no problem therefore to carry out the bout operation.

In fact, produce RK0 as bout key generation unit 110 illustrated in fig. 3 in following state: input bout operation commencing signal and while clock become ' 0 '.When first clock became ' 1 ', bout key generation unit 110 produced RK1 by XOR RK0 and PK1 simultaneously, produced RK2 by XOR PK1 and PK2, and produced RK3 by XOR PK2 and PK3.

As mentioned above, according to as the rijndael cipher apparatus of encryption method illustrated in fig. 8 and decryption method illustrated in fig. 9 is the model that is fit to be applied to smart card, USIM (user's subscriber identity module) card, SIM card etc., its size is little, have low-power consumption and low operating frequency characteristic.

Utilizability on the industry

From top explanation as seen, according to rijndael cipher apparatus of the present invention and encrypting/decrypting method thereof, by being installed in portable terminal such as cell phone and PDA or the smart card, encryption and decryption at high speed require the significant data of fail safe, this portable terminal requires high-speed and undersized cipher processor, and can carry out the bout operation about high 64 bits and low 64 bits cut apart from 128 bits input data.The present invention has following effect:

The first, encryption apparatus according to the present invention has little size, and can be by repeatedly use bout operating equipment, encrypt/decrypt real time data at high speed in device.

Second, because use the bout operating equipment encrypt/decrypt block encryption data in real time of using the rijndael algorithm according to encryption apparatus according to the present invention, so compare with the operating equipment of using existing DES (data encryption standard), it can provide more senior fail safe.

The 3rd, have following advantage according to the rijndael encrypt/decrypt bout operating equipment of encryption apparatus of the present invention: by increasing the simple controller that repeats bout operation pre-determined number, it is encrypt/decrypt block encryption data in real time.

The 4th, according to the bout operating equipment of encryption apparatus of the present invention fast encrypt/data decryption in real time, though it has little size, this size almost be existing be half of size of the bout operating equipment of unit with 128 bits.

The 5th, can use the suitable method of application to realize according to the bout operating equipment of encryption apparatus of the present invention according to it, and under the situation that is applied to the system that does not consider the hardware resource quantity used, be the pass process of unit rather than be the pass process of unit that by using it can obtain the high data encryption/decryption speed of twice with 64 bits with 128 bits.

The embodiment of front is exemplary, and is not interpreted as limiting the present invention.This instruction can easily be applied to the device of other type.Explanation of the present invention is intended to illustrative, does not limit the scope of the claims.To those skilled in the art, much alternative, modifications and variations will be obvious.

Claims

1. auspicious grace Dorr block encryption device, have 128 bits input data and 128 bits input key, and operate and encrypt 128 bits input data by carrying out bout, this bout operation comprises that row displacement, displacement, row mix and add the conversion of bout key, and this device comprises:

The bout operating unit, be used for 128 bits input key is converted to the 128 bit bout keys that are used to encrypt, and after input cryptographic operation commencing signal and mode signal, input bout operation commencing signal, rounds signal and bit select signal to be used for that 128 bits input data are divided into high 64 bits and low 64 bits and when selecting high or low 64 bits, store 128 bit bout keys according to the value of mode signal, and by 128 bits input data being divided into high 64 bits and low 64 bits, and, encrypt 128 bits input data by respectively high 64 bits and low 64 bits cut apart being carried out the bout operation;

The bout operation control unit, when being used for from input cryptographic operation commencing signal and mode signal, be divided into high 64 bits and low 64 bits and select the bit of high or low 64 bits to select signal, bout operation commencing signal and rounds signal to send to the bout operating unit by being used for that 128 bits are imported data, control the bout operation of bout operating unit;

64 Bit data registers, high 64 bits that are used to store each bout operating period generation of being carried out by the bout operating unit are imported the intermediate cryptographic data of data; And

128 Bit data registers, be used to store low 64 bits of the intermediate cryptographic data of the low 64 bits input data that each bout operating period of being carried out by the bout operating unit produces, and storage produces and is stored in enciphered data in the 64 Bit data registers as its high 64 Bit datas as the result of last bout operation as it.

2. auspicious grace Dorr piece decryption device, have 128 bits input data and 128 bits input key, and operate and decipher 128 bits input data by carrying out bout, this bout operation comprises anti-capable displacement, decommutation, adds bout key and anti-row mixing transformation, and this device comprises:

The bout operating unit, be used for 128 bits input key is converted to the 128 bit bout keys that are used to decipher, and after input decryption oprerations commencing signal and mode signal, input bout operation commencing signal, rounds signal and bit select signal to be used for that 128 bits input data are divided into high 64 bits and low 64 bits and when selecting high or low 64 bits, store 128 bit bout keys according to the value of mode signal, and by 128 bits input data being divided into high 64 bits and low 64 bits, and, decipher 128 bits input data by respectively high 64 bits and low 64 bits cut apart being carried out the bout operation;

The bout operation control unit, when being used for from input decryption oprerations commencing signal and mode signal, be divided into high 64 bits and low 64 bits and select the bit of high or low 64 bits to select signal, bout operation commencing signal and rounds signal to send to the bout operating unit by being used for that 128 bits are imported data, control the bout operation of bout operating unit;

64 Bit data registers are used to store the intermediate solution ciphertext data of the high 64 bits input data of each bout operating period generation of being carried out by the bout operating unit; And

128 Bit data registers, be used to store low 64 bits of the intermediate solution ciphertext data of the low 64 bits input data that each bout operating period of being carried out by the bout operating unit produces, and storage produces and is stored in data decryption in the 64 Bit data registers as its high 64 Bit datas as the result of last bout operation as it.

3. Rijndael block cipher apparatus, have 128 bits input data and 128 bits input key, and operate by the bout that execution is used to encrypt and to encrypt or to decipher 128 bits inputs data, this bout that is used to encrypt operation comprises that row displacement, displacement, row mix and add the conversion of bout key, perhaps the bout that is used to decipher by execution is operated and is deciphered 128 bits input data, this bout that is used to decipher operation comprises anti-capable displacement, decommutation, adds bout key and anti-row mixing transformation, and this device comprises:

The bout operating unit, be used for 128 bits input key is converted to the 128 bit bout keys that are used to encrypt or decipher, and after input encryption or decryption oprerations commencing signal and mode signal, input bout operation commencing signal, rounds signal and bit select signal to be used for that 128 bits input data are divided into high 64 bits and low 64 bits and when selecting high or low 64 bits, store 128 bit bout keys according to the value of mode signal, by 128 bits input data being divided into high 64 bits and low 64 bits, and by respectively high 64 bits and low 64 bits cut apart being carried out the bout operation that is used to encrypt, encrypt 128 bits input data, and by 128 bits input data being divided into high 64 bits and low 64 bits, and respectively high 64 bits and low 64 bits cut apart are carried out the bout operation that is used to decipher, decipher 128 bits input data;

The bout operation control unit, when being used for from input encryption or decryption oprerations commencing signal and mode signal, be divided into high 64 bits and low 64 bits and select the bit of high or low 64 bits to select signal, bout operation commencing signal and rounds signal to send to the bout operating unit by being used for that 128 bits are imported data, control the bout operation of bout operating unit;

64 Bit data registers are used to store the intermediate cryptographic or the data decryption of the high 64 bits input data of each bout operating period generation of being carried out by the bout operating unit; And

128 Bit data registers, be used to store the intermediate cryptographic of the low 64 bits input data that each bout operating period of being carried out by the bout operating unit produces or data decryption low 64 bits, and storage produces and is stored in encryption in the 64 Bit data registers or data decryption high 64 Bit datas as it as the result of last bout operation as it.

4. device according to claim 3, wherein said bout operating unit comprises:

Bout key generation unit, if from bout operation control unit input bout operation commencing signal and rounds signal, just basis is by the value of the mode signal of bus input, 128 bits input key is converted to 128 bit bout key RK is used for encrypting or deciphering, and in inner 128 bit bout cipher key register, store 128 bit bout keys;

Row displacement/anti-capable shift transformation unit, if select signal from bout operation control unit input bout operation commencing signal and bit, just basis is by the value of the mode signal of bus input, execution is from high 64 bits of cutting apart by the 128 bits input data of bus input and the anisomerous byte shift that hangs down 64 bits, and, select the value of signal to control the output of this multiplexer according to bit by high 64 bits and low 64 bits of first multiplexer output byte displacement;

Displacement/decommutation converter unit, use relative byte input that the displacement box (S-box) or the decommutation box (SI-box) of a byte output are provided, carry out from row displacement/high 64 Bit datas of anti-capable shift transformation unit output and the displacement or the decommutation of low 64 Bit datas;

First demodulation multiplexer, according to the value of mode signal, by it the encryption output and its deciphering output in any one, output is from high 64 Bit datas of displacement/decommutation converter unit output or hang down 64 Bit datas;

Row mixing/anti-row mixing transformation unit, carry out high 64 Bit datas of the encryption output input by first demodulation multiplexer or the row of low 64 Bit datas and mix, perhaps carry out high 64 Bit datas that added the bout key conversion or the anti-row of low 64 Bit datas and mix;

Second demodulation multiplexer, according to the value of mode signal, by it the encryption output and its deciphering output in any one, output is from high 64 Bit datas of row mixings/anti-row mixing transformation unit output or hang down 64 Bit datas;

Add bout key conversion unit, be used for high 64 Bit datas or low 64 Bit datas of the encryption output input of the deciphering output by first demodulation multiplexer or second demodulation multiplexer are added to from the 128 bit bout key RK that are used to encrypt or decipher of bout key generation unit output; And

The 3rd demodulation multiplexer, according to the value of mode signal, by it the encryption output and its deciphering output in any one, high 64 Bit datas or low 64 Bit datas of output from adding the output of bout key conversion unit.

5. auspicious grace Dorr block encryption method comprises following steps:

If after bus input cryptographic operation commencing signal and mode signal, import four clock bouts operation commencing signal and rounds signal from the bout operation control unit, the value of the mode signal of importing by bus when becoming ' 1 ' according to first clock so from bout operation commencing signal, the bout key generation unit of bout operating unit is converted to 128 bit bout keys with 128 bits input key and is used for encrypting, and stores 128 bit bout keys in inner 128 bit bout cipher key register;

If import four clock bouts operation commencing signal and bit selection signal from the bout operation control unit, so when first clock becomes ' 1 ', the byte shift by high 64 Bit datas of the 128 bits input data of bus input is carried out in row displacement/anti-capable shift transformation unit, and high 64 Bit datas by first multiplexer output byte displacement, and displacement/decommutation converter unit is carried out the displacement of high 64 Bit datas continuously, high 64 Bit datas of output displacement are to first demodulation multiplexer, and high 64 Bit datas of storage displacement in 64 Bit data registers;

When second clock of bout operation commencing signal becomes ' 1 ', the row mixing of exporting and being stored in high 64 Bit datas in the 64 Bit data registers by the encryption output of first demodulation multiplexer is carried out in row mixing/anti-row mixing transformation unit, high 64 Bit datas to the second demodulation multiplexer of output row mixing transformation, and high 64 Bit datas of memory row mixing transformation in 64 Bit data registers, row displacement/anti-capable shift transformation unit is carried out the byte shift by low 64 Bit datas of the 128 bits input data of bus input simultaneously, and low 64 Bit datas by first multiplexer output byte displacement, and displacement/decommutation converter unit is carried out the displacement of low 64 Bit datas continuously, low 64 Bit datas of output displacement are to first demodulation multiplexer, and low 64 Bit datas of storage displacement in low 64 bits of 128 Bit data registers;

When the 3rd clock of bout operation commencing signal becomes ' 1 ', add bout key conversion unit and will be added to the high 64 bit bout keys that produce by bout key generation unit by the encryption output output of second demodulation multiplexer and high 64 Bit datas that are stored in the 64 Bit data registers, and high 64 Bit datas of storage addition in high 64 bits of 128 Bit data registers, and row mixing/anti-row mixing transformation unit is carried out the row mixing of exporting and being stored in low 64 Bit datas in the 128 Bit data registers by the encryption output of first demodulation multiplexer simultaneously, low 64 Bit datas to the second demodulation multiplexer of output row mixing transformation, and in low 64 bits of 128 Bit data registers low 64 Bit datas of memory row mixing transformation; And

When the 4th clock of bout operation commencing signal becomes ' 1 ', adding bout key conversion unit will be added to the low 64 bit bout keys that produced by bout key generation unit by the encryption output output of second demodulation multiplexer and low 64 Bit datas that are stored in the 128 Bit data registers, and low 64 Bit datas of storage addition in low 64 bits of 128 Bit data registers.

6. encryption method according to claim 5, wherein in value according to the mode signal of importing by bus, bout key generation unit is converted to 128 bit bout keys with 128 bits input key and is used for encrypting, and the step of storage 128 bit bout keys in inner 128 bit bout cipher key register produces 128 bit bout keys and is used for encrypting in the cycle of four clocks of bout operation commencing signal.

7. auspicious grace Dorr piece decryption method comprises following steps:

If after bus input decryption oprerations commencing signal and mode signal, import four clock bouts operation commencing signal and rounds signal from the bout operation control unit, the value of the mode signal of importing by bus when becoming ' 1 ' according to first clock so from bout operation commencing signal, the bout key generation unit of bout operating unit is converted to 128 bit bout keys with 128 bits input key and is used for deciphering, and stores 128 bit bout keys in inner 128 bit bout cipher key register;

If import four clock bouts operation commencing signal and bit selection signal from the bout operation control unit, so when first clock becomes ' 1 ', the byte backward shift position by high 64 Bit datas of the 128 bits input data of bus input is carried out in row displacement/anti-capable shift transformation unit, and high 64 Bit datas by first multiplexer output byte backward shift position, and displacement/decommutation converter unit is carried out the decommutation of high 64 Bit datas continuously, high 64 Bit datas of output decommutation arrive first demodulation multiplexer, and store high 64 Bit datas of decommutation in 64 Bit data registers;

When second clock of bout operation commencing signal becomes ' 1 ', add bout key conversion unit and will be added to the high 64 bit bout keys that produce by bout key generation unit by the deciphering output output of first demodulation multiplexer and high 64 Bit datas that are stored in the 64 Bit data registers, three demodulation multiplexers of high 64 Bit datas to the of output addition, and high 64 Bit datas of storage addition in 64 Bit data registers, row displacement/anti-capable shift transformation unit is carried out the byte backward shift position by low 64 Bit datas of the 128 bits input data of bus input simultaneously, and low 64 Bit datas by first multiplexer output byte backward shift position, and displacement/decommutation converter unit is carried out the decommutation of low 64 Bit datas continuously, low 64 Bit datas of output decommutation arrive first demodulation multiplexer, and store low 64 Bit datas of decommutation in low 64 bits of 128 Bit data registers;

When the 3rd clock of bout operation commencing signal becomes ' 1 ', the anti-row mixing of exporting and being stored in high 64 Bit datas in the 64 Bit data registers by the deciphering output of the 3rd demodulation multiplexer is carried out in row mixing/anti-row mixing transformation unit, export high 64 Bit datas of anti-row mixing transformation by second demodulation multiplexer, and high 64 Bit datas of the anti-row mixing transformation of storage in high 64 bits of 128 Bit data registers, and add bout key conversion unit and will be added to the low 64 bit bout keys that produce by bout key generation unit by the deciphering output output of first demodulation multiplexer and low 64 Bit datas that are stored in the 128 Bit data registers simultaneously, by low 64 Bit datas of the 3rd demodulation multiplexer output addition, and low 64 Bit datas of storage addition in low 64 bits of 128 Bit data registers; And

When the 4th clock of bout operation commencing signal becomes ' 1 ', the anti-row mixing of exporting and being stored in low 64 Bit datas in the 128 Bit data registers by the deciphering output of the 3rd demodulation multiplexer is carried out in row mixing/anti-row mixing transformation unit, export low 64 Bit datas of anti-row mixing transformation by second demodulation multiplexer, and in low 64 bits of 128 Bit data registers, store low 64 Bit datas of anti-row mixing transformation.

8. according to the decryption method described in the claim 7, wherein according to the value of the mode signal by bus input, bout key generation unit 128 bits input key is being converted to that 128 bit bout keys are used for deciphering and in the step of inner 128 bit bout cipher key register storage, 128 bit bout keys, in the cycle of two clocks of bout operation commencing signal, is producing the 128 bit bout keys that are used to decipher.

9. auspicious grace Dorr block encryption method comprises step:

If after bus input cryptographic operation commencing signal and mode signal, import three clock bouts operation commencing signal and rounds signal from the bout operation control unit, the value of the mode signal of importing by bus when becoming ' 1 ' according to first clock so from bout operation commencing signal, the bout key generation unit of bout operating unit is converted to 128 bit bout keys with 128 bits input key and is used for encrypting, and stores 128 bit bout keys in inner 128 bit bout cipher key register;

If import three clock bouts operation commencing signal and bit selection signal from the bout operation control unit, so when first clock becomes ' 1 ', the byte shift by high 64 Bit datas of the 128 bits input data of bus input is carried out in row displacement/anti-capable shift transformation unit, and high 64 Bit datas by first multiplexer output byte displacement, and displacement/decommutation converter unit is carried out the displacement of high 64 Bit datas continuously, high 64 Bit datas of output displacement are to first demodulation multiplexer, and high 64 Bit datas of storage displacement in 64 Bit data registers;

When second clock of bout operation commencing signal becomes ' 1 ', the row mixing of exporting and being stored in high 64 Bit datas in the 64 Bit data registers by the encryption output of first demodulation multiplexer is carried out in row mixing/anti-row mixing transformation unit, and high 64 Bit datas to the second demodulation multiplexer of output row mixing transformation, add bout key conversion unit and continuously these high 64 Bit datas are added to the high 64 bit bout keys that produced by bout key generation unit, and high 64 Bit datas of storage addition in 64 Bit data registers, row displacement/anti-capable shift transformation unit is carried out the byte shift by low 64 Bit datas of the 128 bits input data of bus input simultaneously, and low 64 Bit datas by first multiplexer output byte displacement, and displacement/decommutation converter unit is carried out the displacement of low 64 Bit datas continuously, low 64 Bit datas of output displacement are to first demodulation multiplexer, and low 64 Bit datas of storage displacement in low 64 bits of 128 Bit data registers; And

When the 3rd clock of bout operation commencing signal becomes ' 1 ', 64 Bit datas that addition is stored in the 64 Bit data registers then are stored in high 64 bits of 128 Bit data registers, row mixing/anti-row mixing transformation unit is carried out the row mixing of exporting and being stored in low 64 Bit datas in the 128 Bit data registers by the encryption output of first demodulation multiplexer simultaneously, and low 64 Bit datas to the second demodulation multiplexer of output row mixing transformation, and add bout key conversion unit and will hang down 64 Bit datas continuously and be added to the low 64 bit bout keys that produce by bout key generation unit, and low 64 Bit datas of storage addition in low 64 bits of 128 Bit data registers.

10. encryption method according to claim 9, wherein according to the value of the mode signal by bus input, bout key generation unit 128 bits input key is being converted to that 128 bit bout keys are used for encrypting and in the step of inner 128 bit bout cipher key register storage, 128 bit bout keys, in the cycle of two clocks of bout operation commencing signal, is producing the 128 bit bout keys that are used to encrypt.

11. an auspicious grace Dorr piece decryption method comprises following steps:

If after bus input decryption oprerations commencing signal and mode signal, import three clock bouts operation commencing signal and rounds signal from the bout operation control unit, the value of the mode signal of importing by bus when becoming ' 1 ' according to first clock so from bout operation commencing signal, the bout key generation unit of bout operating unit is converted to 128 bit bout keys with 128 bits input key and is used for deciphering, and stores 128 bit bout keys in inner 128 bit bout cipher key register;

If import three clock bouts operation commencing signal and bit selection signal from the bout operation control unit, so when first clock becomes ' 1 ', the byte backward shift position by high 64 Bit datas of the 128 bits input data of bus input is carried out in row displacement/anti-capable shift transformation unit, and high 64 Bit datas by first multiplexer output byte backward shift position, and displacement/decommutation converter unit is carried out the decommutation of high 64 Bit datas continuously, high 64 Bit datas of output decommutation arrive first demodulation multiplexer, and store high 64 Bit datas of decommutation in 64 Bit data registers;

When second clock of bout operation commencing signal becomes ' 1 ', add bout key conversion unit and will be added to the high 64 bit bout keys that produce by bout key generation unit by the deciphering output output of first demodulation multiplexer and high 64 Bit datas that are stored in the 64 Bit data registers, and three demodulation multiplexers of high 64 Bit datas to the of output addition, the anti-row that row mixing/anti-row mixing transformation unit is carried out high 64 Bit datas of addition continuously mix, export high 64 Bit datas of anti-row mixing transformation by second demodulation multiplexer, and high 64 Bit datas of the anti-row mixing transformation of storage in 64 Bit data registers, row displacement/anti-capable shift transformation unit is carried out the byte backward shift position by low 64 Bit datas of the 128 bits input data of bus input simultaneously, and low 64 Bit datas by first multiplexer output byte backward shift position, and displacement/decommutation converter unit is carried out the decommutation of low 64 Bit datas continuously, low 64 Bit datas of output decommutation arrive first demodulation multiplexer, and store low 64 Bit datas of decommutation in low 64 bits of 128 Bit data registers; And

When the 3rd clock of bout operation commencing signal becomes ' 1 ', add bout key conversion unit and will be added to the low 64 bit bout keys that produce by bout key generation unit by the deciphering output output of first demodulation multiplexer and low 64 Bit datas that are stored in the 128 Bit data registers, and low three demodulation multiplexers of 64 Bit datas to the of output addition, the anti-row that row mixing/anti-row mixing transformation unit is carried out low 64 Bit datas of addition continuously mix, export low 64 Bit datas of anti-row mixing transformation by second demodulation multiplexer, and low 64 Bit datas of the anti-row mixing transformation of storage in low 64 bits of 128 Bit data registers, high 64 Bit datas that will be stored in simultaneously in the 64 Bit data registers are stored in high 64 bits of 128 Bit data registers.

12. according to the decryption method described in the claim 11, wherein according to the value of the mode signal by bus input, bout key generation unit 128 bits input key is being converted to that 128 bit bout keys are used for deciphering and in the step of inner 128 bit bout cipher key register storage, 128 bit bout keys, in the cycle of two clocks of bout operation commencing signal, is producing the 128 bit bout keys that are used to decipher.

13. an auspicious grace Dorr block encryption method comprises following steps:

If after bus input cryptographic operation commencing signal and mode signal, import two clock bouts operation commencing signal and rounds signal from the bout operation control unit, the value of the mode signal of importing by bus when becoming ' 1 ' according to first clock so from bout operation commencing signal, the bout key generation unit of bout operating unit is converted to 128 bit bout keys with 128 bits input key and is used for encrypting, and stores 128 bit bout keys in inner 128 bit bout cipher key register;

If import two clock bouts operation commencing signal and bit selection signal from the bout operation control unit, so when first clock becomes ' 1 ', the byte shift by high 64 Bit datas of the 128 bits input data of bus input is carried out in row displacement/anti-capable shift transformation unit, and high 64 Bit datas by first multiplexer output byte displacement, displacement/decommutation converter unit is carried out the displacement of high 64 Bit datas continuously, high 64 Bit datas of output displacement are to first demodulation multiplexer, and high 64 Bit datas by first demodulation multiplexer output displacement, the row that row mixing/anti-row mixing transformation unit is carried out by high 64 Bit datas of the encryption output output of first demodulation multiplexer mix, and high 64 Bit datas to the second demodulation multiplexer of output row mixing transformation, and add bout key conversion unit and continuously these high 64 Bit datas are added to the high 64 bit bout keys that produce by bout key generation unit, and high 64 Bit datas of storage addition in 64 Bit data registers; And

When second clock of bout operation commencing signal becomes ' 1 ', the byte shift by low 64 Bit datas of the 128 bits input data of bus input is carried out in row displacement/anti-capable shift transformation unit, and low 64 Bit datas by first multiplexer output byte displacement, and displacement/decommutation converter unit is carried out the displacement of low 64 Bit datas continuously, and low 64 Bit datas of output displacement are to first demodulation multiplexer, the row that row mixing/anti-row mixing transformation unit is carried out low 64 Bit datas continuously mix, and low 64 Bit datas to the second demodulation multiplexer of output row mixing transformation, add bout key conversion unit and continuously these low 64 Bit datas are added to the low 64 bit bout keys that produced by bout key generation unit, and low 64 Bit datas of storage addition in low 64 bits of 128 Bit data registers, high 64 Bit datas that will be stored in simultaneously in the 64 Bit data registers are stored in high 64 bits of 128 Bit data registers.

14. according to the encryption method described in the claim 13, wherein according to the value of the mode signal by bus input, bout key generation unit 128 bits input key is being converted to that 128 bit bout keys are used for encrypting and in the step of inner 128 bit bout cipher key register storage, 128 bit bout keys, in the cycle of a clock of bout operation commencing signal, is producing the 128 bit bout keys that are used to encrypt.

15. an auspicious grace Dorr piece decryption method comprises following steps:

If after bus input decryption oprerations commencing signal and mode signal, import two clock bouts operation commencing signal and rounds signal from the bout operation control unit, the value of the mode signal of importing by bus when becoming ' 1 ' according to first clock so from bout operation commencing signal, the bout key generation unit of bout operating unit is converted to 128 bit bout keys with 128 bits input key and is used for deciphering, and stores 128 bit bout keys in inner 128 bit bout cipher key register;

If import two clock bouts operation commencing signal and bit selection signal from the bout operation control unit, so when first clock becomes ' 1 ', the byte backward shift position by high 64 Bit datas of the 128 bits input data of bus input is carried out in row displacement/anti-capable shift transformation unit, and high 64 Bit datas by first multiplexer output byte backward shift position, displacement/decommutation converter unit is carried out the decommutation of high 64 Bit datas continuously, and high 64 Bit datas of output decommutation are to first demodulation multiplexer, add bout key conversion unit and will be added to the high 64 bit bout keys that produce by bout key generation unit by high 64 Bit datas that the deciphering output of first demodulation multiplexer is exported continuously, and three demodulation multiplexers of high 64 Bit datas to the of output addition, and the anti-row that row mixing/anti-row mixing transformation unit is carried out high 64 Bit datas of addition continuously mix, export high 64 Bit datas of anti-row mixing transformation by second demodulation multiplexer, and in 64 Bit data registers, store high 64 Bit datas of anti-row mixing transformation; And

When second clock of bout operation commencing signal becomes ' 1 ', the byte backward shift position by low 64 Bit datas of the 128 bits input data of bus input is carried out in row displacement/anti-capable shift transformation unit, and low 64 Bit datas by first multiplexer output byte backward shift position, displacement/decommutation converter unit is carried out the decommutation of low 64 Bit datas continuously, and low 64 Bit datas of output decommutation are to first demodulation multiplexer, add bout key conversion unit and will be added to the low 64 bit bout keys that produce by bout key generation unit by low 64 Bit datas that the deciphering output of first demodulation multiplexer is exported continuously, and low three demodulation multiplexers of 64 Bit datas to the of output addition, the anti-row that row mixing/anti-row mixing transformation unit is carried out low 64 Bit datas of addition continuously mix, export low 64 Bit datas of anti-row mixing transformation by second demodulation multiplexer, and low 64 Bit datas of the anti-row mixing transformation of storage in low 64 bits of 128 Bit data registers, high 64 Bit datas that will be stored in simultaneously in the 64 Bit data registers are stored in high 64 bits of 128 Bit data registers.

16. decryption method according to claim 15, wherein according to the value of the mode signal by bus input, bout key generation unit 128 bits input key is being converted to that 128 bit bout keys are used for deciphering and in the step of inner 128 bit bout cipher key register storage, 128 bit bout keys, in the cycle of a clock of bout operation commencing signal, is producing the 128 bit bout keys that are used to decipher.