CN1831799A - Direct memory access controller and method for data transfer using it - Google Patents
Direct memory access controller and method for data transfer using it Download PDFInfo
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Abstract
A direct storage access controller is prepared as adding hard disc logic circuit supporting address rolling function in of traditional direct storage access controller to make traditional direct storage access controller be direct storage access controller supporting said rolling function in order to let direct storage access controller carry out data transmission in address - rolling mode.
Description
Technical Field
The present invention relates to a memory access technology, and more particularly, to a Direct Memory Access (DMA) controller having an address WRAP function (WRAP) and a method for implementing data transfer between a source address and a destination address using the same.
Background
DMA can realize the data transmission and exchange among different areas of the memory space, and the DMA controller completes all control without the intervention of a CPU in the memory access process.
Fig. 1 shows a block diagram of a conventional DMA controller. Wherein,
the bus Slave (Slave) interface unit 101 is connected with the CPU, and the CPU configures the control logic of the DMA and the control parameters of the register set unit 103 through the interface to implement the control function of various working modes of the DMA;
the DMA request and response interface unit 102 is used to process DMA request and response signals transmitted sequentially from the memory to the peripheral, from the peripheral to the memory, and from the peripheral to the peripheral through the bus Master interface unit 105, the channel logic and register set unit 104, or directly through the bus Master interface unit 105, and interact with the CPU;
the channel logic and register group unit 104 is connected with the bus Master interface unit 105 through a data line and an address line, and is configured by the CPU through the bus Slave interface unit 101, so as to realize parameter setting of each channel of the DMA, and each channel is independent of each other, and is respectively provided with a group of special registers and control logic, so as to allow different access control and transmission of different contents;
the bus Master interface unit 105 is used for connecting with peripheral equipment and/or a memory and realizing data transmission of a storage space hooked on the address bus through a data line;
the interrupt request logic unit 106 is configured to notify the CPU to query the channel logic and the relevant registers in the register set unit to implement corresponding control when the channel logic in the DMA controller has a channel transmission end or failure, so as to complete information and data interaction between the DMA controller and the CPU.
As shown in fig. 2, fig. 2 is a block diagram of a channel in the channel logic and register set unit 104, which includes a first-in-first-out (FIFO) buffer 201 connected to the bus Master interface unit 105 through a data line to implement buffering of input data; the source address control logic unit 203 is controlled by the source address control signal output by the channel control logic unit 202 to control the source address, for example: 8/16/32 bit address access, whether the address increases after one access, the number of reads, etc., the data read from the source address is sent to the DMA channel and buffered in the FIFO buffer 201; a destination address control logic unit 204, which is controlled by a destination address control signal output by the channel control logic unit 202 to control a destination address, and sends data buffered in the fifo buffer 201 to the destination address through the DMA channel and the bus Master interface unit 105; the channel control logic 202 also outputs FIFO address control signals, such as FIFO depth settings, to the FIFO buffer 201, and also outputs interrupt signals to the interrupt logic requesting unit 106.
The data transfer between the source address and the destination address realized by the DMA, the source address and the destination address can be a memory or a peripheral. When accessing a source or destination address of a memory, before transferring a single byte or block of data each time, a CPU needs to initialize a DMA controller to determine a channel selection, a data transfer mode, a first address of a memory area, a total number of bytes transferred, and the like of a current transfer. The external access address of the DMA controller is fixed, and the termination of data transmission is controlled by a transmission byte register in the DMA controller; the access address to the memory is increased or decreased, and the termination of the data transmission is controlled by an external signal.
As shown in fig. 3, fig. 3 is a schematic diagram illustrating data transmission between a source address and a destination address implemented by a DMA, with the source address as an external device and the destination address as an internal memory as an example; the destination address comprises a first storage space destination address and a second storage space destination address, and the external device usually comprises an asynchronous first-in first-out (FIFO) buffer; the solid line is the data flow and the dashed line is the control flow. The specific transfer process is as follows:
a) when the DMA request and response interface unit 102 in the DMA controller receives a signal from a request/response from an external device, the DMA request and response interface unit 102 sends the signal to the CPU, and the CPU initializes, i.e., configures, in an interrupt service program of the DMA controller, a destination address of a transfer, such as a first memory space destination address, a source address, and corresponding control parameters, such as a channel selection of a current transfer, a data transfer mode, a total number of bytes transferred, and the like; after the initialization is completed, the DMA controller becomes a Master, and under the control of the channel logic and register set unit 104, the peripheral data is sent to the memory, for example, the first storage space, through the bus Master interface unit 105;
b) when the data from the peripheral equipment is completely transferred and needs to be sent to another specified memory space such as a second memory space, the DMA controller terminates the DMA transfer;
c) when the DMA request and response interface unit 102 in the DMA controller receives the signal from the peripheral request/response again, the DMA request and response interface unit 102 sends the signal to the CPU, and the CPU reconfigures the destination address of the transfer data, such as the second memory space destination address, the source address, and the corresponding control parameters, in the interrupt service program of the DMA controller; after the initialization is completed, under the control of the channel logic and register set unit 104, the peripheral data is sent to the memory, for example, the destination address of the second memory space, through the bus Master interface unit 105, and when the peripheral data is completely transferred and needs to be sent to another specified memory space, for example, the first memory space, the DMA controller terminates the DMA transfer;
and repeating the steps a to c until the data required to be transmitted in the peripheral equipment is transmitted.
While the DMA controller is transferring data from the peripheral to the second memory space, the CPU may process the data stored to the first memory space, i.e. the DMA controller transferring data is operated in parallel with the CPU processing the data already stored at the destination address.
As can be seen from the above data transfer process, two separate memory addresses are usually required to improve the concurrency of each process, which results in requiring the CPU to configure the transfer address in the interrupt service routine of the DMA every time the memory address is switched. If each memory address is too small, the CPU is frequently interrupted, the efficiency of the CPU is reduced, and the response time of the DMA is increased; if each memory address is too large, the processing delay of signals is increased, the response speed of the system is reduced, the memory space is wasted, and the area and the cost of a chip are increased.
Disclosure of Invention
The invention aims to provide a DMA controller to reduce the frequent intervention of a CPU on the DMA controller. Another object of the present invention is to provide a method for implementing data transfer by using the DMA controller, so as to solve the problem that the existing DMA controller needs the CPU to frequently intervene in the DMA controller during the data transfer process.
The technical scheme of the invention is realized as follows:
a DMA controller for direct memory access comprises a bus slave interface unit, a control logic and register group unit, a bus master interface unit, a direct memory access request and response interface unit, a channel logic and register group unit connected with the bus master interface unit through a data line and an address line, and an interrupt request logic unit; wherein,
the channel logic and register unit comprises a channel control logic unit connected with the bus main interface unit through the address line, a first-in first-out buffer area controlled by a first-in first-out address signal output by the channel control logic unit and used for buffering data from the bus main interface unit through the data line, an address control logic unit controlled by the address signal output by the channel control logic unit and used for providing a read-write address for the bus main interface unit,
the channel logic and register group unit also comprises a winding control register and an address winding logic control unit, wherein the winding control register respectively outputs an address winding boundary and an address winding enable;
the address winding logic control unit converts an address winding boundary output by the winding control register into a winding end address under address winding enabling control, compares the winding end address with the current address of the address line, and outputs a control signal for setting the current address as a winding head address to the address control logic unit when the winding end address is equal to the current address.
Preferably, the address wrap logic control unit comprises,
a wrap-around address converting circuit for converting an address wrap-around boundary outputted from the wrap-around control register into a wrap-around address transition signal, which is outputted after being anded with the address wrap-around enable;
and a first comparison circuit for comparing the current address with the output of the last wrap-around address conversion circuit, and outputting a control signal for setting the current address as a wrap-around start address when the last wrap-around address is equal to the current address.
Preferably, the address wrap logic control unit further converts an address wrap boundary output by the wrap control register into a wrap intermediate address, the wrap intermediate address being compared with the current address, and outputs a wrap interrupt signal to the interrupt request logic unit when the wrap intermediate address is equal to the current address and when the wrap end address is equal to the current address.
Preferably, the address wrap logic control unit further comprises,
a winding middle address conversion circuit for converting the address winding boundary output by the winding control register into a winding middle address transition signal under the address winding enable control, and outputting the winding middle address transition signal and the address winding enable phase and phase;
a second comparison circuit for comparing the wrap-around intermediate address output by the wrap-around intermediate address circuit with the current address and outputting a first high voltage indication when the wrap-around intermediate address is equal to the current address;
a third comparison circuit that compares the last wrap-around address output by the last wrap-around address with the current address and outputs a second high voltage indication when the last wrap-around address is equal to the current address;
and a winding interruption generating circuit which outputs a winding interruption signal by performing an OR operation of the first high voltage instruction and the second high voltage instruction.
Preferably, the address wrap boundary and the address wrap enable output by the wrap control register are a source address wrap boundary and a source address wrap enable, respectively, the address wrap logic control unit is a source address wrap logic control unit, and the address control logic unit is a source address control logic unit that is controlled by a source address signal output by the channel control logic unit to provide a source address to the bus master interface unit.
Preferably, the address wrap boundary and the address wrap enable output by the wrap control register are a destination address wrap boundary and a destination address wrap enable, respectively, the address wrap logic control unit is a destination address wrap logic control unit, and the address control logic unit is a destination address control logic unit that is controlled by a destination address signal output by the channel control logic unit to provide a destination address to the bus master interface unit.
Preferably, the address wrap boundaries output by the wrap control register are a source address wrap boundary and a destination address wrap boundary respectively, the output address wrap enables are a source address wrap enable and a destination address wrap enable respectively, the address wrap logic control unit comprises a source address wrap logic control unit and a destination address wrap logic control unit, the address control logic unit comprises a source address control logic unit which is controlled by a source address signal output by the channel control logic unit to provide a source address to the bus master interface unit, and a destination address control logic unit which is controlled by a destination address signal output by the channel control logic unit to provide a destination address to the bus master interface unit.
Preferably, the wrap-around intermediate address value is half the address wrap-around length.
Preferably, the wrap control register and the address wrap logic control unit correspond to one DMA channel.
A method for implementing data transfer using the direct memory access controller of claim 1, comprising,
A) the CPU configures the address winding boundary and the address winding enable of the direct memory access controller, the CPU judges whether a direct memory access request exists, if so, the step B is executed; otherwise, waiting;
B) judging whether the address winding enable is effective or not, and if so, executing the step C; if the address winding enable is invalid, before the direct memory access controller transmits data each time, the CPU executes interrupt, and reconfigures the direct memory access controller in an interrupt program until the data to be transmitted are transmitted;
C) and C, the direct memory access controller transmits data and judges whether the current address is equal to a winding end address obtained by the direct memory access controller through conversion of a winding boundary, if so, the direct memory access controller sets the current address as a winding initial address, the step C is returned until the data to be transmitted are transmitted, otherwise, the step C is directly returned until the data to be transmitted are transmitted.
Preferably, the step C further includes determining whether the current address is equal to a winding middle address converted by the direct memory access controller from a winding boundary, and if the current address is equal to the winding middle address or the current address is equal to a winding end address, the direct memory access controller outputs an interrupt signal to the CPU.
Preferably, the address wrap boundary and the address wrap enable are a source address wrap boundary and a source address wrap enable, respectively, or a destination address wrap boundary and a destination address wrap enable, or the address wrap boundary comprises a source address wrap boundary and a destination address wrap boundary, and the address wrap enable comprises a source address wrap enable and a destination address wrap enable.
The invention adds a hardware logic circuit supporting the function of address Winding (WRAP) on the basis of the existing DMA controller, so that the traditional DMA controller becomes the DMA controller supporting the function of WRAP, and solves the problem that the existing DMA controller needs CPU intervention to reconfigure the parameters of the DMA controller when reading or writing data in a memory.
Drawings
FIG. 1 shows a block diagram of a prior art DMA controller;
FIG. 2 is a block diagram of a channel in channel logic and register set unit 104;
FIG. 3 is a diagram illustrating data transfer between a source address and a destination address by a DMA, using the source address as a peripheral and the destination address as a memory as an example;
FIG. 4 is a block diagram of the channel logic and register file unit of the present invention;
FIG. 5 is a diagram of the hardware logic circuit added to a DMA channel to implement source address wrapping in a conventional DMA controller according to the present invention;
FIG. 6 is a diagram illustrating control bit information of the wrap control register;
FIG. 7 is a flow chart of the DMA controller according to the present invention.
Detailed Description
The invention adds a hardware logic circuit supporting the function of address WRAP-around (WRAP) in the existing traditional DMA controller, so that the traditional DMA controller becomes the DMA controller supporting the function of WRAP, which is called the address WRAP-around DMA controller (WDMA) for short, and the DMA controller can transmit data in the way of address WRAP-around, that is, when the current address to be accessed reaches the address boundary, the address to be accessed WRAPs around in the set length, and the length of the WRAP-around is 2 in generalNAnd N is a positive integer. For example, 16 bytes are used as the boundary of the address wrap. If the current access address is 0x80000008, the CPU will access the following addresses in turn:
0x80000008-0x8000000f，0x80000000-0x80000007
since the address space to be accessed is 16 bytes, at the boundary of the address (when the content of the 8-byte address is read), i.e. at 0x8000000f, the address is read from 0x80000000 next time, and the content of the remaining 8-byte address is read until 0x 80000007. The DMA controller transmits data in an address winding mode, on one hand, a CPU can use the latest Cache content, meanwhile, hardware can continue to update the Cache content, and the overall performance of the system is improved by concurrent hardware work.
Referring to fig. 4, fig. 4 is a block diagram of a channel logic and register set unit according to the present invention. Different from the existing channel logic and register set unit, the channel control logic unit 202 outputs a control signal to the address control logic unit when the current address reaches the winding boundary, so as to set the current address as the winding start address, and further, outputs a winding interrupt signal to the interrupt request logic unit 106 in the DMA controller, so as to notify the CPU that the existing part of the data transmitted by the CPU can be refreshed. Here, the source address may be only wrapped, the destination address may be only wrapped, or both the source address and the destination address may be wrapped.
As shown in fig. 5, fig. 5 is a diagram of a hardware logic circuit for implementing source address wrapping added to a DMA channel in a conventional DMA controller according to the present invention. The system comprises a winding control register and a source address winding logic control unit, wherein the winding control register corresponds to the control attribute of a DMA channel, and each control bit information is as shown in FIG. 6: the 0 th bit is a source address winding enable bit, the 1 st bit is a destination address winding enable bit, the default value is 0, 1 represents that the enable is effective, and 0 represents that the disable is effective; the 2 nd bit to the 5 th bit are source address winding boundaries, the information is significant when a source address winding enable bit is 1, the 6 th bit to the 9 th bit are destination address winding boundaries, the information is significant when a destination address winding enable bit is 1, the default values of the source address winding boundaries and the destination address winding boundaries are 0001, 0000 represents 8 bytes WRAP, 0001 represents 16 bytes WRAP, 0010 represents 32 bytes WRAP, 0011 represents 64 bytes WRAP, 0100 represents 128 bytes AP, 0101 and 1111 reservations; the 10 th bit to the 31 th bit are reserved bits.
The source address wrap-around logic control unit includes a conversion unit constituted by a wrap-around end address conversion circuit, a first comparison circuit, a second comparison circuit, a third comparison circuit, and a wrap-around interruption generation circuit. Preferably, the conversion unit further comprises a wrap-around intermediate address conversion circuit, and the conversion portions of the wrap-around last address conversion circuit and the wrap-around intermediate address conversion circuit may share one conversion logic unit (as shown in fig. 5), or use separate conversion logic units, respectively. In fig. 5, the source address wrap-around boundary output by the wrap-around control register is sent to a transition logic unit, which outputs a wrap-around end address transition signal and a wrap-around middle address transition signal, respectively, where the wrap-around end address transition signal and the source address wrap-around enable signal are input to a first and gate, respectively, which outputs a wrap-around end address; the winding intermediate address transition signal and the source address winding enable signal are respectively input into a second AND gate, and the AND gate outputs a winding intermediate address; preferably, the value of the wrap-around middle address is the wrap-around half address, i.e., if the wrap-around address is 2NN is a positive integer indicating the number of bits (number of bits) of the lower address, the wrap-around half address is 2N-1-1。
The last winding address and the current address output by the first and gate are respectively input into a first comparison circuit, when the last winding address and the current address are equal, the comparison circuit outputs a control signal for setting the current address to be equal to the first winding address, and preferably, the first winding address is set to be 0 address, and the control signal is a zero clearing signal. The winding end address and the current address output by the first AND gate are also respectively input into a third comparison circuit, and when the winding end address and the current address are equal, the comparison circuit outputs a first high level; the winding middle address and the current address output by the second AND gate are respectively input into a second comparison circuit, and when the winding middle address and the current address are equal, the comparison circuit outputs a second high level; the wrap-around interrupt generating circuit is an or gate circuit, and the first high level and the second high level are respectively input to the or gate circuit, and the high level output by the or gate circuit is sent to the active request logic unit 106 as a wrap-around interrupt signal.
The destination address winding logic control unit has the same structure as the source address winding logic control unit, except that the input of the destination address winding logic control unit is connected with the destination address winding boundary signal and the destination address winding enable signal output by the winding control register.
With a winding boundary of 128 (128-2)7N is 7), the winding start address is 0x00, and the winding middle address is the winding half address. When the winding boundary is 128, the winding start address is 0x00, the winding half address is 0x3f, the winding end address is 0x7f, and it is assumed that the access start address is 0x 40. When the DMA starts, the sequence of the access addresses is 0x40-0x7f, when 0x7f is accessed, the first comparison circuit outputs a control signal to update the current address to 0x00, and simultaneously the third comparison circuit outputs a second high level, and an interrupt signal is output through an OR gate circuit to inform a CPU that the data of 0x40-0x7f can be processed; while the CPU processes 0x40-0x7f data, the DMA controller accesses addresses in the order of 0x00-0x3 f; when 0x3f is accessed, the third comparator circuit outputs a second high level, and an interrupt signal is output through an OR gate circuit to inform the CPU that the data of 0x00-0x3f can be processed, and the DMA controller accesses addresses in the order of 0x40-0x7 f. Control of hardware logic circuits due to address wrap-aroundTherefore, the CPU only needs to configure the DMA controller once, the DMA controller can work until the data transfer is finished, the intervention of the CPU is reduced, the efficiency of the system is improved, and the design of the driving software of the DMA controller is simplified.
Referring to fig. 7, fig. 7 is a flow chart illustrating a DMA controller according to the present invention to transfer data. The following describes an example of using a source address and a destination address both as memories to transmit burst data to implement a data transmission method by using the DMA controller of the present invention.
Firstly, a CPU initializes a DMA controller, namely a source address winding boundary and a source address winding enable, a winding first source address, a winding first destination address, a destination address winding boundary and a destination address winding enable of a memory are configured, and a working mode and parameters related to a starting source address, a starting destination address, a burst transfer length, a total length of data to be transferred and the like are configured; assuming that a starting source address is 0x800000040, a starting destination address is 0x90000040, a source address wrap-around boundary and a destination address wrap-around boundary are both 128 bytes, a burst transfer length is 64 bytes, and a total transmission length is 32 × 2 × 32 bytes;
then, CPU waits for DMA request, when receiving DMA request, CPU sends response message to DMA controller, DMA controller becomes master controller, judge the value of the coiling control register, when DMA controller has function of coiling address, the address change of visiting the memory changes according to the way of coiling address, until the data that need to be transmitted are all transmitted, otherwise, visit the memory according to the mode of the prior art, namely, before transmitting a burst data each time, CPU initializes DMA controller, then visit the memory, until the data that need to be transmitted are all transmitted;
when the DMA controller becomes a master to perform current burst transfer and the CPU receives a wrap interrupt signal output by the DMA controller, the CPU can update the data of the last burst transfer so as to improve the concurrency of each process of the system.
The above process of accessing the memory in the address wrap-around manner is as follows: when the current access source address reaches the source address winding end address, the DMA controller outputs a control signal for updating the current source address to the winding head address, preferably, the source address winding head address is 0x80000000, the output control signal is a clear signal, similarly, when the current access destination address reaches the destination address winding end address, the DMA controller outputs a control signal for updating the current destination address to the winding head address, preferably, the destination address winding head address is 0x90000000, and the output control signal is a clear signal; in the second burst transfer, the DMA controller transfers the data with the source address range of 0x80000000-0x8000003f to the storage space with the destination address range of 0x90000000-0x9000003 f; in the subsequent burst transfer, the change of the access address sequentially cycles the range of address change of the first burst transfer and the second burst transfer.
In the above embodiment, the destination address wrap-around enable may also be configured to be disabled such that the change in destination address is incremented from the starting destination address, the destination address ranging from 0x90000040 to 0x900000 bf.
The following describes a method for transferring burst data from an external device to a first destination address memory and a second destination address memory respectively by using a DMA controller according to the present invention.
Firstly, a CPU initializes a DMA controller, namely a destination address winding boundary and a destination address winding enable are configured, and a working mode and relevant parameters such as an initial destination address, a burst transfer length, a total length of data to be transferred and the like are configured;
then, CPU waits for DMA request, when DMA controller receives the signal from peripheral request/response, send the signal to CPU, CPU sends the response message to DMA controller, DMA controller becomes the master controller, judge the value of the coiling control register, when DMA controller has the function of coiling address, the address change of visiting the memory changes according to the way of coiling address, until the data that need to transmit are all transferred, otherwise, visit the memory according to the mode of the prior art, namely, before transmitting a burst data each time, CPU initializes DMA controller, then visits the memory, until the data that need to transmit are all transferred;
when the DMA controller becomes a master to perform current burst transfer and the CPU receives a wrap interrupt signal output by the DMA controller, the CPU can update the data of the last burst transfer so as to improve the concurrency of each process of the system.
It can be seen from the above embodiments that the DMA controller of the present invention is used to implement data transfer, which avoids that the CPU reconfigures the DMA controller in the next burst transfer after the last burst transfer, and only needs to configure once, and greatly saves the storage space occupied by data.
Claims (12)
1. A DMA controller for direct memory access comprises a bus slave interface unit, a control logic and register group unit, a bus master interface unit, a direct memory access request and response interface unit, a channel logic and register group unit connected with the bus master interface unit through a data line and an address line, and an interrupt request logic unit; wherein,
the channel logic and register unit comprises a channel control logic unit connected with the bus main interface unit through the address line, a first-in first-out buffer area controlled by a first-in first-out address signal output by the channel control logic unit and used for buffering data from the bus main interface unit through the data line, and an address control logic unit controlled by the address signal output by the channel control logic unit and used for providing a read-write address for the bus main interface unit, and is characterized in that,
the channel logic and register group unit also comprises a winding control register and an address winding logic control unit, wherein the winding control register respectively outputs an address winding boundary and an address winding enable;
the address winding logic control unit converts an address winding boundary output by the winding control register into a winding end address under address winding enabling control, compares the winding end address with the current address of the address line, and outputs a control signal for setting the current address as a winding head address to the address control logic unit when the winding end address is equal to the current address.
2. The direct memory access controller of claim 1, wherein the address wrap logic control unit comprises,
a wrap-around address converting circuit for converting an address wrap-around boundary outputted from the wrap-around control register into a wrap-around address transition signal, which is outputted after being anded with the address wrap-around enable;
and a first comparison circuit for comparing the current address with the output of the last wrap-around address conversion circuit, and outputting a control signal for setting the current address as a wrap-around start address when the last wrap-around address is equal to the current address.
3. The dma controller according to claim 1 or 2, wherein the address wrap logic control unit further converts an address wrap boundary output by the wrap control register into a wrap intermediate address, the wrap intermediate address being compared with the current address, and outputs a wrap interrupt signal to the interrupt request logic unit when the wrap intermediate address is equal to the current address and when the wrap end address is equal to the current address.
4. The direct memory access controller of claim 3, wherein the address wrap logic control unit further comprises,
a winding middle address conversion circuit for converting the address winding boundary output by the winding control register into a winding middle address transition signal under the address winding enable control, and outputting the winding middle address transition signal and the address winding enable phase and phase;
a second comparison circuit for comparing the wrap-around intermediate address output by the wrap-around intermediate address circuit with the current address and outputting a first high voltage indication when the wrap-around intermediate address is equal to the current address;
a third comparison circuit that compares the last wrap-around address output by the last wrap-around address with the current address and outputs a second high voltage indication when the last wrap-around address is equal to the current address;
and a winding interruption generating circuit which outputs a winding interruption signal by performing an OR operation of the first high voltage instruction and the second high voltage instruction.
5. The dma controller of claim 1 or 2, wherein the address wrap boundaries and the address wrap enable output by the wrap control register are a source address wrap boundary and a source address wrap enable, respectively, and wherein the address wrap logic control unit is a source address wrap logic control unit that controls a source address signal output by the channel control logic unit to provide a source address to the bus master interface unit.
6. The DMA controller of claim 1 or 2 wherein the address wrap boundaries and address wrap enables output by the wrap control register are destination address wrap boundaries and destination address wrap enables, respectively, the address wrap logic control unit is a destination address wrap logic control unit that controls a destination address control logic unit that provides a destination address to the bus master interface unit under a destination address signal output by the channel control logic unit.
7. The DMA controller of claim 1 or 2, wherein the wrap control register outputs address wrap boundaries as a source address wrap boundary and a destination address wrap boundary, respectively, outputs address wrap enables as a source address wrap enable and a destination address wrap enable, respectively, the address wrap logic control unit comprises a source address wrap logic control unit and a destination address wrap logic control unit, the address control logic unit comprises a source address control logic unit controlled by a source address signal output by the channel control logic unit to provide a source address to the bus master interface unit, and a destination address control logic unit controlled by a destination address signal output by the channel control logic unit to provide a destination address to the bus master interface unit.
8. The DMA controller of claim 3 wherein the wrap-around intermediate address value is half the address wrap-around length.
9. The DMA controller of claim 1, wherein the wrap control register and the address wrap logic control unit correspond to a DMA channel.
10. A method for implementing data transfer using the direct memory access controller of claim 1,
A) the CPU configures the address winding boundary and the address winding enable of the direct memory access controller, the CPU judges whether a direct memory access request exists, if so, the step B is executed; otherwise, waiting;
B) judging whether the address winding enable is effective or not, and if so, executing the step C; if the address winding enable is invalid, before the direct memory access controller transmits data each time, the CPU executes interrupt, and reconfigures the direct memory access controller in an interrupt program until the data to be transmitted are transmitted;
C) and C, the direct memory access controller transmits data and judges whether the current address is equal to a winding end address obtained by the direct memory access controller through conversion of a winding boundary, if so, the direct memory access controller sets the current address as a winding initial address, the step C is returned until the data to be transmitted are transmitted, otherwise, the step C is directly returned until the data to be transmitted are transmitted.
11. The method of claim 10, wherein step C further comprises determining whether the current address is equal to a wrap-around middle address translated by the wrap-around boundary of the dma controller, and wherein the dma controller outputs an interrupt to the CPU if the current address is equal to the wrap-around middle address or the current address is equal to the wrap-around end address.
12. The method of claim 10, wherein the address wrap boundary and address wrap enable are a source address wrap boundary and a source address wrap enable, or a destination address wrap boundary and a destination address wrap enable, respectively, or wherein the address wrap boundary comprises a source address wrap boundary and a destination address wrap boundary, and wherein the address wrap enable comprises a source address wrap enable and a destination address wrap enable.
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| CNB2005100515776A CN100371918C (en) | 2005-03-07 | 2005-03-07 | Direct memory access controller and method for data transfer using it |
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| CNB2005100515776A CN100371918C (en) | 2005-03-07 | 2005-03-07 | Direct memory access controller and method for data transfer using it |
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| CN100371918C CN100371918C (en) | 2008-02-27 |
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Cited By (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101196859B (en) * | 2006-12-04 | 2010-05-12 | 中芯国际集成电路制造(上海)有限公司 | Direct access memory device and direct access memory operation method |
| CN101303677B (en) * | 2008-05-04 | 2010-06-02 | 华为技术有限公司 | Method and system for controlling accessing direct memory as well as controller |
| CN101196861B (en) * | 2006-12-07 | 2010-06-02 | 佳能株式会社 | DMA transfer control method and transfer control system |
| CN111782154A (en) * | 2020-07-13 | 2020-10-16 | 北京四季豆信息技术有限公司 | Data moving method, device and system |
| CN112306693A (en) * | 2020-11-18 | 2021-02-02 | 支付宝(杭州)信息技术有限公司 | Data packet processing method and device |
| CN114340097A (en) * | 2021-12-30 | 2022-04-12 | 合肥市芯海电子科技有限公司 | Method and device for controlling lamp strip, chip and electronic equipment |
Family Cites Families (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5155814A (en) * | 1990-08-31 | 1992-10-13 | International Business Machines Corporation | Nonsynchronous channel/dasd communication system |
| US5644784A (en) * | 1995-03-03 | 1997-07-01 | Intel Corporation | Linear list based DMA control structure |
| US6584514B1 (en) * | 1999-09-28 | 2003-06-24 | Texas Instruments Incorporated | Apparatus and method for address modification in a direct memory access controller |
| US6542940B1 (en) * | 1999-10-25 | 2003-04-01 | Motorola, Inc. | Method and apparatus for controlling task execution in a direct memory access controller |
-
2005
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Cited By (9)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101196859B (en) * | 2006-12-04 | 2010-05-12 | 中芯国际集成电路制造(上海)有限公司 | Direct access memory device and direct access memory operation method |
| CN101196861B (en) * | 2006-12-07 | 2010-06-02 | 佳能株式会社 | DMA transfer control method and transfer control system |
| CN101303677B (en) * | 2008-05-04 | 2010-06-02 | 华为技术有限公司 | Method and system for controlling accessing direct memory as well as controller |
| CN111782154A (en) * | 2020-07-13 | 2020-10-16 | 北京四季豆信息技术有限公司 | Data moving method, device and system |
| CN111782154B (en) * | 2020-07-13 | 2023-07-04 | 芯象半导体科技(北京)有限公司 | Data moving method, device and system |
| CN112306693A (en) * | 2020-11-18 | 2021-02-02 | 支付宝(杭州)信息技术有限公司 | Data packet processing method and device |
| CN112306693B (en) * | 2020-11-18 | 2024-04-16 | 支付宝(杭州)信息技术有限公司 | Data packet processing method and device |
| CN114340097A (en) * | 2021-12-30 | 2022-04-12 | 合肥市芯海电子科技有限公司 | Method and device for controlling lamp strip, chip and electronic equipment |
| CN114340097B (en) * | 2021-12-30 | 2024-07-30 | 合肥市芯海电子科技有限公司 | Method and device for controlling lamp strip, chip and electronic equipment |
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