CN1845087A - Interrupt handling method and interrupt handling apparatus - Google Patents
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Abstract
The invention relates to an intermission treating method, which arranges an intermission address register in the intermission controller. Said method comprises: A, writing the initial address of user intermission treating program at present highest priority into the intermission address register, and sending said highest priority intermission request to the CPU inner core; B, CPU inner core reads the address of said intermission address register, and executes the user intermission treating program according to said address. The invention can shorten the time that CPU inner core starts to execute the user intermission treating program, improve the efficiency that CPU inner core treats intermission request, to improve the whole property of SOC. The invention has the same execute time that from the inlet of system intermission treating program to the inlet of each user intermission treating program. And said invention can be used in general CPU inner core and SOC.
Description
Technical field
The present invention relates to the interrupt processing technology field, particularly a kind of interruption processing method and Interrupt Process device.
Background technology
Generally speaking, central processing unit (CPU) kernel all provides some to interrupt the application signal, provides two kinds of hardware interrupts application signals such as popular in the industry ARM kernel: regular interrupt application (IRQ) and interruption application (FIQ) fast.In the System on Chip/SoC (SOC) of integrated CPU core, need to handle a more than user usually and interrupt, therefore need finish the management work of look-at-me by an interruptable controller, such as interrupting functions such as permission, interrupt mask, interrupt arbitrage.Interruptable controller is given CPU core according to the look-at-me of user's demand selection limit priority and is handled.
With reference to Fig. 1, the part that relates to Interrupt Process in the system generally includes: CPU core, interruptable controller, and as other hardware module of interrupt source (be also referred to as and interrupt the user).Interrupt source proposes to interrupt application to interruptable controller, and interruptable controller is finished the management work of look-at-me, and selects the interruption application of limit priority to give CPU core according to user's demand and handle.CPU core, interrupt source and interruptable controller also link to each other with system bus by register interface, and CPU is by this system bus control interruptable controller and interrupt source corresponding hardware module.
General SOC chip, such as the S3C44B0X of Samsung based on the ARM7TDMI kernel, treatment scheme to interruption is as follows: interrupt taking place if having, then CPU core enters the system break handling procedure, this moment, which concrete interruption application was CPU core do not know to need to handle, so CPU core at first removes to read an interruption of interruptable controller status register (the IRQ Interrupt PendingStatus that registers, I_ISPR), the system break handling procedure begins to judge from the 0th of this register whether the value of current state position is effective value 1 then, if found an effective mode bit, then provide the sequence number of this mode bit, for example the 8th is that 1 sequence number is 8, the 20th is 1 to provide sequence number is 20, the base address that the size that each interrupt vector table is multiply by in this number of being is added interrupt vector table has just obtained the address of this interrupt vector, can read the address of actual user interrupt service routine from this address, CPU core is carried out this user interrupt service routine then; If judge that the value that obtains the current state position is not an effective value, then jump to next mode bit and continue to judge.
Effectively interrupt need using comparison and skip operation in the process of application in above-mentioned CPU core inquiry, skip operation can reduce the execution efficient of instruction pipelining.Therefore, said method has caused from entering the system break handling procedure to beginning to carry out the chronic of real user's interrupt handling routine, causes the inefficiency of CPU core handling interrupt application.And the execution time from the inlet of system break handling procedure to the inlet of each user's interrupt handling routine is inequality, that is the different processing time of interrupting application differs very big.
Summary of the invention
In view of this, the present invention proposes a kind of interruption processing method, in order to improve the efficient of CPU core handling interrupt application.Another object of the present invention provides a kind of Interrupt Process device, in order to improve the efficient of CPU core handling interrupt application.
According to above-mentioned purpose, the invention provides a kind of interruption processing method, this method is provided with interrupt address register in interruptable controller, and this method is further comprising the steps of:
A. the start address with user's interrupt handling routine of current highest priority interrupt application writes interrupt address register, and this highest priority interrupt application is sent to CPU core;
The B.CPU kernel reads the address in the described interrupt address register, and carries out described user's interrupt handling routine according to this address.
This method further is provided with the OIER corresponding with interrupting application in advance, interrupts application register and user's interrupt address storage unit in interruptable controller, and the start address that will interrupt user's interrupt handling routine of applying in advance writes user's interrupt address storage unit of correspondence.Further comprise before the steps A: interruptable controller receives the interruption application from interrupt source, and when judging that it is effective drawing corresponding OIER, it is effectively that corresponding interruption application register is set.The step that described in the steps A start address of user's interrupt handling routine of current highest priority interrupt application is write interrupt address register comprises: select the interruption application of limit priority in current interruption application register effectively interrupts applying for; The start address of user's interrupt handling routine of this highest priority interrupt application is write interrupt address register from user's interrupt address storage unit of correspondence.
This method further is provided with the interruption serial number register in advance in interruptable controller.Described in the steps A start address of user's interrupt handling routine of current highest priority interrupt application is comprised from the step that user's interrupt address storage unit of correspondence writes interrupt address register: the sequence number of highest priority interrupt application is write the interruption serial number register, described address is write interrupt address register from user's interrupt address storage unit of correspondence according to this sequence number.
Described user's interrupt address storage unit is user's interrupt address register or SRAM.
Described user's interrupt address storage unit is SRAM.Start address with user's interrupt handling routine of current highest priority interrupt application described in the steps A comprises from the step that SRAM writes interrupt address register: the sequence number of current highest priority interrupt application is write the interruption serial number register, calculate corresponding SRAM address according to this sequence number, the start address of user's interrupt handling routine of current highest priority interrupt application is write interrupt address register from SRAM according to this SRAM address.
Further comprise the step of removing the interruption application register corresponding after the step B with interrupting sequence number.
Further comprise judging whether interrupt the application register effective after the step B, and effectively the time execution in step A and B once more.
The present invention also provides a kind of Interrupt Process device, and this interrupt control device comprises:
The interruptable controller that comprises interrupt address register is used for the start address of user's interrupt handling routine of current highest priority interrupt application is write interrupt address register, and this highest priority interrupt application is sent to CPU core;
CPU core is used for reading described address according to described highest priority interrupt application from interrupt address register, and carries out described user's interrupt handling routine according to this address.
This device further comprises: the interrupt source that proposes to interrupt application to interruptable controller.
Described interruptable controller comprises: interrupt OIER, interruption application register, user's interrupt address storage unit of application corresponding to each, wherein whether OIER is used to be controlled at after the interruption application that receives interrupt source that the interruption application register of correspondence is set to effectively, whether interrupt the application register and be used to store corresponding interruption application and really imitate, user's interrupt address storage unit is used to store the start address of user's interrupt handling routine of corresponding interruption application; Interrupt arbiter, be used for interrupting the interruption application that the application register tables is shown the current limit priority of effective interruption application selection, the sequence number of this highest priority interrupt application is write the interruption serial number register, and this highest priority interrupt application is sent to CPU core; Interrupt serial number register, be used to store the sequence number of described highest priority interrupt application.
Described user's interrupt address storage unit is user's interrupt address register or SRAM.
From such scheme as can be seen, because the start address that interruptable controller will send to user's interrupt handling routine of the highest priority interrupt application that CPU core handles among the present invention has deposited interrupt address register in, CPU core directly reads the address in the interrupt address register and carries out user's interrupt handling routine according to this address, not needing CPU core to carry out judges and skip operation again, but realized the tediously long interrupt source selection course that former cause software is finished with hardware, shortened the time that CPU core begins to carry out user's interrupt handling routine greatly, improve the efficient of CPU core handling interrupt application, thereby improved the overall performance of SOC.In addition, use technical scheme of the present invention after, the execution time from the inlet of system break handling procedure to the inlet of each user's interrupt handling routine is identical.Because the validity that the present invention does not need successively the user to be interrupted applying for is judged, so the number that the user interrupts applying among the SOC is many more, the present invention is big more to the improvement of SOC performance.In addition, the present invention can be applied in the general CPU core and SOC, has certain ubiquity.
Description of drawings
Fig. 1 is the structural representation of general interrupt processing system.
Fig. 2 is the schematic flow sheet of first embodiment of the invention.
Fig. 3 is the structural representation of interruptable controller in the first embodiment of the invention.
Fig. 4 is the structural representation of interruptable controller in the second embodiment of the invention.
Fig. 5 is the schematic flow sheet of second embodiment of the invention.
Embodiment
For making the purpose, technical solutions and advantages of the present invention clearer, the present invention is described in more detail by the following examples.
With reference to Fig. 2, the first embodiment of the present invention may further comprise the steps:
Step 101, in interruptable controller, interrupt application for each in advance a corresponding OIER, an interruption application register and user's interrupt address register are set, in interruptable controller, also set in advance and interrupt serial number register and interrupt address register.
According to the interruptable controller of above-mentioned setting as shown in Figure 3.With reference to Fig. 3, interruptable controller comprises OIER, interrupts applying for register, user's interrupt address register, interrupts serial number register, interrupt address register and interrupt arbiter.As known in those skilled in the art, the steering logic that self is all arranged in the register usually is to finish control operations such as reading and writing, judgement, in embodiments of the present invention, the control operation of each register is all finished by the steering logic of self, repeats no more when specifically describing.
Wherein, whether OIER allows the interruption application register of correspondence to be set to effectively after being controlled at the interruption application that receives interrupt source, promptly whether allow corresponding interruption application effective, if OIER is invalid, then interruptable controller will can not be provided with corresponding interruption application register for effective, if OIER is effective, then interruptable controller receives that corresponding interruption application register to be set after the corresponding interruption application effective, so that follow-uply should interrupt applying for sending to CPU core.Whether interruption application register is used for storing corresponding interruption application effective.Generally the time of keeping from the interruption application signal of interrupt source can be not oversize, so interruptable controller need be applied for the interruption of correspondence to storing, so that interruptable controller and CPU core are carried out follow-up processing.User's interrupt address register is used to store the start address of user's interrupt handling routine of corresponding interruption application.For instance, for can handling 256 interruptable controllers that interrupt applying for, 256 OIER need be set altogether, if the data width of CPU core is 32, then need these registers are divided into 8 32 bit registers, need to be provided with 256 in addition and interrupt the application register, need be divided into 8 32 bit registers to these registers equally, also need to be provided with user's interrupt address register of 256 32.
The interruption serial number register is used for storing the sequence number of current highest priority interrupt application.Interrupt address register is used for storing the initial address of user's interrupt handling routine of current highest priority interrupt application, and this address is from the user interrupt address register corresponding with the highest priority interrupt application.For can handling 256 interruptable controllers that interrupt applying for, the interruption serial number register is an eight bit register, and interrupt address register is 32 bit registers.
In addition, interrupt arbiter in the interruptable controller is used for interrupting the interruption application that the application register tables is shown effective interruption application selection limit priority, the sequence number of this highest priority interrupt application is write the interruption serial number register, and send this interruption application to CPU core.
Step 102, when the SOC chip reset, the register that is provided with in the initialization step 101 is invalid with all initialization of register for example.Wherein, if all OIER all are in disarmed state, interrupt the application register so and can ignore all interruption applications.Can with all user's interrupt address registers all initialization point to invalid address.
Step 103, each interrupts the corresponding user's interrupt address register of application in the CPU core configure interrupt controller, is about to each reference position of interrupting user's interrupt handling routine of application and writes corresponding user's interrupt address register.If CPU core does not use certain to interrupt, can not dispose corresponding user's interrupt address register.
CPU core also in the configure interrupt controller each to interrupt the corresponding OIER of application effective, allow corresponding interruption user to send and interrupt application to CPU core.If CPU core does not use certain to interrupt, can not dispose corresponding OIER.
CPU core has disposed after the interruptable controller, can move its normal application program.
Step 104 is to step 106, interruptable controller receives the interruption application of certain interrupt source, interrupt application register controlled logic determines and interrupt applying for this whether corresponding OIER is effective, if, corresponding interruption application register then is set for effective, otherwise execution in step 104 is waited for receiving the next application of interrupting.
In addition, if when in step 104, receiving a plurality of interruption application simultaneously, judge respectively whether each interrupts the corresponding OIER of application effective, if effectively, corresponding interruption application register then is set for effective, otherwise execution in step 104 waits for that receiving next the interruption applies for.
Step 107, be in " non-interruption " state at interruptable controller and interrupt the application register and have one at least when effective, interrupt arbiter is effectively interrupted application to all and is arbitrated, and selects to obtain the interruption application of current limit priority, with as the system break application to the CPU core transmission.
Can whether judge effectively whether interruptable controller is in " non-interruption " state by the system break application signal of judging interrupt arbiter output, for example system break application signal low level is effective, so when this signal is high level, interruptable controller is in " non-interruption " state, and promptly interruptable controller can interrupt application to CPU core output; When if this signal is low level, interruptable controller is in " interruption " state, the interruptable controller that is in " interruption " state will can not arbitrated other interruption application, even the interruption application of higher priority is arranged, also arbitrate no longer again, till interruptable controller is got back to " non-interruption " state.One status register also can be set represent that current interruptable controller is in " interruption " state or " non-interruption " state.
Step 108, interrupt arbiter deposits the sequence number of described highest priority interrupt application in the interruption serial number register, and sends this highest priority interrupt application to CPU core.For example, be highest priority interrupt if interrupt 0, then interrupting serial number register is 0; Be highest priority interrupt if interrupt 31, then interrupting serial number register is 31; Be highest priority interrupt if interrupt 255, then interrupting serial number register is 255.The interrupt address register steering logic is according to the interruption application serial of interrupting in the serial number register simultaneously, address in user's interrupt address register of current highest priority interrupt application correspondence is written in the interrupt address register, and the initial address of user's interrupt handling routine of this interruption application has been represented in this address.
Step 109, if CPU core allows to interrupt, then change the executive system interrupt handling routine over to, read the address in the interrupt address register, change this address over to and carry out corresponding user's interrupt handling routine code, this user's interrupt handling routine is carried out and is finished in the retrieval system interrupt handling routine of back.
Step 110, CPU core read the interruption serial number register, and the value of interrupting serial number register is write back in the interruption serial number register, so that remove the value of corresponding interruption application register.
Step 111, behind the interruption application register of removing correspondence, interruptable controller enters " non-interruption " state.Whether effective, if effectively, then represent the current interruption that also has other in the waiting for CPU kernel processes, execution in step 107 if judge interrupting the application register; Otherwise execution in step 104 is waited for and is received new interruption application.
In the first embodiment of the present invention, adopt user's interrupt address register as user's interrupt address storage unit, store the start address that each interrupts user's interrupt handling routine of application.If it is many to interrupt the quantity of application, for example there are 256, then need the register of 256 * 32=8K size to store these addresses, the register of 8K position need take bigger area, and causes chip cost than higher.Therefore, for the cost that reduces the shared area of interruptable controller and reduce chip, the present invention has further proposed second embodiment.In a second embodiment, the register array that adopts static easy assess memorizer (SRAM) to replace a plurality of user's interrupt address registers among first embodiment to form.For example, if the start address of using 256 * 32 register array to store user's interrupt handling routine among first embodiment, the start address that then adopts one 256 * 32 SRAM to store user's interrupt handling routine among second embodiment.
The interruptable controller of second embodiment of the invention as shown in Figure 4.With reference to Fig. 4, this interruptable controller comprises OIER, interrupts application register, SRAM, interruption serial number register, interrupt address register and interrupt arbiter.As previously mentioned, different with first embodiment is that second embodiment adopts the SRAM storage to interrupt the start address of user's interrupt handling routine of application; Remainder is identical with first embodiment, repeats no more here.For instance, for can handling 256 interruptable controllers that interrupt applying for,, then need to be provided with 256 * 32 SRAM if the data width of CPU core is 32.
When this SRAM of configuration, be that CPU is when writing user's interrupt handling routine start address of each interruption, the register address that the SRAM steering logic provides according to CPU calculates corresponding SRAM address, and according to the SRAM address of correspondence user's interrupt handling routine start address that CPU provides is write among the SRAM.When sending current highest priority interrupt application to CPU core, the SRAM steering logic calculates the address of SRAM according to the sequence number in the interruption serial number register, from SRAM, reading out data, write interrupt address register as corresponding user's interrupt handling routine start address.
With reference to Fig. 5, interrupt applying for to be example to have 256, the flow process of second embodiment of the invention may further comprise the steps:
Step 201 is interrupted application for each in advance corresponding an OIER and an interruption application register is set in interruptable controller.The start address of using one 256 * 32 SRAM to store 256 user's interrupt handling routines in the interruptable controller simultaneously.This SRAM maps directly on the cpu i/f of register of interruptable controller, generates read-write control signal and the data of SRAM according to the cpu command of CPU read-write user interrupt handling routine start address.
In interruptable controller, also set in advance and interrupt serial number register and interrupt address register.
Step 202, when the SOC chip reset, the register and the SRAM that are provided with in the initialization step 201.Be invalid for example with all initialization of register.
Step 203, when this SRAM of configuration, be that CPU writes user's interrupt handling routine of each interruption when initial, when interruptable controller is received the cpu command of CPU core configure user interrupt handling routine start address, the write signal of SRAM is effective, the address of SRAM is the 9:2 position of cpu i/f address wire, this is because the address that CPU provides is a byte address, and the data of 4 bytes of an address storage among the SRAM, so to ignore low 2 storage unit of cpu i/f address wire with 256 SRAM of 9:2 bit addressing; The write data of SRAM is the content on the cpu i/f write data line.
CPU core also in the configure interrupt controller each to interrupt the corresponding OIER of application effective, allow corresponding interruption user to send and interrupt application to CPU core.If CPU core does not use certain to interrupt, can not dispose corresponding OIER.
CPU core has disposed after the interruptable controller, can move its normal application program.
Step 204 is to step 206, interruptable controller receives the interruption application of certain interrupt source, interrupt application register controlled logic determines and interrupt applying for this whether corresponding OIER is effective, if, corresponding interruption application register then is set for effective, otherwise execution in step 204 is waited for receiving the next application of interrupting.
In addition, if when in step 204, receiving a plurality of interruption application simultaneously, judge respectively whether each interrupts the corresponding OIER of application effective, if effectively, corresponding interruption application register then is set for effective, otherwise execution in step 204 waits for that receiving next the interruption applies for.
Step 207, be in " non-interruption " state at interruptable controller and interrupt the application register and have one at least when effective, interrupt arbiter is effectively interrupted application to all and is arbitrated, and selects to obtain the interruption application of current limit priority, with as the system break application to the CPU core transmission.
Step 208, interrupt arbiter deposits the sequence number of described highest priority interrupt application in the interruption serial number register, and sends this highest priority interrupt application to CPU core.
The SRAM steering logic is written to the user interrupt handling routine start address of the data that read as the interruption application of current limit priority in the interrupt address register according to the address of the value of interrupting serial number register as SRAM from SRAM.
Step 209, if CPU core allows to interrupt, then change the executive system interrupt handling routine over to, read the address in the interrupt address register, change this address over to and carry out corresponding user's interrupt handling routine code, this user's interrupt handling routine is carried out and is finished in the retrieval system interrupt handling routine of back.
Step 210, CPU core read the interruption serial number register, and the value of interrupting serial number register is write back in the interruption serial number register, so that remove the value of corresponding interruption application register.
Step 211, behind the interruption application register of removing correspondence, interruptable controller enters " non-interruption " state.Whether effective, if effectively, then represent the current interruption that also has other in the waiting for CPU kernel processes, execution in step 207 if judge interrupting the application register; Otherwise execution in step 204 is waited for and is received new interruption application.
The above only is preferred embodiment of the present invention, and is in order to restriction the present invention, within the spirit and principles in the present invention not all, any modification of being done, is equal to replacement, improvement etc., all should be included within protection scope of the present invention.
Claims (11)
1, a kind of interruption processing method is characterized in that, this method is provided with interrupt address register in interruptable controller, and this method is further comprising the steps of:
A. the start address with user's interrupt handling routine of current highest priority interrupt application writes interrupt address register, and this highest priority interrupt application is sent to CPU core;
The B.CPU kernel reads the address in the described interrupt address register, and carries out described user's interrupt handling routine according to this address.
2, method according to claim 1, it is characterized in that, this method further is provided with the OIER corresponding with interrupting application in advance, interrupts application register and user's interrupt address storage unit in interruptable controller, and the start address that will interrupt user's interrupt handling routine of applying in advance writes user's interrupt address storage unit of correspondence;
Further comprise before the steps A: interruptable controller receives the interruption application from interrupt source, and when judging that it is effective drawing corresponding OIER, it is effectively that corresponding interruption application register is set;
The step that described in the steps A start address of user's interrupt handling routine of current highest priority interrupt application is write interrupt address register comprises: select the interruption application of limit priority in current interruption application register effectively interrupts applying for; The start address of user's interrupt handling routine of this highest priority interrupt application is write interrupt address register from user's interrupt address storage unit of correspondence.
3, method according to claim 2 is characterized in that, this method further is provided with the interruption serial number register in advance in interruptable controller;
Described in the steps A start address of user's interrupt handling routine of current highest priority interrupt application is comprised from the step that user's interrupt address storage unit of correspondence writes interrupt address register: the sequence number of highest priority interrupt application is write the interruption serial number register, described address is write interrupt address register from user's interrupt address storage unit of correspondence according to this sequence number.
4, method according to claim 3 is characterized in that, described user's interrupt address storage unit is user's interrupt address register or static RAM SRAM.
5, method according to claim 3 is characterized in that, described user's interrupt address storage unit is SRAM;
Start address with user's interrupt handling routine of current highest priority interrupt application described in the steps A comprises from the step that SRAM writes interrupt address register: the sequence number of current highest priority interrupt application is write the interruption serial number register, calculate corresponding SRAM address according to this sequence number, the start address of user's interrupt handling routine of current highest priority interrupt application is write interrupt address register from SRAM according to this SRAM address.
6, according to claim 3,4 or 5 described methods, it is characterized in that, further comprise the step of removing the interruption application register corresponding after the step B with interrupting sequence number.
7, method according to claim 6 is characterized in that, further comprise after the step B judging whether interrupt the application register effective, and effectively the time execution in step A and B once more.
8, a kind of Interrupt Process device is characterized in that, this interrupt control device comprises:
The interruptable controller that comprises interrupt address register is used for the start address of user's interrupt handling routine of current highest priority interrupt application is write interrupt address register, and this highest priority interrupt application is sent to CPU core;
CPU core is used for reading described address according to described highest priority interrupt application from interrupt address register, and carries out described user's interrupt handling routine according to this address.
9, device according to claim 8 is characterized in that, this device further comprises: the interrupt source that proposes to interrupt application to interruptable controller.
10, device according to claim 9 is characterized in that, described interruptable controller comprises:
Interrupt OIER, interruption application register, user's interrupt address storage unit of application corresponding to each, wherein whether OIER is used to be controlled at after the interruption application that receives interrupt source that the interruption application register of correspondence is set to effectively, whether interrupting the application register, to be used to store corresponding interruption application effective, and user's interrupt address storage unit is used to store the start address of user's interrupt handling routine of corresponding interruption application;
Interrupt arbiter, be used for interrupting the interruption application that the application register tables is shown the current limit priority of effective interruption application selection, the sequence number of this highest priority interrupt application is write the interruption serial number register, and this highest priority interrupt application is sent to CPU core;
Interrupt serial number register, be used to store the sequence number of described highest priority interrupt application.
11, device according to claim 10 is characterized in that, described user's interrupt address storage unit is user's interrupt address register or SRAM.
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| CN105022706A (en) * | 2014-05-02 | 2015-11-04 | 恩智浦有限公司 | Controller circuits, data interface blocks, and methods for transferring data |
| CN105095128A (en) * | 2014-05-22 | 2015-11-25 | 中兴通讯股份有限公司 | Interrupt processing method and interrupt controller |
| CN110007964A (en) * | 2019-03-15 | 2019-07-12 | 芯来科技(武汉)有限公司 | Interruption system for RISC-V framework |
| CN111045730A (en) * | 2019-12-12 | 2020-04-21 | 南京沁恒微电子股份有限公司 | Hardware fast interrupt processing system and method for RISC-V architecture |
| CN117632433A (en) * | 2023-12-05 | 2024-03-01 | 合芯科技有限公司 | Method, device equipment and storage medium for improving interrupt response speed |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| KR100313939B1 (en) * | 1998-12-05 | 2001-12-20 | 김영환 | Interrupt Controller |
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2006
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| CN105095128B (en) * | 2014-05-22 | 2020-04-03 | 中兴通讯股份有限公司 | Interrupt processing method and interrupt controller |
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| CN100419724C (en) | 2008-09-17 |
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