CN1738043A - Failure analysis vehicle for yield enhancement with self test at speed burnin capability for reliability testing - Google Patents

Abstract

A test vehicle for evaluating a manufacturing process for integrated circuits that uses a more space efficient layout of library driving cells arranged to produce circuits that exercise many interconnections that may be designed at the minimum design parameters of a manufacturing process. The cells can be configured to operate as ring oscillators increasing the effective circuit frequency of the test module allowing higher frequency circuit testing, and shortening the time it takes to perform life cycle testing. Visibly marking cells, combined with electrically isolating error prone circuit segments makes, identifying defects much more efficient. The accessibility of many testing methods allows quick location of root cause failures, which allows improvements to be made to the manufacturing process.

Description

The failure analysis carrier that has the self-rate of finished products enhancing of testing that is used for the aging ability of speed of reliability test

Quoting alternately of related application

The application is the part continuation that is applied for the U.S. Patent Application Serial 10/307018 that is entitled as " Failure Analysis Vehicle " on November 27th, 2002 by Richard Schultz and Steve Howard, and the announcement of this application and the full content of principle are combined in herein by reference and specifically.

Technical field

The present invention relates to the integrated circuit manufacturing, relate more specifically to be used to prove the test piece of coming of new technology.

Background technology

In the exploitation of integrated circuit coming of new technology, produced certain design rule of the ability that limits this technology.The designer begins the design of new integrated circuit in the exploitation manufacturing capacity.The ability that the simultaneity of new process development and product design is produced the manufacturing process of integrated circuits for enough these design rules of energy has very large importance.

These design rules comprise such as minimum track width, and the minimum range between trace can be deposited in the maximum access quantity at top and the content of other such parameters mutually.Usually, the producer can guarantee, if parts meet this design rule, a kind of technology just will produce good parts, so just allows the designer just to begin the design of integrated circuit in several months before manufacturing process is ready.

After at first producing new integrated circuit (IC) design, when producing the product of success through adjustment, this design and manufacturing process arranged the cycle of a failure analysis usually.The root of some integrated circuits causes failure analysis may be very time-consuming, will spend several days sometimes even time in several weeks could be isolated single inefficacy on the single chip.

The getable FAILURE ANALYSIS TECHNOLOGY of Developmental Engineer comprises that machinery detects, optional beam induced current (OBIC), the light beam inductive reactance changes (OBIRCH), micromicrosecond imaging amperometry (PICA), photoinduction voltage transformation (LIVA), electric charge induction voltage transformation (CIVA), various ESEMs (SEM) technology, active and passive voltage-contrast, known technology on electron beam (E-Beam) and the other technologies.In addition, the destructive testing such as etching and polishing can be used for isolating and the identification variety of issue.

Under many circumstances, the design of integrated circuit may limit or forbid being used to finding out certain technology of inefficacy.For example, in order to detect certain path with laser technology, this path institute's research path directly above must not have another kind of metal trace.In addition, various technology are isolating problem in the definite part of circuit only, and can not isolate concrete trace or path.

Allow circuit board is carried out usually with the unavailable various significant analyses of other inspection technology with the E-Beam technology of the consistent application of active and passive voltage correlation technique.The using active voltage-contrast, the current electricity condition of integrated circuit die structure can visually be found out.Whether a structure is in VDD, and ground connection or some intermediatenesses are shown by the bright relatively or dark that this structure presents.Usually, the project of ground connection shows dark, and the project that is in VDD shows bright.If desired, dark and bright display effect can be put upside down.Passive voltage-contrast is worked in a similar manner, but is not applied to the power supply of circuit.Substrate is grounded, and charge to unearthed structure from the electronics of SEM or E-Beam, and the structure of ground connection is not accepted electric charge.During the manufacturing of wafer, check each level to utilize passive correlation technique after closer checking sightless level in the time of can producing at the level of wafer and in the polished removal of the level of wafer.The structure of ground connection presents dark usually, and that earth-free structure presents is bright.For the active voltage contrast, if desired, the dark of ground structure and non-ground structure and bright can putting upside down.

In process exploitation and inspection period, importantly will lose efficacy and isolate accurate position.For example, a passage has very high resistance.In order to correct manufacturing process, the position of this passage must accurately be discerned.The FAILURE ANALYSIS TECHNOLOGY of only isolating the part of electric channel is inadequate for the meticulous adjustment of manufacturing process.

Summary of the invention

The present invention is by providing the enforcement integrated circuit fabrication process, the failure analysis that people can be carried out reach as much as possible each other connect and the system and method for element has overcome the shortcoming and the limitation of prior art.The quick identification of defectiveness integrated circuit component in ranks quickened the process of failure analysis, and feasible more high efficiency and more effective manufacturing process are tested.In addition, the present invention can be used for utilizing the dynamic property test static properties of direct current and high speed operation frequency.The integrated circuit that designs in a lot of manufacturing process scopes provides completely and failure analysis fast, so manufacturing defect can find rapidly that technology can be improved.

Therefore embodiments of the invention can comprise a kind of test carrier that is used for integrated circuit, this carrier comprises a plurality of unit delay parts, wherein each unit delay part comprises the unit delay part input, unit delay part output, storehouse driving element and interconnecting modules, wherein the unit delay part input is connected to the storehouse driving element, the storehouse driving element further is connected to interconnecting modules, interconnecting modules further is connected to unit delay part output, a plurality of unit delay parts are connected in series mutually, link the unit delay part input from unit delay part output, form a unit delay part chain; This carrier also comprises the input signal trace of the unit element input of the leading unit delay part that is connected to the unit delay part chain; Output signal trace with the output of the unit element of the last unit delay part that is connected to the unit delay part chain.

Embodiments of the invention can further comprise the method for the manufacturing process of test integrated circuit test carrier, the step that this method comprises is: the designing integrated circuit test carrier, this IC test carrier comprises a plurality of unit delay parts, wherein each unit delay part comprises the unit delay part input, unit delay part output, storehouse driving element and interconnecting modules, wherein the unit delay part input is connected to the storehouse driving element, the storehouse driving element further is connected to interconnecting modules, interconnecting modules further is connected to unit delay part output, a plurality of unit delay parts are connected in series mutually, link the unit delay part input from unit delay part output, form a unit delay part chain; This carrier also comprises the input signal trace of the unit element input of the leading unit delay part that is connected to the unit delay part chain; Output signal trace with the output of the unit element of the last unit delay part that is connected to the unit delay part chain; This method also comprises with manufacturing process makes the IC test carrier; Stimulus is applied to the input signal trace of IC test carrier; Read consequential signal from the output signal trace of IC test carrier; Consequential signal and predetermined contrast signal are compared; And if consequential signal do not meet predetermined contrast signal, make the defective conclusion of this manufacturing process.

Embodiments of the invention can further comprise the test carrier that is used for integrated circuit, this carrier comprises: a plurality of unit delay parts, wherein each unit delay part comprises a plurality of unit element inputs, a plurality of unit element outputs, a plurality of storehouses driving element that is arranged side by side and a plurality of interconnecting modules that on overlapping layer, are provided with, single-unit delay element input in wherein a plurality of unit delay part inputs is connected to the single storehouse driving element in the driving element of a plurality of storehouses, single storehouse driving element is connected to the single interconnecting modules in a plurality of interconnecting modules, and single interconnecting modules is connected to the single-unit delay element output in a plurality of unit delay part outputs; A plurality of unit delay parts are connected in series mutually, link a plurality of unit delay part inputs from a plurality of unit delay part outputs, form a unit delay part chain; This carrier also comprises a plurality of input signal traces of a plurality of unit element inputs of the leading unit delay part that is connected to the unit delay part chain; A plurality of output signal traces with a plurality of unit elements output of the last unit delay part that is connected to the unit delay part chain.

Embodiments of the invention can further comprise the method for the manufacturing process of test integrated circuit test carrier, the step that this method comprises is: the designing integrated circuit test carrier, this IC test carrier comprises a plurality of unit delay parts, wherein each unit delay part comprises a plurality of unit delay part inputs, a plurality of unit delay part outputs, a plurality of storehouses driving element that is arranged side by side and a plurality of interconnecting modules that on overlapping layer, are provided with, single-unit delay element input in wherein a plurality of unit delay part inputs is connected to the single storehouse driving element in the driving element of a plurality of storehouses, single storehouse driving element is connected to the single interconnecting modules in a plurality of interconnecting modules, and single interconnecting modules is connected to the single-unit delay element output in a plurality of unit delay part outputs; A plurality of unit delay parts are connected in series mutually, link a plurality of unit delay part inputs from a plurality of unit delay part outputs, form a unit delay part chain; This carrier also comprises a plurality of input signal traces of a plurality of unit element inputs of the leading unit delay part that is connected to the unit delay part chain; A plurality of output signal traces with a plurality of unit elements output of the last unit delay part that is connected to the unit delay part chain; This method also comprises with manufacturing process makes the IC test carrier; A plurality of stimuluss are applied to a plurality of input signal traces of IC test carrier; Read a plurality of consequential signals from a plurality of output signal traces of IC test carrier; A plurality of consequential signals and a plurality of predetermined contrast signal are compared; And if a plurality of consequential signal do not meet a plurality of predetermined contrast signals, make the defective conclusion of this manufacturing process.

Embodiments of the invention can further comprise the test carrier that is used for integrated circuit, this carrier comprises: a plurality of integrated circuit components, each integrated circuit component in wherein a plurality of integrated circuit components can be counted visual recognition by the ranks on all metal levels that place integrated circuit.

Embodiments of the invention can further comprise the method for checking integrated circuit, the step that this method comprises is: the design experiment carrier, this test carrier comprises a plurality of integrated circuit components, and each integrated circuit component in wherein a plurality of integrated circuit components can be counted visual recognition by the ranks on all metal levels that place integrated circuit; Make test carrier with integrated circuit fabrication process; Visual checkout facility carrier; Count the recognition integrated circuit element with the ranks that pass through to observe on three metal levels.

Embodiments of the invention can further comprise the test carrier that is used for integrated circuit, and this carrier comprises: place the hookup figure on the level of integrated circuit (IC) wafer; The hookup figure is connected to a plurality of passages on the second layer of integrated circuit (IC) wafer; Electrical connection between a plurality of passages on the second layer of integrated circuit (IC) wafer; With a plurality of passages of on the hookup figure layer of integrated circuit (IC) wafer, being isolated by electricity, the therefore only electrical connection between a plurality of passages that reach the hookup figure on the second layer of integrated circuit (IC) wafer.

Embodiments of the invention can further comprise the method for the manufacturing process of test integrated circuit test carrier, the step that this method comprises is: the designing integrated circuit test carrier, and this IC test carrier comprises: place the hookup figure on the level of integrated circuit (IC) wafer; The hookup figure is connected to a plurality of passages on the second layer of integrated circuit (IC) wafer; Electrical connection between a plurality of passages on the second layer of integrated circuit (IC) wafer; With a plurality of passages of on the hookup figure layer of integrated circuit (IC) wafer, being isolated by electricity, the therefore only electrical connection between a plurality of passages that reach the hookup figure on the second layer of integrated circuit (IC) wafer; This method also comprises with manufacturing process makes the IC test carrier; When hookup figure layer produces with passive voltage comparison test hookup figure layer to find defective; By whether passive voltage contrast images and the predetermined passive voltage contrast images of reference comparison confirmed test circuitous pattern are had defective; If do not meet the passive voltage contrast images of predetermined reference with passive voltage contrast images, make the defective conclusion of this manufacturing process.

Embodiments of the invention can further comprise the method for the manufacturing process of check integrated circuit test carrier, the step that this method comprises is: the designing integrated circuit test carrier, and this IC test carrier comprises: place the hookup figure on the level of integrated circuit (IC) wafer; The hookup figure is connected to a plurality of passages on the second layer of integrated circuit (IC) wafer; Electrical connection between a plurality of passages on the second layer of integrated circuit (IC) wafer; With a plurality of passages of on the hookup figure layer of integrated circuit (IC) wafer, being isolated by electricity, the therefore only electrical connection between a plurality of passages that reach the hookup figure on the second layer of integrated circuit (IC) wafer; This method also comprises with manufacturing process makes the IC test carrier; Applying power supply and do not applying under two kinds of situations of power supply with active and passive voltage comparison test test carrier to find defective; By whether active and passive voltage contrast images and the predetermined active and passive voltage contrast images of reference comparison confirmed test circuitous pattern are had defective; If active and passive voltage contrast images does not meet the active and passive voltage contrast images of predetermined reference, remove all levels except hookup figure layer of IC test carrier; With passive voltage comparison test hookup figure layer; Hookup figure passive electrical is pressed contrast images and predetermined comparing with reference to the passive voltage contrast images of hookup; Press contrast images not meet the predetermined defective in the passive voltage contrast images part location test circuitous pattern in hookup figure passive electrical with reference to hookup.

The invention has the advantages that, can produce the integrated circuit of the design limitation that can emphatically point out many manufacturing process.In addition, make engineer or technical staff can accurately locate accurate root (root) rapidly for the comprehensive unconfined test of many signal traces and cause defective, thereby determine any improvement and the variation that to make for manufacturing process rapidly.In addition, manufacturing process can obtain monitoring and check by periodically making and test this test carrier.

Description of drawings

Fig. 1 is the schematic diagram of the embodiment of the step interconnection between two storehouse elements of integrated circuit.

Fig. 2 is the schematic diagram of embodiment of schematic representative of front view of the step interconnection of the non-stacked channels of application heap superimposition.

Fig. 3 is the schematic diagram of the graphic embodiment of cell delay.

Fig. 4 is the schematic diagram of embodiment of the physical layout of unit delay part shown in Figure 3.

Fig. 5 is the schematic diagram of the embodiment of failure test layout.

Fig. 6 is the schematic diagram of the embodiment of shift register, and wherein unit delay part is configured to be easy to carry out high-speed test (HST).

Fig. 7 is the schematic diagram of the embodiment of unit delay part chain.

Fig. 8 is the schematic diagram of the embodiment of unit delay part chain, wherein has the multiple interconnect module that places on the multiple level that has corresponding multiple storehouse driving element, and set multiple interconnect module can be utilized all levels of integrated circuit (IC) wafer more expeditiously.

Fig. 9 is the schematic three dimensional views of physical layout of the unit delay part of embodiment shown in Figure 8, has the multiple interconnect module that places on the multiple level that has corresponding multiple storehouse driving element among the figure.

Figure 10 uses external clock as the schematic diagram of data input with the embodiment of the unit delay part chain that allows to carry out frequency test.

Figure 11 is arranged to as the schematic diagram of ring oscillator work with the embodiment of the unit delay part chain of the higher frequency test of the test carrier that do not need to allow external clock.

Figure 12 A-D is the schematic diagram that places on all metal levels of integrated circuit (IC) wafer with the embodiment of the integrated circuit component ranks number of the easy visual recognition that allows to carry out integrated circuit component.

Figure 13 A-D is the schematic diagram that places the embodiment of the integrated circuit component ranks number on all metal levels of integrated circuit (IC) wafer, this wafer have the passage that places in the ranks number or contact with in addition when metal level does not expose, also allow to carry out the easy identification of integrated circuit component.

Figure 14 A-C is the top view that shows the embodiment of the signal pointer through isolating, and this signal pointer through isolating allows applied voltage contrast and e beam inspection technology with the defective in the located integrated circuit easily.

Figure 15 is the end view of the embodiment shown in Figure 14 A-C of the signal pointer through isolating, and this signal pointer through isolating allows applied voltage contrast and e beam inspection technology with the defective in the located integrated circuit easily.

Embodiment

Fig. 1 has shown the embodiment 100 of the step interconnection between two storehouse elements 102 and 104 of integrated circuit.Article two, power bus 106 and 108 provides power supply to element 102 and 104.The signal traces that leaves element 102 starts from 2 layer 110 on metal and transfers to 3 layer 112 on the metal that has passage 114.Metal trace is transferred to 4 layer 116 on the metal that has passage 118 then.Signal traces is continuously to 5 layer 120 on the metal of the form of spiraling, 6 layer 122 on metal, 8 layer 126 on 7 layer 124 on metal and metal.Metal trace arrives 9 layer 128 on metal continuously.The figure of the form of spiraling repeats to 2 layer 130 on metal for 9 layer 128 and enters the second storehouse element 104 from metal with similar forms.

In each spirals figure, from approaching setting of trace quilt of power bus.For example, on 4 layer 116 on metal, signal traces 132 approaches to be connected to the trace 134 of power bus 108.Under similar forms, power bus trace 136,138,140,142 and 144 is staggered in stepped form.In addition, in certain embodiments, can directly place the below of signal traces from the trace of one of power bus.These traces can be provided with adjacent to each otherly as far as possible by fabrication process parameters.Signal traces can be exposed to the top of integrated circuit, thereby detects with various FAILURE ANALYSIS TECHNOLOGY.In certain embodiments, power trace can directly place below the signal traces.

Under many circumstances, each level of integrated circuit must comprise the metal of certain minimum number so that the stress that brings out in the integrated circuit (IC) chip reduces to minimum.Such condition can be satisfied with the design by those of ordinary skill in the art.In some cases, can in each layer, establish additional trace to meet the requirement of minimum metal by structure.In other embodiment, the metal of minimum number can satisfy with basic step design.

Place the pilot region of the exposure on 9 layers on the metal to be connected to signal traces at each metal level.Like this, zone 146 is connected to 2 layer 110 on metal, and zone 148 is connected to 3 layer 112 on metal, zone 150 is connected to 4 layer 116 on metal, zone 152 is connected to 5 layer 120 on metal, and zone 154 is connected to 6 layer 122 on metal, and zone 156 is connected to 7 layer 124 on metal.These zones also can be arranged on the sloping portion of step.

Step interconnection 100 is the structures that can be used for a kind of integrated circuit of modulation fabrication technique.All signal trace width can be in the minimum interval between minimum dimension and the width.In addition, in the signal path between two storehouse elements 102 and 104 a large amount of passages is arranged.Passage is the project of high failure rate in the typical manufacturing process of integrated circuit, therefore is used to the modulation fabrication technique.

Step interconnection 100 be designed for test capability and defective is isolated.Each signal traces on each level has can be from 9 layers of approaching corresponding pilot region of metal.This makes many experimental techniques be used to discern and isolate the passage of single destruction.In order to determine that accurate root causes inefficacy, it is desirable to accurate passage or trace that locate failure takes place.For example, if a passage just can be checked mask, mould or other treatment facilities of this certain layer in 5 layers of inefficacy of metal.If inefficacy is not isolated to the special modality in certain layer and this layer, manufacturing process just can not be overhauled, and the development step of technology will carry out comparatively slowly.

Present embodiment makes the process exploitation engineer produce hard designing for manufacturing, also gives engineer's mechanism that assessment as much as possible was lost efficacy simultaneously.Have the integrated circuit of a large amount of step interconnection 100 by manufacturing, test piece can produce in the scope of manufacturing process, but also can be assessed rapidly, accurately to locate any inefficacy with needed many FAILURE ANALYSIS TECHNOLOGY.

Those of ordinary skill in the art can design the metal level that has various quantity and the interval between various minimum path width or the signal path, remains on the step interconnection in the spirit and scope of the present invention simultaneously.

Fig. 2 has shown the schematic diagram of the front view of step interconnection 200, has wherein used that pile up and the non-passage that piles up.Signal path 202 enters step from the logic element on 1 layer 204 on the metal.Passage 206 is transferred to 2 layer 207 on metal with signal.Passage 206 has directly three passages that pile up 208,210 and 212 above passage 206.Signal path is transferred to 3 layer 209 on metal once more at passage 214.Also have, three passages that pile up 218,220 and 222 directly are set above passage 214.Passage 224 has two passages 228 and 230 of passage 226 of below and top.Passage 232 has the passage 234 and 236 and the passage 238 of top of below.Passage 242,244 and 246 is below passage 240.Passage 248,250,252,254,256 and 258 passages that do not pile up.

Many possible passage geometric figure in the single step of step interconnection 200 tests.In the downward part of step, promptly passage 248,250, and the non-stacked channels that exists as the autonomous channel between each layer that exists in the integrated circuit is arranged in 252,254,256 and 258.Step in top, in the combination of each stacked channels, comprise the signal transfering channel.In certain embodiments, stacked channels can be present in two parts of step.Such embodiment can be for the assessment manufacturing process of great use, and the passage that piles up in such technology is a serious problem particularly, and the Fabrication parameter of technology is with evaluated.

Many integrated circuit fabrication process have the restriction of stacked channels quantity.This restriction may partly derive from the stress that stacked channels produces in the integrated circuit.In the present embodiment of step interconnection 200, the maximum quantity of stacked channels can be four.Can implement each combination or the setting of stacked channels like this.Those of ordinary skill in the art can design such step interconnection, and wherein the maximum quantity of stacked channels is between the entire quantity of zero metal level in integrated circuit.In certain embodiments, stacked channels can not be implemented in the step.

For various embodiment, the quantity of the level in the integrated circuit can be different.Necessary mfg. moulding die of each layer and mask in the integrated circuit are added in the cost.Like this, for the development of previous manufacturing process, can construct have three to five layers embodiment to finish preliminary development, the embodiment that has the maximum quantity level that this technology may reach then just can be configured and be used for the last technological development stage.The maximum level quantity that varying number can be arranged for each integrated circuit fabrication process.

Fig. 3 has shown the embodiment 300 of schematic unit delay part.Data in 302 arrive data output 304 by circuit.Circuit comprises buffer 306, the step of passage 308, NOR gate 310, second step 312, NAND gate 314, the three steps 316, inverter 318 and the 4th step 319.Power bus comprises VDD 320 and VCC 322, is connected to NOR gate 310 and NAND gate 314, so positive signal is transmitted by this circuit.By the used time of this circuit transmitting signal can be known.

In typical embodiment, circuit 300 can be connected many times end-to-end, has hundreds of time or several thousand times in single integrated circuit.Unit delay circuit 300 can be used for several different useful embodiment.

Fig. 4 has shown the embodiment 400 of the physical layout of the unit delay part that Fig. 3 shows.Circuit comprises buffer 406, first step 408, NOR gate 410, second step 412, NAND gate 414, the three steps 416, inverter 418 and the 4th step 419.Power bus VDD 420 and VCC422 have also been shown among the figure.

This element also is configured to make power bus to aim at.Such arrangement makes the cross section of mechanically obtaining circuit easily to check problem area.In the cross section, because the figure of the repetition of embodiment 400, known good trace can compare with bad trace under a cloud.

Fig. 5 has shown the embodiment 500 of failure test layout.Data on the line 502 are propagated and are exported in DOL Data Output Line 506 by a series of unit delay parts 504.Can be with any amount of unit delay part 504.Some embodiment can comprise several thousand or a hundreds of thousands unit delay part.

When data on the line 502 when being high, signal is propagated until losing efficacy by each unit delay part.For example, if single passage is opened or high impedance, signal will be propagated until arriving the inefficacy passage.Because accessibility pilot region in the step, the test engineer can be simply and is easily determined accurate channel position, comprises this channel bit metal level thereon.

Each unit delay part comprises four steps, and each step comprises many passages.In typical manufacturing process, the failure rate of passage or other integrated circuit components can be in 1: 1000000 or higher scope in process exploitation.Therefore, it will be useful having the circuit that brings to few 100000 or 1000000 passages, and these passages will easily carry out failure analysis.By making the passage of very high quantity or the feature that other are difficult to make, manufacturing process is carried out to be emphasized.This technology can be by being applied to voltage result and the test easily in data in 502 and the reading of data outlet 506 simply.

A lot of different experimental techniques can be used for the position of problem identificatioin.Step has the pilot region of exposure, mechanically detect in these zones, and detect with front and back side AC laser, front and back side DC emission microscope, the DC current surveillance OBIC and the OBIRCH that are used for resistive defects, PICA AC emission is caught, the LIVA DC isolation of losing efficacy, EBEAM AC signal capture, the EBEAM figure relies on the passive voltage-contrast of DC, the passive voltage-contrast of SEM and comprise that the active Pico of AC detects, dc voltage is detected and the active control exploration technology of DC is detected.

The design of the unit delay part that Fig. 4 shows can allow from the top directly to provide the comprehensive covering to various FAILURE ANALYSIS TECHNOLOGY near all traces in the step.For example, because signal traces from the top as seen, various laser pumping FAILURE ANALYSIS TECHNOLOGY can be used for isolating the problem on any part of the signal path on any level.In the inefficacy of not specific other integrated circuits that design for test capability of investigation, the mass part of signal path can grow dark owing to overlapping trace.

Fig. 6 has shown the embodiment 600 of shift register, and wherein unit delay part 602 is configured to carry out easily high-speed test (HST).Data in 604 propagate into the line of unit delay part 602 by bistable state 608, propagate into second bistable state 610 again.Second line of signal by unit delay part 602 leaves second bistable state 610 and propagates into the 3rd bistable state 612.Signal propagates into the 4th bistable state 614 by three-way the 3rd bistable state 612 of leaving of unit delay part 602.The shared public clock line of all bistable states.

By each clock cycle, data must be propagated by each row of unit delay part 602 simultaneously.If problem is present in many unit delay parts one, data can not correctly be propagated and with destroyed.Problem such when the clock rate degree is high at that time will be more obvious.

Present embodiment is devoted to the high-speed test (HST) of integrated circuit, and wherein embodiment 500 is devoted to the static test of circuit.When carrying out high-speed test (HST), present embodiment is with the trickleer resistance variations between the detecting element and can carry out the test more completely of manufacturing process.

In different embodiment, the line of unit delay part 602 can have different length, and bistable quantity also can be different.For example, when using many unit delay parts, propagation times is with height, so clock speed will be lower.When available testing equipment may be not enough near the shorter delay line of test, such example may be more useful.In certain embodiments, the quantity of delay element can be one in hundreds of or more scope.In addition, the quantity of the row of shift register is the amount doesn't matter, depends on the quantity and the available chip space of integrated circuit of the unit delay part that abundant test manufacturing process is necessary.

In certain embodiments, shift register embodiment 600 and layout may reside in the single integrated circuit in failure test embodiment 500.Those of ordinary skill in the art can create other the embodiment in conjunction with other hookup, keeps the spirit and scope of the present invention simultaneously.

Fig. 7 is the schematic diagram of the embodiment 700 of unit delay part 710 chains.Embodiment 700 is similar in appearance to the unit delay part that discloses with respect to the narration in Fig. 3 and 4.The unit delay part 710 that I limits is made of single storehouse driving element 704 and single interconnecting modules 708.Such as in the narration of Fig. 5 announcement, unit delay part 710 can be joined together and produce can be by several thousand or each embodiment of constituting of hundreds of thousands unit delay part 710.I/O (IO) data input signal 702 is sent to the first storehouse driving element 704, is delivered to interconnecting modules 708 then.The a series of combinations that are connected to the storehouse driving element 704 of interconnecting modules 708 are repeated to produce the necessary many number of times of unit delay part chain that are enough to test manufacturing process.In the end of unit delay part chain, IO data output signal 706 can with the comparison as a result of hope to determine whether any defective is arranged in test carrier.The single storehouse driving element 704 that uses together with the single layer of interconnects module 708 of each unit delay part 710 is arranged in the unit delay part chain.This list storehouse driving element 704 can be in a large amount of logical devices, includes but not limited to inverter, NAND gate, NOR gate, buffer etc.Single interconnection layer module 708 can be made of a large amount of hookup figures, includes but not limited to capacitor, and metal combs is spiraled, contact/passage chain etc.Contact/passage chain can utilize more than one level to form interconnecting modules 708.

Fig. 8 is the embodiment 800 of unit delay part 812 chains, and the multiple interconnect module 810 that is placed on the multiple level is wherein arranged, and corresponding multiple storehouse driving element 804 is set to utilize all levels of integrated circuit (IC) wafer more efficiently.Narration with respect to Fig. 9 has more at large disclosed the multiple level of storehouse driving element 804 and the overlapping level of interconnecting modules 810.The multiple level of storehouse driving element 804 and the overlapping layer second phase of interconnecting modules 810 are discussed about Fig. 8 and are understood present embodiment is had more completely.Each storehouse driving element 804 can utilize six to seven levels of integrated circuit (IC) wafer.Interconnecting modules 804 utilizes one deck usually, if which floor contact or passage chain also only need.Because interconnecting modules 810 shows on a fraction of six or seven layers that forms storehouse driving element 804 required wafers, embodiment 800 can be placed side by side with two or more storehouses driving element 804, therefore corresponding interconnecting modules 810 can layering on top separately.Therefore storehouse driving element 804 is connected on the different levels that can be placed in integrated circuit (IC) wafer, utilizes on the corresponding different interconnecting modules 810 of whole width of multiple storehouse driving element 810.Utilize the multiple level of interconnecting modules to make skilled person in the industry that more test images is placed on the same area of integrated circuit (IC) wafer, this wafer is used to single test images when only one deck being used for interconnecting modules 810.Each storehouse driving element 804 has the input 802,808 of isolation.Embodiment 800 can be with storehouse driving element 804 and interconnecting modules 810 the form chaining in the narration of Fig. 7, to disclose.For the embodiment 800 that utilizes multiple interconnect module 810 and multiple storehouse driving element 804 of the present invention, I limits unit delay part 812 and is restricted to the single storehouse driving element 804 that is connected on single interconnecting modules 810.The unit delay part 812 of shown embodiment 800 is made of the unit delay part 812 of two separation, and these two elements are owing to interconnecting modules 810 is multi-level and overlapping.Interconnecting modules 810 by layering at top separately, so unit delay part 812 by single storehouse driving element 804 and the level that comprises the interconnecting modules 810 of the interconnecting modules 810 that is connected to storehouse driving element 804 through selecting constitute.IO data inputs is isolated usually, if but those of ordinary skill in the art need also can connect together.There is multiple IO data output signal 806,814 to be used for the result of unit of display delay element 812 chains in the end of unit delay part 812 chains.IO data output signal 806,814 can with the value comparison of unit delay part 812 chains of hope to determine whether to exist any defective workmanship.Similar with the embodiment that the narration that is relevant to Fig. 7 discloses, the embodiment 800 with multiple driving element 804 and multiple interconnect module layer 810 can be arranged to various settings with the unit delay part more or less 812 of chaining and dissimilar interconnecting modules 810.Storehouse driving element 804 can be in a large amount of logical devices, includes but not limited to inverter, NAND gate, NOR gate, buffer etc.Interconnection layer module 708 can be made of a large amount of hookup figures, includes but not limited to capacitor, and metal combs is spiraled, contact/passage chain etc.

Fig. 9 is the schematic three dimensional views of physical layout of the unit delay part 900 of embodiment shown in Figure 8, places the multiple interconnect module 910,912 on the multiple level that has corresponding multiple storehouse driving element 906,908 among the figure.Storehouse driving element 906,908 requires the multiple integrated circuit level.In embodiment 900, the storehouse driving element is an inverter, but storehouse driving element 906,908 can be a kind of in a large amount of logical devices, includes but not limited to inverter, NAND gate, NOR gate, buffer etc.Each interconnecting modules 910,912 uses the individual layer of integrated circuit (IC) wafer usually, can be made of a large amount of hookup figures, includes but not limited to capacitor, and metal combs is spiraled, contact/passage chain etc.Each spiral interconnecting modules 910 and metal combs interconnecting modules 912 that all is on the individual layer of integrated circuit (IC) wafer is shown as embodiment 900.Have multiple driving element 906,908, interconnecting modules 910.912 can be stacked on top separately, farthest to utilize the space, and the integrated circuit fabrication process of test sheet test carrier farthest.The first storehouse driving element 906 receives IO data input signal 902, and this signal is handled by the first storehouse driving element 906.This signal is sent to IO data input signal 902 and is in the interconnecting modules 910 that spirals with one deck then.In case signal is by the interconnecting modules 910 that spirals, signal is delivered to IO data output 914 uploading with one deck with IO data input signal 902.The second storehouse driving element 908 is received in IO data input signal 902 and is handled by the second storehouse driving element 908 with the 2nd IO data input signal 904, the two IO data input signals 904 on one deck.This signal is sent to the metal combs interconnecting modules 912 that is in different layers with storehouse driving element 908 output and IO data input signal 904 then.In case signal is by metal combs interconnecting modules 912, signal turns back to the level of IO data input 902,904 and is used as IO data output signal 918 and transmits.IO data output signal 914,918 can be attached to exterior I O and connect or be connected on another unit delay part in the unit delay part chain.The quantity of driving element 906,908 can enlarge to meet the available level that is used for the selected type of interconnecting modules 910,912.Those of ordinary skill in the art also can set out interconnection layer 910,912 to utilize whole level or and the sub-fraction of the shared level of another interconnecting modules.For example, a fraction of passage chain that only takies the multiple level of integrated circuit can use together with other hookup figure, and wherein other hookup figure has taken the remaining width of integrated circuit layer.

Figure 10 uses external clock 1006 as the schematic diagram of data input with the embodiment 1000 of unit delay part 1010 chains of tolerance frequency test.Embodiment 1000 is a kind of among the embodiment that forms of the logic arrangement of the available Fig. 5 of being similar to.External clock 1006 is used to drive unit delay part 1010 chains.Minimum limited unit delay part 1010 is made of single storehouse driving element 1002 and single interconnecting modules 1004.Signal is by unit delay part 1010 chains, until the terminal that arrives the unit delay part chain and be used as clock output signal 1008 outputs.Clock output signal 1008 can with the output signal comparison of hope to determine whether any defective workmanship is arranged in test carrier.Storehouse driving element 1002 can be a kind of in a large amount of logical devices, includes but not limited to inverter, NAND gate, NOR gate, buffer etc.Interconnecting modules 1004 can be made of a large amount of hookup figures, includes but not limited to capacitor, and metal combs is spiraled, contact/passage chain etc.

Figure 11 is set up the schematic diagram of embodiment 1100 that does not need unit delay part 1114 chains of external clock 1108 as ring oscillator work with the higher frequency test that allows test carrier.The anti-phase selection element 1102 of ring oscillator embodiment 1100 usefulness is selected between the initial anti-phase selection element 1102 with formation ring oscillator circuit using external clock 1108 or the output of unit delay part 1114 chains connected back.The single storehouse driving element 1104 that is connected to single interconnecting modules 1106 is minimum limited unit delay parts 1114.When the unit delay part chain was used as ring oscillator 1100, external clock input 1108 there is no need, because anti-phase selection element sends unit delay part output as input of unit delay part chain rather than external clock input 1108.It is the switches that the ring oscillator circuit is connected and closed that ring oscillator may import 1110.When ring oscillator may be imported 1110 conductings, signal was propagated by circuit, was returned 1102 inputs of initial anti-phase selection element until it.The state variation by transmitting signal of unit delay part makes anti-phase selection element 1102 output change states, and passes through the variation of unit delay part chain spread state.The frequency of ring oscillator is the inverse of the delay of the delay of accumulation of each storehouse driving element 1104 in the test chain accumulation that adds each interconnection layer module 1106.Anti-phase selection element 1102 external clocks that are connected to another unit delay part 1110 chains by the output with unit delay part 1114 chains import 1106, and different unit delay part 1110 chains can be made under different frequencies works.Ring oscillator be provided with 1100 allow test carriers in inside with very high frequency work, i.e. 200MHz or higher, still producing simultaneously can be by the clock of frequency division tremendously low frequency output 1112.Like this, clock output signal can be measured by the frequency meter of non-costliness.High internal frequency allows more to approach the hundreds of MHz of integrated circuit (IC) products to the test of the frequency of GHz and longer life test, because circuit can circulate under the speed that is exceedingly fast, the time cycle that is shortened is reached and depend on the same state variation number of embodiment of external clock.Progressively the clock of the Xia Jianging favourable part of exporting 1112 frequencies is that the cost of frequency meter is high along with the increase of the top frequency scope of frequency meter.

Figure 12 A-D is the schematic diagram that places on all metal levels of integrated circuit (IC) wafer with the embodiment of the integrated circuit component ranks several 1206 of the easy visual recognition that allows integrated circuit component.Figure 12 A is the schematic top view 1201 that has the embodiment of metal level.Figure 12 B is the schematic top view 1202 of the embodiment of metal level crested.Figure 12 C is the schematic side view 1203 that has the embodiment of metal level 1210.Figure 12 D is the schematic side view 1204 of the embodiment of metal level 1220 cresteds.Ranks several 1206 are placed in metal level 1210,1214, on 1220 with the row and column of recognition integrated circuit element.The ranks number obtains best demonstration in the top view 1201,1202 of embodiment.When metal level was removed, the ranks number was invisible 1208,1222, exposed until another metal level.When metal level be removed and metal level between oxide layer when being visible all levels, the removal process of level is a problem.End view 1203,1204 has shown best how oxide layer 1212,1218 covers integrated circuit component ranks several 1206.

Figure 13 A-D is all metal levels 1316 that place integrated circuit (IC) wafer, 1320, on 1328, passage or contact 1306,1310,1314,1324 place in the ranks number, even when metal level 1316,1320,1328 also allow the integrated circuit component schematic diagram of the embodiment 1300 of the integrated circuit component ranks several 1308,1312 of identification easily when not exposing.Figure 13 A is the schematic top view 1301 that has the embodiment of metal level.Figure 13 B is the schematic top view 1302 of the embodiment of metal level crested.Figure 13 C is the schematic side view 1303 that has the embodiment of metal level 1316.Figure 13 D is the schematic side view 1304 of the embodiment of metal level 1328 cresteds.Similar with the embodiment that discloses in the narration of Figure 12, represent the ranks several 1308 of integrated circuit component to be placed in all metal levels 1316 of integrated circuit (IC) wafer, 1320,1328 upper channels and/or contact 1306,1310,1314,1324 are arranged in such a way, it is several 1308,1312 to connect the integrated circuit ranks, and extends to other levels in the integrated circuit (IC) wafer.When being in metal level 1316,1320, in the time of on 1328, integrated circuit ranks several 1308,1312 and passage/contact 1306,1310,1314,1324 are visual 1312,1330.Passage and/or contact 1306,1310,1314,1324 are approaching by multiple level, therefore work as metal level 1316 and are removed 1312,1330, and passage/contact 1310,1324 still as seen.Top view 1301,1302 has shown best how integrated circuit ranks several 1308,1312 show when being examined, and end view 1303,1304 has shown best even contact/passage 1306 ought only have oxide layer 1318,1326 to show the time, as seen how 1310,1314,1324 still keep.The value of this embodiment is, checks the necessity for correct failure analysis when oxide layer 1318,1326 exposes.Passage/contact 1306,1310,1314,1324 begin and end in those of ordinary skill in the art to think on any one suitable integrated circuit level of correct failure analysis purpose.

Figure 14 A-C show to allow voltage-contrast and the electron beam technology top view of the embodiment of the signal pointer 1410,1420 through isolating of the defective 1416 in the located integrated circuit easily.Figure 14 A is the schematic diagram 1451 that shows the embodiment of all metal levels and passage.Figure 14 B is the schematic diagram 1452 that only shows the embodiment of the integrated circuit layer that comprises the hookup figure.Figure 14 C is the schematic diagram 1453 of the only embodiment of display channel.This embodiment uses metal combs as the favourable part of IC test circuitous pattern with explanation various piece of isolation experiment integrated circuit pattern on a level of integrated circuit (IC) wafer.Half of metal combs 1412 is attached to signal traces metal level 1402 with passage 1406.Second half of metal combs is attached to ground connection trace metal level 1404 with passage 1408.If defective 1416 takes place in integrated circuit fabrication process, integrated circuit layer can be removed 1422 and be used to check the metal level of the hookup of purpose with demonstration.Because the metal combs circuit can be made of several thousand comb pointers, check that with typical the single defective of technological orientation may be very tediously long.The integrated circuit of the various piece allowable defect of isolation experiment integrated circuit pattern is removed and is electrically connected metal level on individual layer, and the hookup figure of exposure through isolating is to help the location of defective.Half each other comb pointer 1410,1414,1420 of the signal of metal combs circuit is isolated by electricity on hookup figure metal level.The signal pointer of metal combs 1410 is electrically connected to signal traces metal level 1402 with passage 1406.Passage between the metal level connects provides continuous by being electrically connected of the metal combs 1412 transmission signals of telecommunication.When defective 1416 was detected, integrated circuit layer can be removed with the signal pointer 1414,1420 through isolating on exposure test circuitous pattern metal level 1422 and the hookup figure metal level 1422.By signal pointer 1414,1420, when applied voltage contrast and electron beam defect analysis technology, have only the earth connection of metal combs 1418 and each other signal pointer 1414 demonstration that comprises defective to be grounded (dark) through isolating.The signal pointer is isolated the defective 1416 that makes in the metal combs hookup figure 1442 and is located fast and easily.When integrated circuit layer is removed but oxide layer when covering metal combs layer 1430, passage can be grounded (i.e. dark) to determine which signal pointer 1426 with voltage-contrast and electron beam defect analysis check-up.The passage 1428 of ground connection also shows dark, conforms to the signal pointer 1426 of ground connection.When with voltage-contrast and electron beam defect analysis technology, the signal pointer 1424 of non-ground connection shows bright.The passage 1424,1426,1428 that utilization shows by oxide layer is even the isolation of signal pointer also makes the defect analysis personnel locate defective 1416 rapidly and easily when the metal combs layer does not directly expose 1430.

Figure 15 is the permission voltage-contrast that shows of Figure 14 A-C and the e beam inspection technology end view of the embodiment 1500 of the signal pointer 1504,1512 through isolating of the defective 1514 in the located integrated circuit easily.The end view of embodiment 1500 has shown the metal combs test integrated circuit pattern that is electrically connected to signal traces metal level 1506 on the metal level with passage 1502.Ground connection trace metal level and metal combs earth connection are not shown, because ground connection trace metal level and metal combs earth connection are also unnecessary for the explanation of the end view of understanding embodiment 1500.The signal pointer 1504,1512 of metal combs is shown as from outside outstanding of paper, and the ground connection pointer 1510 of metal combs is shown as and penetrates the outstanding of paper.Signal traces metal level 1506 is shown the last electrical connection of the signal pointer 1504,1512 that metal combs is described.Signal pointer 1504,1512 is isolated by electricity on the metal combs layer.Passage 1502 is connected to signal traces metal level 1506 with the signal pointer 1504,1512 of metal combs through isolating.Each signal pointer 1504,1512 of metal combs integrated circuit is by being provided with the zone that is used for passage 1502 through enlarging and it being attached on the metal combs layer signal pointer 1504,1512 through isolating and being isolated.Set line 1508 is used to illustrate that signal traces metal 1506 where can be removed to allow the inspection to passage 1502.The electrical connection that is used for metal combs signal pointer is set up with signal traces metal level 1506, and this layer is connected to each signal pointer 1504,1512 with passage 1502 on the metal combs layer.If defectiveness 1514 on the mono signal pointer 1512 of metal combs circuit, and signal traces metal level 1506 is in the appropriate location, then whole signal metal comb structure shows ground connection (dark) when the working voltage correlation technique.In case signal traces metal level 1506 is removed 1508, be connected to each signal pointer 1504,1512 passage 1502 shows passive voltage-contrast or electron beam defect analysis technology, and the passage that is used for signal pointer 1512 that only is subjected to defective 1514 influences just is grounded (promptly dark).Every other through isolating the signal pointer and the passage 1504 that adheres to show normal (promptly bright), therefore in a big interconnecting modules hookup, allow to carry out quick identification for defective 1514.The various piece of isolated interconnection modular circuit figure is not limited to the metal combs structure.Spiral and other test images also can be isolated into less part, finish with the passage of interlayer for being connected electrically on another removable level of signal.The figure of isolating other will have with seen for metal combs hookup figure identical through improved defect location effect.

Various embodiment are very useful for the exploitation and the check of integrated circuit fabrication process.In typical application, one of them embodiment will design with the target design parameter for coming of new technology.Such design parameter can comprise the quantity of minimum track width and maximum stacked channels.An embodiment can manufacture integrated circuit with coming of new technology.Any problem for this integrated circuit will be isolated in-problem accurate passage or trace rapidly.This problem will be tracked to specific process then, master reticle, or track other manufacture view in case of necessity.When technology can produce one or more embodiment of the present invention and when not producing any inefficacy, this technology just can be proved, produce in batches just can begin.

For the already present manufacturing process of check, present embodiment can further play a role.For the manufacturing process of having set up, it is desirable to periodically produce among each embodiment, to assess any problem and the correct operation of check with this manufacturing process.

For the purpose that illustrates and narrate to the present invention proposes narration above.But and mean limit the present invention or limit the invention to the precise forms that is disclosed that according to above-mentioned principle, other modifications and variations all are possible.The selection of embodiment and the purpose of narration are in order to explain principle of the present invention and practical application thereof best, thereby make those of ordinary skill in the art can in each embodiment, utilize the present invention and various modification thereof best, make it be suitable for special-purpose as expected.Attached claim is believed to comprise except prior art and limits extraneous every other alternate embodiment of the present invention.

Claims (30)

1. test carrier that is used for integrated circuit comprises:

A plurality of unit delay parts, wherein each described unit delay part comprises the unit element input, unit element output, storehouse driving element and interconnecting modules, wherein said unit element input is connected to described storehouse driving element, described storehouse driving element further is connected to described interconnecting modules, described interconnecting modules further is connected to described unit element output, described a plurality of unit delay part is connected in series mutually, link described unit delay part input from described unit delay part output, form a described unit delay part chain;

Be connected to the input signal trace of unit element input of the leading unit delay part of described unit delay part chain; With

Be connected to the output signal trace of unit element output of the last unit delay part of described unit delay part chain.

2. test carrier as claimed in claim 1 is characterized in that wherein the storehouse driving element comprises by NAND gate, NOR gate, at least one element in the set that buffer and inverter are formed.

3. test carrier as claimed in claim 1 is characterized in that wherein said interconnecting modules comprises by capacitor, and metal combs is spiraled, at least one element in the set that contact chain and passage chain are formed.

4. test carrier as claimed in claim 1 is characterized in that, wherein said input signal trace is connected to external timing signal, and described output signal trace is write and the relevant clock output signal of described external clock logic.

5. test carrier as claimed in claim 4 further comprises:

Anti-phase selection element, wherein said anti-phase selection element have a ring oscillator may be imported, and selects component data input and the output of a selection component data for two;

Described selection component data output is connected to described input signal trace;

One of select in the data input to be connected to described external timing signal for described two;

In the input of described two selection data another is connected to described unit delay part chain output signal trace;

The state that described ring oscillator may be imported determines that in the component datas input which is described two selected by anti-phase and send to described selection component data output; With

The described output signal trace of the described chain of described unit delay part is used as the outside transmission of described clock output signal.

6. test carrier as claimed in claim 5 is characterized in that, wherein said clock output signal further is connected to described two and one of selects in the elements input as described external timing signal.

7. method of testing the manufacturing process of integrated circuit test carrier, the step that this method comprises is:

Design described IC test carrier, described IC test carrier comprises:

A plurality of unit delay parts, wherein each described unit delay part comprises the unit element input, unit element output, storehouse driving element and interconnecting modules, wherein said unit element input is connected to described storehouse driving element, described storehouse driving element further is connected to described interconnecting modules, described interconnecting modules further is connected to described unit element output, described a plurality of unit delay part is connected in series mutually, link described unit delay part input from described unit delay part output, form a described unit delay part chain;

Be connected to the input signal trace of unit element input of the leading unit delay part of described unit delay part chain; With

Be connected to the output signal trace of unit element output of the last unit delay part of described unit delay part chain;

Make described IC test carrier with described manufacturing process;

Stimulus is applied to the described input signal trace of described IC test carrier;

Read consequential signal from the described output signal trace of described IC test carrier;

Described consequential signal and predetermined contrast signal are compared; And

If described consequential signal does not meet described predetermined contrast signal, make the defective conclusion of described manufacturing process.

8. method as claimed in claim 7 is characterized in that, wherein said IC test carrier further comprises:

Described storehouse driving element, this storehouse driving element comprises by NAND gate, NOR gate, at least one element in the set that buffer and inverter are formed.

9. method as claimed in claim 7 is characterized in that, wherein said IC test carrier further comprises:

Described interconnecting modules, this interconnecting modules comprises by capacitor, metal combs is spiraled, at least one element in the set that contact chain and passage chain are formed.

10. method as claimed in claim 7, it is characterized in that wherein said IC test carrier further comprises: be connected to the described input signal trace of external timing signal and be relevant to the described output signal trace of the clock output signal of described external clock as logic.

11. method as claimed in claim 10 is characterized in that, wherein said IC test carrier further comprises:

Anti-phase selection element, wherein said anti-phase selection element have a ring oscillator may be imported, and selects component data input and the output of a selection component data for two;

Described selection component data output is connected to described input signal trace;

One of select in the data input to be connected to described external timing signal for described two;

In the input of described two selection data another is connected to described unit delay part chain output signal trace;

The state that described ring oscillator may be imported determines that in the component datas input which is described two selected by anti-phase and send to described selection component data output; With

The described output signal trace of the described chain of described unit delay part is used as the outside transmission of described clock output signal.

12. method as claimed in claim 11 is characterized in that, wherein said IC test carrier further comprises:

Further be connected to described two described clock output signals of one of selecting in the elements input as described external timing signal.

13. a test carrier that is used for integrated circuit comprises:

A plurality of unit delay parts, wherein each unit delay part comprises a plurality of unit element inputs, a plurality of unit element outputs, a plurality of storehouses driving element that is arranged side by side and a plurality of interconnecting modules that on overlapping layer, are provided with, single-unit delay element input in wherein said a plurality of unit delay part input is connected to the single storehouse driving element in the driving element of described a plurality of storehouses, described single storehouse driving element is connected to the single interconnecting modules in described a plurality of interconnecting modules, and described single interconnecting modules is connected to the single-unit delay element output in described a plurality of unit delay part output;

Be connected in series mutually, link described a plurality of unit delay part input, form described a plurality of unit delay parts of a described unit delay part chain from described a plurality of unit delay part outputs;

Be connected to a plurality of input signal traces of a plurality of unit elements input of the leading unit delay part of described unit delay part chain; With

Be connected to a plurality of output signal traces of a plurality of unit elements output of the last unit delay part of described unit delay part chain.

14. test carrier as claimed in claim 13 is characterized in that, wherein said storehouse driving element comprises by NAND gate, NOR gate, at least one element in the set that buffer and inverter are formed.

15. test carrier as claimed in claim 13 is characterized in that, wherein said interconnecting modules comprises by capacitor, and metal combs is spiraled, at least one element in the set that contact chain and passage chain are formed.

16. a method of testing the manufacturing process of integrated circuit test carrier, the step that this method comprises is:

Design described IC test carrier, described IC test carrier comprises:

A plurality of unit delay parts, wherein each unit delay part comprises a plurality of unit delay part inputs, a plurality of unit delay part outputs, a plurality of storehouses driving element that is arranged side by side and a plurality of interconnecting modules that on overlapping layer, are provided with, single-unit delay element input in wherein said a plurality of unit delay part input is connected to the single storehouse driving element in the driving element of described a plurality of storehouses, described single storehouse driving element is connected to the single interconnecting modules in described a plurality of interconnecting modules, and described single interconnecting modules is connected to the single-unit delay element output in described a plurality of unit delay part output;

Be connected in series mutually, link described a plurality of unit delay part input, form a plurality of unit delay parts of the chain of a described unit delay part from described a plurality of unit delay part outputs;

Be connected to a plurality of input signal traces of a plurality of unit elements input of the leading unit delay part of described unit delay part chain; With

Be connected to a plurality of output signal traces of a plurality of unit elements output of the last unit delay part of described unit delay part chain;

Make described IC test carrier with described manufacturing process;

A plurality of stimuluss are applied to described a plurality of input signal traces of described IC test carrier;

Read a plurality of consequential signals from described a plurality of output signal traces of described IC test carrier;

Described a plurality of consequential signals and a plurality of predetermined contrast signal are compared; And

If described a plurality of consequential signal does not meet described a plurality of predetermined contrast signal, make the defective conclusion of described manufacturing process.

17. method as claimed in claim 16 is characterized in that, wherein said IC test carrier further comprises:

Described storehouse driving element, this storehouse driving element comprises by NAND gate, NOR gate, at least one element in the set that buffer and inverter are formed.

18. method as claimed in claim 16 is characterized in that, wherein said IC test carrier further comprises:

Described interconnecting modules, this interconnecting modules comprises by capacitor, metal combs is spiraled, at least one element in the set that contact chain and passage chain are formed.

19. a test carrier that is used for integrated circuit comprises:

A plurality of integrated circuit components, each integrated circuit component in wherein said a plurality of integrated circuit components can visually be discerned by the ranks number on all metal levels that place described integrated circuit.

20. test carrier as claimed in claim 19 further comprises:

Therefore place a plurality of passages on the described ranks number, when described passage generation ranks number when the top of described integrated circuit is seen.

21. test carrier as claimed in claim 19 further comprises:

Place a plurality of contacts in the described ranks number, therefore when described contact generation ranks number when the top of described integrated circuit is seen.

22. a method of checking integrated circuit, the step that this method comprises is:

The design experiment carrier, described test carrier comprises a plurality of integrated circuit components, each integrated circuit component in wherein said a plurality of integrated circuit components can be counted visual recognition by the ranks on all metal levels that place described integrated circuit;

Make described test carrier with integrated circuit fabrication process;

The described test carrier of visual inspection; With

Count the recognition integrated circuit element by the described ranks of observing on the described metal level.

23. the step that method as claimed in claim 22 further comprises is:

The further described IC test carrier of design, described IC test carrier further comprises a plurality of a plurality of passages that place described ranks number, therefore when described passage generation ranks number when the top of described integrated circuit is seen;

Remove metal level, only stay the oxide layer of setting; With

By observe described passage with the ranks number of discerning described integrated circuit component the recognition integrated circuit element.

24. the step that method as claimed in claim 22 further comprises is:

The further described IC test carrier of design, described IC test carrier further comprises a plurality of a plurality of contacts that place described ranks number, therefore when described contact generation ranks number when the top of described integrated circuit is seen;

Remove metal level, only stay the oxide layer of setting; With

By observe described contact with the ranks number of discerning described integrated circuit component the recognition integrated circuit element.

25. a test carrier that is used for integrated circuit, this carrier comprises:

Place the hookup figure on the level of integrated circuit (IC) wafer;

Described hookup figure is connected to a plurality of passages on the second layer of described integrated circuit (IC) wafer;

Electrical connection between described a plurality of passages on the described second layer of described integrated circuit (IC) wafer; With

Described a plurality of passages of on the described hookup figure layer of described integrated circuit (IC) wafer, being isolated by electricity, the therefore only electrical connection between the described a plurality of passages that reach described hookup figure on the described second layer of described integrated circuit (IC) wafer.

26. test carrier as claimed in claim 25 is characterized in that, wherein said hookup figure comprises by spiraling metal combs, at least one element in the set that contact chain and passage chain constitute.

27. a method of testing the manufacturing process of integrated circuit test carrier, the step that this method comprises is:

Design described IC test carrier, described IC test carrier comprises:

Place the hookup figure on the level of integrated circuit (IC) wafer;

Described hookup figure is connected to a plurality of passages on the second layer of described integrated circuit (IC) wafer;

Electrical connection between described a plurality of passages on the described second layer of described integrated circuit (IC) wafer; With

Described a plurality of passages of on the described hookup figure layer of described integrated circuit (IC) wafer, being isolated by electricity, the therefore only electrical connection between the described a plurality of passages that reach described hookup figure on the described second layer of described integrated circuit (IC) wafer;

Make described IC test carrier with described manufacturing process;

When described hookup figure layer produces with the described hookup figure of passive voltage comparison test layer with the discovery defective;

By whether passive voltage contrast images and the predetermined passive voltage contrast images of reference comparison confirmed test circuitous pattern are had defective; With

If described passive voltage contrast images does not meet the passive voltage contrast images of described predetermined reference, make the defective conclusion of described manufacturing process.

28. method as claimed in claim 27 is characterized in that, wherein said IC test carrier further comprises:

By capacitor, metal combs is spiraled, the described hookup figure that at least one element in the set that contact chain and passage chain are formed constitutes.

29. a check is used for the method for the IC test carrier of manufacturing process, the step that this method comprises is:

Design described IC test carrier, described IC test carrier comprises:

Place the hookup figure on the level of integrated circuit (IC) wafer;

Described hookup figure is connected to a plurality of passages on the second layer of described integrated circuit (IC) wafer;

Electrical connection between described a plurality of passages on the described second layer of described integrated circuit (IC) wafer; With

Described a plurality of passages of on the described hookup figure layer of described integrated circuit (IC) wafer, being isolated by electricity, the therefore only electrical connection between the described a plurality of passages that reach described hookup figure on the described second layer of described integrated circuit (IC) wafer;

Make described IC test carrier with described manufacturing process;

, apply power supply during check and do not apply power supply to find defective with the described test carrier of active and passive voltage comparison test;

By more active and passive voltage contrast images, determine whether described hookup figure defectiveness, with the active and passive electrical pressure ratio of predetermined reference than image;

If described active and passive voltage contrast images does not meet the active and passive voltage contrast images of described predetermined reference, remove all levels of described IC test carrier except described hookup figure layer;

With the described hookup figure of passive voltage comparison test layer;

Hookup figure passive electrical is pressed contrast images and predetermined comparing with reference to the passive voltage contrast images of hookup; With

Locating hookup figure passive electrical described in the described hookup figure presses contrast images not meet described predetermined defective with reference to the passive voltage contrast images of hookup part.

30. method as claimed in claim 29 is characterized in that, wherein said IC test carrier further comprises:

By capacitor, metal combs is spiraled, the described hookup figure that at least one element in the set that contact chain and passage chain are formed constitutes.

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