CN1705012A - Drive circuit and image display device employing same and portable device thereof - Google Patents
Drive circuit and image display device employing same and portable device thereof Download PDFInfo
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- CN1705012A CN1705012A CNA2005100763028A CN200510076302A CN1705012A CN 1705012 A CN1705012 A CN 1705012A CN A2005100763028 A CNA2005100763028 A CN A2005100763028A CN 200510076302 A CN200510076302 A CN 200510076302A CN 1705012 A CN1705012 A CN 1705012A
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
- G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
- G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
- G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
- G09G3/3611—Control of matrices with row and column drivers
- G09G3/3648—Control of matrices with row and column drivers using an active matrix
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G2300/00—Aspects of the constitution of display devices
- G09G2300/04—Structural and physical details of display devices
- G09G2300/0421—Structural details of the set of electrodes
- G09G2300/0426—Layout of electrodes and connections
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G2300/00—Aspects of the constitution of display devices
- G09G2300/08—Active matrix structure, i.e. with use of active elements, inclusive of non-linear two terminal elements, in the pixels together with light emitting or modulating elements
- G09G2300/0809—Several active elements per pixel in active matrix panels
- G09G2300/0814—Several active elements per pixel in active matrix panels used for selection purposes, e.g. logical AND for partial update
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G2300/00—Aspects of the constitution of display devices
- G09G2300/08—Active matrix structure, i.e. with use of active elements, inclusive of non-linear two terminal elements, in the pixels together with light emitting or modulating elements
- G09G2300/0809—Several active elements per pixel in active matrix panels
- G09G2300/0833—Several active elements per pixel in active matrix panels forming a linear amplifier or follower
- G09G2300/0838—Several active elements per pixel in active matrix panels forming a linear amplifier or follower with level shifting
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- Crystallography & Structural Chemistry (AREA)
- Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- General Physics & Mathematics (AREA)
- Theoretical Computer Science (AREA)
- Liquid Crystal Display Device Control (AREA)
- Control Of Indicators Other Than Cathode Ray Tubes (AREA)
- Liquid Crystal (AREA)
Abstract
A liquid crystal display part is divided into a plurality of blocks along a horizontal direction. Specifically, it is divided into the block having 24 source lines for each, and a plurality of data buses DB are provided corresponding to the plurality of blocks respectively. Each data bus DB receives image data from a data terminal DQ. The data buses DB are arranged so as not to cross over each other and each block receives the image data from one data bus DB.
Description
Technical field
The present invention relates to driving circuit, particularly relate to driving and come the driving circuit of the image displaying part of display image, and be provided with the image display device of this driving circuit and be provided with the portable set of this image display device by a plurality of pixels that drive rectangular configuration.
Background technology
In recent years, its signal Processing form is converted to digital signal processing from analog signal processing in the communication facilities beyond the information equipment or audio frequency, the visual device etc.And these equipment have the tendency of miniaturization and and low consumption electrification.Particularly be in the portable set of representative, be extensive use of liquid crystal indicator as the low power consumption display device with the pocket telephone.
Liquid crystal indicator generally is provided with: the image displaying part of a plurality of picture element matrix shapes configuration, to pixel accordingly many roots polar curve of being provided with of column direction supply with vertical scanning circuit with the horizontal scanning circuit of the corresponding display voltage of video data and the many gate lines activation that will be provided with corresponding to pixel row direction.
Activate gate line successively with the vertical scanning circuit, by with horizontal scanning circuit via sweep trace to the display voltage of the pixel of capable connections of sweep object supply corresponding to video data, the liquid crystal cell that each pixel comprises is luminous with the display brightness of display voltage correspondence, and the entire image display part shows desired image.
In recent years, follow the raising data quantitative change to be processed of display device resolution huge, require data processing at a high speed.On the other hand, also require low consumption electrification as described above.Specifically, require to reduce driving voltage, and the lower voltage of data processing at a high speed and driving voltage is compromise (tradeoff) relation in order to the device of realizing the low consumption electrification.
Adopt following structure about this point is general: data transfer rate is very fast on actuation time of the internal circuit that is used for data processing and data transfer rate, a plurality of latching sections that latch data is set are first latch cicuit and second latch cicuit etc. for example, the maintenance data are also guaranteed during the action of internal circuit, thereby are realized high speed processing and low consumption electrification.
The spy opens to disclose in the 2000-356975 communique first and second latchs is set, and reduces the structure of the stray capacitance that produces on data supply line and the intersection region in order to the control signal wire of data-driven simultaneously.
The load of stray capacitance is different because of what of the point (point) of each signal wire intersection region, can not carry out the problem that normal view data transmits because of the deviation of the transfer rate of data supply line for example takes place for the difference of this load.In addition, also have the problem of the circuit power consumption increase of driving data supply line during heavy duty, can carry out processing at a high speed and can further reduce power consumption according to the structure of above-mentioned communique.
But, the structure that just reduces the stray capacitance that produces at the data supply line of supplying with view data with in order to the intersection region of the control signal wire of drive control signal in the above-mentioned communique is illustrated, but not only still produces stray capacitance on each intersection region at each data supply line at control signal wire.And, as mentioned above, follow the raising of the resolution of display device also to rise in order to the transmitted frequency of the data supply line that transmits at a high speed huge data volume (below, also be called data bus).
Thereby, because being bus capacitance, the stray capacitance that the intersection region between data bus produces increases, might cause power consumption to increase.In addition, the deviation because of transfer rate as described above may not transmit normal view data.
Summary of the invention
The present invention forms for addressing the above problem design, aims to provide by reducing bus capacitance, can realize the processing at a high speed and the drive unit of low consumption electrification, and the image display device and the portable set that is provided with this image display device that are provided with this drive unit.
Driving circuit of the present invention is the driving circuit that drives image displaying part, this image displaying part is provided with a plurality of image-displaying members of rectangular configuration, and a plurality of image-displaying members are divided into a plurality of, wherein be provided with: be provided with respectively corresponding to a plurality of, receive many chromosomes of constituting in order to a plurality of bit data of the view data that shows at image displaying part separately as the data supply line; Be provided with corresponding to each view data supply line, respond the first latch cicuit portion that first indicator signal latchs the view data that sends correspondence image data supply line to; Be provided with corresponding to each first latch cicuit portion, respond the second latch cicuit portion that second indicator signal latchs the view data that the corresponding first latch cicuit portion latchs; Transmit the first and second indicator signal lines of first and second indicator signals.Many chromosomes are as the not configuration across each other of data supply line.
Preferably be provided with image displaying part and above-mentioned driving circuit in the image display device.
Particularly, be provided with above-mentioned image display device in the portable set.
In driving circuit of the present invention, image display device and the portable set, therefore many chromosomes reduce the stray capacitance of the intersection region generation of each view data supply line, and can realize processing and low consumption electrification at a high speed as the not configuration across each other of data supply line.
For above-mentioned and other purpose, feature, form and advantage of the present invention, below will provide clear elaboration about detailed description of the present invention by what accompanying drawing was understood.
Description of drawings
Fig. 1 is the integrally-built schematic block diagram of the image display device of the expression embodiment of the invention 1.
Fig. 2 is the circuit diagram of the structure of expression liquid crystal display part shown in Figure 1.
Fig. 3 is the schematic block diagram of the horizontal scanning circuit of the explanation embodiment of the invention 1.
Fig. 4 is the structural drawing that describes the first latch cicuit group of the embodiment of the invention 1 and the second latch cicuit group's a part in detail.
Fig. 5 is the circuit structure diagram of the latch cicuit of the embodiment of the invention 1.
Fig. 6 is the sequential chart of input form of input data of the data bus of the explanation input embodiment of the invention 1.
Fig. 7 is one one the concept map that describes the first and second latch cicuit groups of the embodiment of the invention 2 in detail.
Fig. 8 is the first and second latch cicuit groups' the pie graph of a part that describes the variation of the embodiment of the invention 2 in detail.
Fig. 9 is the structural drawing of latch cicuit of the variation of the embodiment of the invention 2.
Figure 10 A, Figure 10 B are the key diagrams that is installed on the electrical equipment of image display device.
Embodiment
Below, the embodiment that present invention will be described in detail with reference to the accompanying.In addition, part same or suitable among the figure adopts prosign, does not repeat its explanation.
With reference to Fig. 1, be provided with liquid crystal display part 5 (image displaying part), vertical scanning circuit 2, the horizontal scanning circuit 3 of display image in the image display device 1 of the embodiment of the invention 1.Also have, image display device 1 receives a plurality of digital signal input from the composing images data DTA of frame memory 20.
Liquid crystal display part 5 comprises a plurality of liquid crystal cells of aftermentioned of rectangular configuration.Each liquid crystal cell is provided with arbitrary colored filter in R (red), G (green) and B (indigo plant) three primary colors, and constituting a unit of display at the adjacent liquid crystal cell of column direction (R), liquid crystal cell (G) and liquid crystal cell (B) is pixel.In addition, corresponding to many gate lines of row configuration of liquid crystal cell, dispose many roots polar curve corresponding to the row of liquid crystal cell.
Comprise demultiplexer group 4, analogue amplifier group 6, D/A translation circuit group 8, the second latch cicuit group 10, the first latch cicuit group 12, shift register 14 and many single data bus DB in the horizontal scanning circuit 3.
Import the first latch cicuit group 12 from the view data DTA of frame memory 20 inputs via data bus DB.The first latch cicuit group, 12 responses are from the indicating lock deposit data of shift register 14, and the second latch cicuit group, 10 responses are from exporting to D/A translation circuit group 8 behind the further latch data of the indication of shift register 14.
D/A translation circuit group 8 will latched data be that digital signal conversion becomes simulating signal in the second latch cicuit group 10.In analogue amplifier group 6, amplify then, and export to demultiplexer group 4.
It is the corresponding display voltage of video data that demultiplexer group 4 receives with the simulating signal of amplifying, cut apart by the display voltage time that will receive, and via each source electrode line of correspondence, to each unit of display output and liquid crystal cell (R), liquid crystal cell (G) and corresponding display voltage of liquid crystal cell (B) of the gate line of selecting.
The structure of liquid crystal display part shown in Figure 15 is described with reference to Fig. 2.The part of liquid crystal display part 5 only is shown because of the relation of drawing among Fig. 2 in addition.
With reference to Fig. 2, comprise a plurality of liquid crystal cell PX, many gate lines G L and many roots polar curve SL in the liquid crystal display part 5.Each free N channel thin-film transistor 102 of a plurality of liquid crystal cell PX, electric capacity 104 and liquid crystal display cells 106 constitute.Below thin film transistor (TFT) is called " TFT (Thin FilmTransistor) ".
The rectangular configuration of a plurality of liquid crystal cell PX is along many gate lines G L of its row configuration, along many roots of row configuration polar curve SL.Therefore, a plurality of liquid crystal cell PX are connected with gate lines G L with corresponding source electrode line SL separately.In addition, a plurality of liquid crystal cell PX accept opposed electrode voltage VCOM separately jointly.
As an example, and the liquid crystal cell PX of the capable j row of i (i, j) N channel TFT 102 is connected between source electrode line SL (j) and the node 108 in (i, j are the integers more than 2), and the gate lines G L (i) that is connected with the vertical scanning circuit is connected with grid.Liquid crystal display cells 106 is provided with the liquid crystal cell electrode that is connected with node 108 and applies the opposite electrode of opposed electrode voltage VCOM.One side of electric capacity 104 is connected with node 108, and the opposing party is fixed in opposed electrode voltage VCOM.
Liquid crystal cell PX (i, j) in, change the orientation of the liquid crystal in the liquid crystal display cells 106 according to the potential difference (PD) between liquid crystal cell electrode and the opposite electrode, thereby change the brightness (reflectivity) of liquid crystal display cells 106.Thereby, can on liquid crystal display cells 106, show the brightness (reflectivity) corresponding with the display voltage that applies via source electrode line SL (j) and N channel TFT 102.
Then, activate gate lines G L (i) with vertical scanning circuit 2, apply display voltage from source electrode line SL (j) to liquid crystal display cells 106, then, gate lines G L (i) deactivation, N channel TFT 102 is ended, but between the off period of N channel TFT 102, electric capacity 104 also can keep the current potential of liquid crystal cell electrode, so liquid crystal display cells 106 can be kept the brightness corresponding with the display voltage that applies (reflectivity).In addition, in other liquid crystal cell PX, adopt same spline structure, therefore do not repeat its detailed description.
The horizontal scanning circuit 3 of the embodiment of the invention 1 is described with reference to Fig. 3.
With reference to Fig. 3, comprise in the horizontal scanning circuit 3 of the embodiment of the invention 1: the demultiplexer group 4 that a plurality of 1:8 demultiplexer DM constitute, the analogue amplifier group 6 that a plurality of analogue amplifier AM constitute, the D/A translation circuit group 8 that a plurality of D/A translation circuit DAC constitute, the first latch cicuit group 12 that a plurality of first latch cicuits constitute, the second latch cicuit group 10 that a plurality of second latch cicuits constitute, data bus DB1～DB22, and data terminal DQ1～DQ22.
In addition, be provided with the signal wire and the signal wire that transmits the control signal LATB that controls second latch cicuit of the control signal LATA1～LATA18 of control first latch cicuit that transmits shift register 14 (not shown) output.
In this structure, be that the liquid crystal display part 5 of 176 pixels is illustrated with regard to the pixel count of horizontal direction setting.That is, be the structure that disposes 176 * 3=528 liquid crystal cell in the horizontal direction.And liquid crystal display part 5 becomes a plurality of along divided in horizontal direction.Specifically, in this example, be provided with 528 source electrode lines of S001～S528, be divided into the piece of the source electrode line that is provided with 24 group corresponding to row.Then, correspond respectively to a plurality of many single data bus DB is set.Corresponding to the piece that is provided with source electrode line S001～S024 data bus DB1 is set.And, data bus DB2 is set corresponding to the piece that is provided with source electrode line S025～S048.Similarly the piece corresponding to S505～S528 is provided with data bus DB22.Each data bus DB receives the view data input from data terminal DQ.That is, in this structure, each piece is the structure that receives view data from a single data bus DB, and each data bus DB is configured to not intersect each other.
In addition, the control signal LATA1～LATA18 and the LATB of shift register 14 outputs also are configured to not intersect with data bus DB.
Describe first a latch cicuit group 12 of the embodiment of the invention 1 and the second latch cicuit group's 10 a part in detail with reference to Fig. 4.
In this example, first and second latch cicuits corresponding with data bus DBk and DBk+1 are shown.
With reference to Fig. 4, the view data that the input and latch data bus DBk of 18 first latch cicuit LA difference responsive control signal LATA1～LATA18 transmits.In addition, the view data that latchs of 18 latch cicuit LA of input and latch of the second latch cicuit LB responsive control signal LATB.Because data bus DBk+1 also is same structure, does not repeat its detailed description.
With reference to Fig. 5, the latch cicuit LA of the embodiment of the invention 1 comprises transmission gate 201,204 and phase inverter 202,203,205,206.
Input data DTA is sent to node N0 via transmission gate 201.The data DTA that passes to node N0 is anti-phase and send output node N1 to via phase inverter 205.The signal that passes to output node N1 passes to node N0 via phase inverter 206 and transmission gate 204.Form latch by this phase inverter 205 and 206.Transmission gate 201 receives via the inversion signal of the control signal LATA of phase inverter 202 inputs with via the control signal LATA of phase inverter 202 and 203 inputs, and will import data DTA and send node N0 to.
Specifically, the input of transmission gate 201 responsive control signal LATA (" H " level) will be imported data DTA and send node N0 to.Be in cut-off state when control signal LATA (" L " level).Transmission gate 204 receives via the inversion signal of the control signal LATA of phase inverter 202 inputs with via the control signal LATA of phase inverter 202 and 203 inputs, and the signal that will send node N1 to passes to node N0.Specifically, the input of transmission gate 204 responsive control signal LATA (" L " level) is passed to node N0 with the signal that sends node N1 to.Be in cut-off state when control signal LATA (" H " level).The logic level of latch cicuit LA responsive control signal LATA in the structure of the present invention and its inversion signal latch in the transmission gate 201,204 of portion and the phase inverter 205,206 in formation and to latch input data DTA.Also have, in this structure, the control signal LATA of input is single, utilizes internal inverters 202,203 to generate its anti-phase control signal.Thereby, can reduce to transmit the signal number of lines of control signal LATA.In addition, the structure of latch cicuit LB only is that with the difference of above-mentioned latch cicuit LA the control signal LATB that imports is different.
With reference to Fig. 6, the input form of the input data DTA1～DTA22 of the data bus of importing the embodiment of the invention 1 is described.
As shown in Figure 6, in first scanning, to each data terminal DQ input image data DTA1～DTA22 successively.In this structure, each data terminal DQ is imported in the view data serial.Specifically, DQ1～DQ22 supplies with data DTA1～DTA22 respectively to the data terminal, focuses on data terminal DQ1 as an example, at initial moment t1, imports the view data of the S001 (1) corresponding with source electrode line S1.Then, this is t1 input control signal LATA1 (" H " level) constantly, and image bit data S001 (1) is latched in the first latch cicuit LA.Then, among the moment t2... that follows, S001 (2), S001 (3) ... the 6 bit image bit data serials input of S001 (6) after control signal LATA2～LATA6 (" H " level) input, is latched in the first latch cicuit LA successively.Here mark (X) expression is in order to the bit data of the regulation output voltage corresponding with source electrode line S001.Specifically, as the 1st of an example (1) expression, the 6th of (6) expression.Constitute the view data of a pixel cell by this 6 bit image bit data.Similarly, the 6 bit image data of the 6 bit image data of input source polar curve S009, S017 in the back, responsive control signal LATA7～LATA18 input is latched.After during the input of these 18 bit image data, input control signal LATB (" H " level), the image bit data that latch in 18 latch cicuit LA latch in second latch cicuit.This a series of processing is equivalent to first scanning.
Be latched in the image bit data of second latch cicuit, the source electrode line of correspondence be driven into predetermined voltage by D/A translation circuit DAC and analogue amplifier AM and 1:8 demultiplexer DM.Specifically, source electrode line S001, S009, S017 are driven to the predetermined voltage of per 6 image bit data correspondence.
As mentioned above, by D/A translation circuit DAC and analogue amplifier AM and 1:8 demultiplexer DM drive corresponding source electrode line during beginning second scanning.Specifically, the image bit data serial input corresponding with source electrode line S002, S010, S018.Repeat same processing.Each data terminal DQ2～DQ22 is also carried out same processing concurrently.Also have, 1:8 demultiplexer DM is 8 phases, shows on liquid crystal display part 5 through the 8th whole view data of processing that scans.
In this structure, as shown in Figure 3, data bus DB is set, does not make configuration across between each data bus DB simultaneously by each piece.Thereby, reduce the stray capacitance that the intersection region between data bus produces, can realize processing and low consumption electrification at a high speed.
And, the control signal LATA1～LATA18 and the LATB of input first latch cicuit and second latch cicuit are not disposed across with data bus DB.Thereby, can reduce also that data bus DB intersects with the signal wire that transmits control signal LATA and LATB and the stray capacitance that produces, can realize the processing and the low consumption electrification of high speed.Also have, in this structure, as an example, just drive be provided with 176 pixels promptly the structure of the driving circuit of the liquid crystal display part of 528 root polar curve S001～S528 be illustrated, but the structure of driving circuit is not limited to said structure, the number that can adopt data terminal DQ is that 22, the number of first, second latch cicuit of each terminal DQ correspondence are the structure that 24, demultiplexer number are made as 6 phases, or the number of data terminal DQ is that 33, the number of first, second latch cicuit are the structure that 12, demultiplexer number are made as 8 phases.
With reference to Fig. 7, describe the first and second latch cicuit groups' of the embodiment of the invention 2 a part in detail.Here, first and second latch cicuits corresponding with data terminal DQk and DQk+1 are shown.
This routine difference is the first latch cicuit group 12 is replaced as the first latch cicuit group 12#.
The difference of the first latch cicuit group 12# is corresponding to data bus DB level translator LSF to be set.The general operation voltage that constitutes the TFT of pixel is because of the high voltage that needs to supply with more than the 5V (volt) of threshold value of TFT.
Thereby in the past as the drive voltage level of data bus DB, the state of using the amplitude level with data-signal to shift is that the driving voltage more than the 5V is supplied with the image bit data.
In this structure, before first latch cicuit LA input data, level translator LSF is being set from data bus DB.
Promptly, by this structure, for example drive the data-signal that transmits data bus DB with the driving voltage about 3V, and by be amplified to the amplitude level about 5V with level translator LSF, the amplitude level of the data-signal of data bus DB can be reduced, and the power consumption that consumes in the data bus can be further suppressed.
The variation of embodiment 2
With reference to Fig. 8, the first and second latch cicuit groups' of the variation of the detailed description embodiment of the invention 2 a part.
With reference to Fig. 8, the difference of the structure of the variation of the embodiment of the invention 2 is to replace the first latch cicuit group 12# with the first latch cicuit group 12#a.Other parts repeat its detailed description equally and not.
The difference of the first latch cicuit group 12#a of the variation of the embodiment of the invention 2 is with latch cicuit LA# displacement latch cicuit LA.
With reference to Fig. 9, to compare with the latch cicuit LA of Fig. 5 explanation, the difference of the latch cicuit LA# of the variation of the embodiment of the invention 2 is to be provided with level translator 210.
Comprise phase inverter 207,208 and level buanch unit 209 in the level translator 210 with pooling feature.In this structure, the amplitude of the data-signal that transmits from data bus DB for example is made as above-mentioned 0～3 volt.That is, the first latch cicuit LA# is imported the data-signal of 0～3V.
Data bus DB discharges and recharges in the power consumption that causes, the power consumption that also exists the stray capacitance with opposite electrode to cause the cross capacitance except that between above-mentioned bus wiring.The data bus length of arrangement wire reaches tens of millimeter, enclosing source electrode driver from panel terminal, also becomes big value with the stray capacitance of opposite electrode.Therefore, data-signal not being carried out the level transfer and imports the first latch cicuit LA# is to low consumption electrification effective and efficient manner.
Among the first latch cicuit LA#, data latch part with 3 volts identical driven of data signal amplitude of input, just latched and afterwards transferred to the signal of 0～5V by level translator 210 level are set.Also have, the level to 5V of this level translator 210 shifts also can be right after before second latch cicuit and carries out, but the output of first latch cicuit causes load to increase because of coupling capacitance or the opposite electrode electric capacity with control signal LATA, and the buffer size that level translator 210 is had in order to ensure the sufficient driving force of 3V driving is that phase inverter 207 is very big, the power consumption that this can worsen layout area efficient and improve this buffer portion.
Thereby, on the first latch cicuit LA#, just carry out level after latching and shift 5V to drive impact damper, and realize dwindling layout area in the structure of the latch cicuit of the variation of present embodiment 2.
In addition, the needed time increases in the time of can suppressing with following mode to drive the first latch cicuit LA# and latch with 3V.Specifically, with the grid width/grid length (W/L) of the output transistor of the phase inverter 205 that constitutes the first latch cicuit LA# than comparing, the grid width/grid length of input transistors that is designed so that to constitute phase inverter 207 is little.
So in the first latch cicuit LA#, the W/L of input transistors that can be by reducing level translator 210 recently suppresses to latch the increase of needed time.
With reference to Figure 10 A, installed on the portable phone 1300 of image display device a plurality of action buttons 1302 and liquid crystal display part 1005 have been shown.
With reference to Figure 10 B, show display message output source 1000, display message treatment circuit 1002, power circuit 1004, image display device 1006 and the timing generator 200 of portable phone 1300 inside.Wherein, be provided with above-mentioned frame memory etc., ROM (Read Only Memory) or RAM storeies such as (Random Access Memory) in the display message output source 1000, the storage unit of various dishes etc., the interface circuit that the tuned circuit of tuning output image signal etc., execution are handled in order to the predetermined input of the input operation output display message of operation response button 1302 etc.In addition, based on the various clock signals that generate by timing generator 200, display message treatment circuit 1002 is supplied with the display message of the viewdata signal etc. of predetermined formats.Then, be provided with known various circuit such as rotation circuit, γ compensating circuit in the display message treatment circuit 1002, the processing of the display message of importing is supplied with image display device 1006 with this view data DTA with for example above-mentioned GCLK of various clock signals, SSLK or control signals such as commencing signal GST, SST.In addition, 1004 pairs of each component parts of power circuit are supplied with predetermined power source.
Also have,, can be used for the various display device of display message such as LCD TV, video recorder, automobile navigation apparatus for electronic equipment and indefinite, particularly portable set.
More than the present invention is had been described in detail, but only be example, do not constitute qualification of the present invention, should know that the spirit and scope of the present invention only are defined by the claims.
Claims (11)
1. driving circuit drives image displaying part, and described image displaying part is provided with a plurality of image-displaying members of rectangular configuration, and described a plurality of image-displaying member is divided into a plurality of, wherein is provided with:
Be provided with respectively corresponding to described a plurality of, and receive many chromosomes of constituting in order to a plurality of bit data of the view data that shows at described image displaying part separately as the data supply line;
Be provided with respectively as the data supply line corresponding to described many chromosomes, and respond a plurality of first latch cicuit portions that first indicator signal latchs the view data that sends correspondence image data supply line to separately;
Be provided with respectively corresponding to described a plurality of first latch cicuit portions, and respond a plurality of second latch cicuit portions that second indicator signal latchs the view data that the corresponding first latch cicuit portion latchs separately; And
Transmit the first and second indicator signal lines of described first and second indicator signals respectively,
Described many chromosomes are as the not configuration across each other of data supply line.
2. driving circuit as claimed in claim 1, it is characterized in that: also be provided with a plurality of digital to analog conversion portion that is provided with respectively corresponding to described a plurality of second latch cicuit portions, separately with the output signal of the second latch cicuit portion of correspondence from the digital signal conversion to the simulating signal, and export to described a plurality of image-displaying member.
3. driving circuit as claimed in claim 1 is characterized in that: described first and second indicator signal lines and described view data supply line be configuration across not.
4. driving circuit as claimed in claim 3 is characterized in that: at least one circuit part of each described first and second latch cicuit portion is connected with the second indicator signal line with the single described first indicator signal line;
At least one circuit part of each described first and second latch cicuit portion comprises the indicator signal that receives described at least one indicator signal line correspondence, with the negative circuit of its logic level anti-phase back output;
Each described first latch cicuit portion comprises response with the logic level of described first indicator signal and the anti-phase inverted logic level signal of logic level of described first indicator signal, latchs first of described bit data and latchs portion;
Each described second latch cicuit portion comprises response with the logic level of described second indicator signal and the anti-phase inverted logic level signal of logic level of described second indicator signal, latchs second of bit data that the first latch cicuit portion of described correspondence latchs and latchs portion.
5. driving circuit as claimed in claim 1 is characterized in that: each described view data supply line transmits a plurality of bit data of the view data that constitutes the serial input.
6. driving circuit as claimed in claim 1, it is characterized in that: also be provided with the level shifter that between the first latch cicuit portion of each described view data supply line and correspondence, is provided with, the little amplitude digital signal conversion of bit data is arrived the digital signal of large amplitude.
7. driving circuit as claimed in claim 1 is characterized in that: also be provided with level shifter, with the little amplitude digital signal conversion of bit data that the first latch cicuit portion is latched to the large amplitude digital signal and export to the second corresponding latch cicuit.
8. driving circuit as claimed in claim 7 is characterized in that: each described first latch cicuit portion is provided with the output transistor in order to the signal of output latch;
Described level shifter is provided with buffer circuit, and this buffer circuit is provided with the input transistors of the signal input that receives described output transistor output;
The size design of the input transistors of described buffer circuit is to below the size of described output transistor.
9. driving circuit as claimed in claim 8 is characterized in that: the channel width of described input transistors (W)/channel length (L) is designed to the channel width (W) of described output transistor/below the channel length (L).
10. an image display device that is provided with the described driving circuit of claim 1 also is provided with image displaying part.
11. a portable set is provided with the described image display device of claim 10.
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2004161704A JP2005345513A (en) | 2004-05-31 | 2004-05-31 | Driving circuit, image display apparatus and mobile device |
| JP161704/04 | 2004-05-31 |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN1705012A true CN1705012A (en) | 2005-12-07 |
| CN100449600C CN100449600C (en) | 2009-01-07 |
Family
ID=35497996
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CNB2005100763028A Expired - Fee Related CN100449600C (en) | 2004-05-31 | 2005-05-31 | Drive circuit and image display device employing same and portable device thereof |
Country Status (4)
| Country | Link |
|---|---|
| JP (1) | JP2005345513A (en) |
| KR (1) | KR100719053B1 (en) |
| CN (1) | CN100449600C (en) |
| TW (1) | TWI299845B (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101964171A (en) * | 2010-09-16 | 2011-02-02 | 深圳市明微电子股份有限公司 | Data transmission method and data receiving device |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP5218311B2 (en) * | 2009-07-17 | 2013-06-26 | 日本電気株式会社 | Image display device, image display method, and image display system |
Family Cites Families (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5529545A (en) * | 1993-02-23 | 1996-06-25 | Unitta Co., Ltd. | Toothed belt |
| JPH08227283A (en) * | 1995-02-21 | 1996-09-03 | Seiko Epson Corp | Liquid crystal display device, its driving method and display system |
| JPH0973062A (en) * | 1995-09-06 | 1997-03-18 | Citizen Watch Co Ltd | Liquid crystal display device |
| JP4011715B2 (en) * | 1997-03-03 | 2007-11-21 | 東芝松下ディスプレイテクノロジー株式会社 | Display device |
| JP2000356975A (en) * | 1999-06-16 | 2000-12-26 | Seiko Epson Corp | Driving circuit, electrooptical device and electronic equipment |
| TW554323B (en) * | 2000-05-29 | 2003-09-21 | Toshiba Corp | Liquid crystal display device and data latching circuit |
| JP5259904B2 (en) * | 2001-10-03 | 2013-08-07 | ゴールドチャームリミテッド | Display device |
-
2004
- 2004-05-31 JP JP2004161704A patent/JP2005345513A/en active Pending
-
2005
- 2005-04-20 TW TW094112543A patent/TWI299845B/en active
- 2005-05-23 KR KR1020050042873A patent/KR100719053B1/en not_active IP Right Cessation
- 2005-05-31 CN CNB2005100763028A patent/CN100449600C/en not_active Expired - Fee Related
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101964171A (en) * | 2010-09-16 | 2011-02-02 | 深圳市明微电子股份有限公司 | Data transmission method and data receiving device |
| CN101964171B (en) * | 2010-09-16 | 2013-05-22 | 深圳市明微电子股份有限公司 | Data transmission method |
Also Published As
| Publication number | Publication date |
|---|---|
| TWI299845B (en) | 2008-08-11 |
| TW200604993A (en) | 2006-02-01 |
| KR20060046132A (en) | 2006-05-17 |
| JP2005345513A (en) | 2005-12-15 |
| CN100449600C (en) | 2009-01-07 |
| KR100719053B1 (en) | 2007-05-16 |
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