CN1639860A - 埋入式垂直动态随机存储器单元及双工作功能逻辑门 - Google Patents
埋入式垂直动态随机存储器单元及双工作功能逻辑门 Download PDFInfo
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Abstract
本发明涉及埋入式垂直动态随机存储器单元及双工作功能逻辑门。一种产生极高密度埋入式DRAM/极高性能逻辑结构的工艺，包括制造具有自我对准硅化的源极/漏极的垂直MOSFET DRAM单元以及支撑中的栅极导体双工作功能MOSFETs。
Description
技术领域
本发明涉及制造埋入式垂直动态随机存储器(DRAM)单元(cell)及双工作功能逻辑门的工艺，尤其是关于极高密度埋入式DRAM和极高性能支撑的MOSFETs的新颖制造流程。
背景技术
MOSFET在形成动态随机存取存储器(DRAM)中被使用。DRAM电路通常包括由列及行连接在一起的单元阵列，该等行列已知分别为字线(wordlines)及位线(bitlines)。从记忆单元读出数据或写入数据至记忆单元是采用驱动被选择的字线及位线而达成的。通常，一个DRAM记忆单元包括连接至一个电容的一个MOSFET。此电容包括被称为漏极或源极区域的栅极扩散区域，依晶体管的运作而定。
有许多不同型态的MOSFETs。平面(planar)MOSFET是一种晶体管沟道区域的表面与基板的主要表面大致平行的晶体管。垂直(vertical)MOSFET是一种晶体管沟道区域的表面与基板的主要表面大致垂直的晶体管。沟槽(trench)MOSFET是一种晶体管沟道区域的表面不与基板的主要表面平行、且沟道区域位于基板内的晶体管。对沟槽MOSFET而言，沟道区域的表面通常与主要表面垂直，虽然这并非需要。
尤其是，沟槽电容经常与DRAM单元一起使用。沟槽电容是一种形成于一硅基板内的三维(dimension)结构。这一般采用蚀刻不同尺寸的沟槽至硅基板内而形成。沟槽通常具有N+掺杂多晶硅做为电容的一片(plate)(一个储存点)。电容的另一板通常采用从一个掺杂源扩散N+杂质至环绕沟槽的较低部份的基板的一部份之内而形成。在此二区域之间放置一个介电层以形成该电容。
为防止载体穿过相邻组件之间例如电容的基板的移动，在相邻半导体组件之间形成隔离区域。通常，组件隔离区域的形式为在半导体基板下方延伸的薄的场氧化物区域(field oxide region)。早期形成场氧化物区域的惯用技术是硅的区域氧化(local oxidation of silicon；LOCOS)技术。LOCOS场氧化区域的形成采用首先沉积一硅氮化物(“氮化物”)于基板表面上，然后有选择性地蚀刻硅氮化物的一部份以形成暴露将被形成场氧化的基板上的罩幕。该被屏蔽的基板被放置于一个氧化的环境中并于被罩幕暴露的区域上形成一个薄的氧化物层，形成在基板上方及下方延伸的一个氧化物层。另一种LOCOS场氧化的方式是使用浅沟槽隔离(shallow trenchisolation，“SIT”)。在SIT中，严格限定的沟槽采用例如异向(anisotropic)蚀刻而被形成于半导体基板内。由SIT所形成的沟槽隔离区域的优点在于提供跨越整个侧面延伸的组件隔离以及提供较平面的结构。使用改善的隔离，尺寸上的持续降低是可能的。
目前DRAM技术中的沟槽经常朝向DRAM阵列中最小特征尺寸(F)的持续量测以及更小型单元布局(例如，7F2，6F2)的方向驱动。由于不断增加的阵列密度的需求，使用F＝150nm以及以上的沟槽储存电容之最新平面MOSFET单元面临基本的顾虑。为满足隔离电流(off-current)目标所需的增加的P型阱掺杂浓度造成阵列接面漏电流的明显增加，这降低了记忆时间。MOSFET的尺寸，采用其本身，将典型向阵列中的之垂直MOSFET存取晶体管的方向移转。
朝向最小特征尺寸之降低及增加集成水平的另一种干扰是半导体芯片客户对单一芯片上具有更多更多功能的产品的需求。例如，埋入的DRAM/逻辑(EDRAM)产品快速地流行。
对于在市场上具有竞争力的存储器产品，需要在芯片的DRAM部份具有极高的密度(对存储器的生产率)，因此具有极高的性能支持MOSFETs。达成此结合的目标是此工业的一项主要挑战。
发明内容
现在，依据本发明已经发展一种产生极高密度埋入式DRAM/极高性能逻辑结构的新颖工艺。此工艺包括：制造具有自我对准硅化(salicided)的源极/漏极以及支撑中的栅极导体双工作功能MOSFETs。此工艺的特征在于形成该支撑用的栅极导体的相同操作中限定阵列中无边界位接触的单一区块罩幕及蚀刻准位的使用。此工艺也提供自我对准(self-aligned)驱动区域(active area)的位线接触(对邻近上升的浅沟槽隔离(Raised ShallowTrench Isolation；RSTI)无边界)；并去除硼磷硅玻璃(Boron-Phospho-Silicide-Glass；BPSG)回流步骤，降低热来源并允许较浅的源极/漏极。
附图说明
附图1至18是一个DRAM阵列及支撑MOSFET在连续工艺步骤中的上视及剖面图。
具体实施方式
现在参照附图，图1表示包含驱动区域(AA)氮化物焊点(nitride pad)区域10及深沟槽(DP)区域12的DRAM阵列的上视图。一个储存电容形成于DT12的较低的部份内，具有位于上部的一个栅极导体20。阵列的剖面图表示于图2，支撑MOSFET的剖面图则表示于图3。所示的阵列及支撑中的结构代表遵循STI平坦化的结构。此领域中在硅基板内制造垂直MOSFETDRAMs的标准工艺经由限定驱动区域氮化物焊点区域10及浅沟槽隔离(SIT)14平坦化而被旋加。这些标准的工艺技术包括深沟槽内的储存电容的形成，沉积沟槽上部氧化物(TTO)16，阱植入17，位线扩散的植入19，原始焊点结构的移除，栅极氧化物18的生长，栅极多晶硅20沉积及平坦化，以及新焊点氮化物层10的沉积。驱动区域在新的焊点氮化物层10中被形成图案。
用以形成STI图案的氮化物层10被制造成足够薄以限定后续将被形成的字线堆栈的高度。此字线堆栈的高度必须允许硅化物层(例如，钨硅化物，WSix)的内容物及氧化物帽(cap)。如图4及5所示，使用一阵列栅极导体(GC)罩幕形成一光阻层(未示出)的图案。然后，氮化物层10及STI14被动态离子蚀刻(RIE’s)以形成波纹字线导体用的沟道13。被暴露的阵列GC多晶硅20随后可被形成凹陷以提供Wsix的内容物及帽氧化物层用的想要的高度。如图5所示的支撑MOSFET区域在此步骤期间并未被蚀刻。
回到图6至8，一个WSix层21被沉积至暴露的阵列GC多晶硅20及STI14中的沟道13内，且随后被平坦化至氮化物层10的上表面。WSix随后被形成凹陷；一个正硅酸乙酯(tetraethyl othosilicate；TEOS)层22被沉积至该凹陷内且随后被平坦化至氮化物层10的上表面，形成字线导体上的隔离帽。
接着，一个中波紫外线(mid ultra violet，MUV)光阻区块罩幕23被用于允许光阻对支撑的保护(图10)，而阵列氮化物10层在阵列中被移除。在阵列氮化物10层在阵列中被移除之后，暴露的多晶硅20被RIE至下方栅极氧化物18的表面以形成图9所示的结构。此技术在阵列中的每一处留下一薄的氧化物层22，除了将于其中形成扩散栓CB多晶硅的凹槽25以外。光阻罩幕23随后被移除。
回到图11及12，一个栅极(字线)侧壁氧化物随于凹陷25的侧壁上生长，随后沉积被主动离子蚀刻的一个TEOS氧化物层以形成字线侧壁上的一个氧化物间隔26。
此时，如图13及14所示，支撑中剩下的氮化物10被移除，并沉积未掺杂之多晶硅27的第二层N+位线植入19在工艺的早期，于形成栅极氧化物18之前被形成。于多晶硅27的沉积之前在字线导体之间的暴露表面进行额外的N+位线接触植入。
移至图15及16，高波紫外线DUV光阻层罩幕被用以限定支撑的扩散拴登陆焊点与门极的边界，其随后被RIE。栅侧壁间隔24随后使用标准技术在支撑中形成。支撑源极/漏极区域26与27，双工作功能多晶硅栅极导体28，以及扩散栓CB多晶硅29在各个步骤中被植入。间隔24及25同时被形成于位线多晶硅(CB多晶)29及支撑栅极导体28之侧壁上。一个隔离材料层(例如，SiO2，SiN)被均匀沉积且随后被异向蚀刻(例如，RIE)以形成间隔24及25。随后，栅极导体28的顶部、扩散栓29着陆焊点、以及源极/漏极扩散26/27以层32被自我对准硅化。
最后，参照图17及18，工艺以薄氮化物障碍蚀刻停止层34，接续中间层氧化物层36，例如BPSG(硼磷硅化物玻璃)的沉积而继续进行。随后，使用一个双波纹工艺，穿孔于第一次中间层氧化物层之RIE主动离子蚀刻之后打开。此双波纹工艺也形成位线用的金属联机沟道的第一层。氮化物障碍34随后被打开，钨40被沉积并抛光以使导体形成波纹至之前形成的联机沟道内。随后继续标准的程序以形成不同的联机准位、穿孔、以及中间层介电层。位线用的钨采用已知的CVD步骤被沉积至联机沟道内。
虽然所描述的为优选实施例，熟悉本领域的技术人员可在不脱离本发明的精神及范围的情况下对其进行不同的修改及取代。因此，可以了解的是，本发明仅采用例示的方式被公开，且这种例示和实施例不会解释成对权利要求的范围的限制。
Claims (6)
1.一种形成一个记忆阵列及支撑晶体管的方法，包括：
在具有一个栅极氧化物层、一个多晶硅层、以及沉积于其上的一个上部介电氮化物层的一个硅基底内形成一个沟槽电容；
施加一个具有图案的罩幕于该阵列及支撑区域上，并于该氮化物层、该多晶硅层、以及浅沟槽隔离区域中形成凹陷；
在该氮化物层、该多晶硅层、以及浅沟槽隔离区域中的所述凹陷中形成一个硅化物和一个氧化物帽；
施加一个区块罩幕以保护该支撑，而将该氮化物层自该阵列移除并蚀刻该暴露的多晶硅层至该栅极氧化物层的顶部；
从该支撑区域移除该氮化物层并沉积一个多晶硅层于该阵列及支撑区域之上；
施加一罩幕以形成图案并形成该阵列中的一个位线扩散栓登陆焊点以及该支撑晶体管用的栅极导体；
自我对准硅化该登陆焊点及该栅极导体的上部；
施加一个中间层氧化物且随后打开建立导电联机信道用的该中间层氧化物中的穿孔。
2.按照权利要求1所述的方法，其特征在于，一个单一光阻罩幕被施加至该阵列的一个位线扩散栓登陆焊点以及支撑MOSFET的栅极导体。
3.按照权利要求1所述的方法，其特征在于，字线导体的形成是通过由于部份蚀刻该多晶硅层时施加一个中波紫外线罩幕来保护该支撑的。
4.按照权利要求1所述的方法，其特征在于，该登陆焊点及该栅极导体的上部同时被自我对准硅化。
5.按照权利要求1所述的方法，其特征在于，自我对准至该栅极氧化物层的一个位线接触是通过施加一区块罩幕并蚀刻该暴露的多晶硅层而形成的。
6.一种形成一个埋入式动态随机存储器阵列及支撑MOSFETs的方法，包括：
在具有一个栅极氧化物层、一个多晶硅层、以及沉积于其上的一个上部介电氮化物层的一个硅基底内形成一个沟槽电容，；
施加一个具有图案的罩幕于该阵列及该支撑区域上，并于该氮化物层、该多晶硅层、以及浅沟槽隔离区域中形成凹陷；
在该氮化物层、该多晶硅层、以及浅沟槽隔离区域中的所述凹陷中形成一个钨硅化物和一个氧化物帽；
施加一个区块罩幕以保护该支撑，而将该氮化物层自该阵列移除，并采用部份蚀刻该暴露的多晶硅层至该栅极氧化物层的上部而形成字线导体；从该支撑区域移除该氮化物层并沉积一个多晶硅层于该阵列及支撑区域之上；
施加一个单一罩幕以形成图案并形成该阵列中的一个位线扩散栓登陆焊点以及该支撑MOSFETs用之栅极导体；
同时自我对准硅化该登陆焊点及该栅极导体的上部；
施加一个中间层氧化物且随后打开建立导电联机信道用的该中间层氧化物中的穿孔。
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US09/725,412 | 2000-11-29 | ||
| US09/725,412 US6258659B1 (en) | 2000-11-29 | 2000-11-29 | Embedded vertical DRAM cells and dual workfunction logic gates |
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| Publication Number | Publication Date |
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| CN1639860A true CN1639860A (zh) | 2005-07-13 |
| CN100336203C CN100336203C (zh) | 2007-09-05 |
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| US (1) | US6258659B1 (zh) |
| EP (1) | EP1396010B1 (zh) |
| KR (1) | KR100392210B1 (zh) |
| CN (1) | CN100336203C (zh) |
| DE (1) | DE60129605T2 (zh) |
| TW (1) | TW512494B (zh) |
| WO (1) | WO2002045130A2 (zh) |
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| JP2001319928A (ja) * | 2000-05-08 | 2001-11-16 | Hitachi Ltd | 半導体集積回路装置およびその製造方法 |
| US6509226B1 (en) * | 2000-09-27 | 2003-01-21 | International Business Machines Corporation | Process for protecting array top oxide |
| US6610573B2 (en) * | 2001-06-22 | 2003-08-26 | Infineon Technologies Ag | Method for forming a single wiring level for transistors with planar and vertical gates on the same substrate |
| US6429068B1 (en) * | 2001-07-02 | 2002-08-06 | International Business Machines Corporation | Structure and method of fabricating embedded vertical DRAM arrays with silicided bitline and polysilicon interconnect |
| US6716734B2 (en) | 2001-09-28 | 2004-04-06 | Infineon Technologies Ag | Low temperature sidewall oxidation of W/WN/poly-gatestack |
| US6709926B2 (en) * | 2002-05-31 | 2004-03-23 | International Business Machines Corporation | High performance logic and high density embedded dram with borderless contact and antispacer |
| US6635526B1 (en) | 2002-06-07 | 2003-10-21 | Infineon Technologies Ag | Structure and method for dual work function logic devices in vertical DRAM process |
| US6750097B2 (en) | 2002-07-30 | 2004-06-15 | International Business Machines Corporation | Method of fabricating a patterened SOI embedded DRAM/eDRAM having a vertical device cell and device formed thereby |
| US6849495B2 (en) * | 2003-02-28 | 2005-02-01 | Infineon Technologies Ag | Selective silicidation scheme for memory devices |
| US6972266B2 (en) * | 2003-09-30 | 2005-12-06 | International Business Machines Corporation | Top oxide nitride liner integration scheme for vertical DRAM |
| US7018891B2 (en) * | 2003-12-16 | 2006-03-28 | International Business Machines Corporation | Ultra-thin Si channel CMOS with improved series resistance |
| US9190494B2 (en) | 2008-02-19 | 2015-11-17 | Micron Technology, Inc. | Systems and devices including fin field-effect transistors each having U-shaped semiconductor fin |
| US8866254B2 (en) | 2008-02-19 | 2014-10-21 | Micron Technology, Inc. | Devices including fin transistors robust to gate shorts and methods of making the same |
| US7742324B2 (en) * | 2008-02-19 | 2010-06-22 | Micron Technology, Inc. | Systems and devices including local data lines and methods of using, making, and operating the same |
| US7915659B2 (en) | 2008-03-06 | 2011-03-29 | Micron Technology, Inc. | Devices with cavity-defined gates and methods of making the same |
| KR100960443B1 (ko) | 2008-03-18 | 2010-05-28 | 주식회사 하이닉스반도체 | 반도체 소자의 제조방법 |
| US7808042B2 (en) | 2008-03-20 | 2010-10-05 | Micron Technology, Inc. | Systems and devices including multi-gate transistors and methods of using, making, and operating the same |
| US8546876B2 (en) * | 2008-03-20 | 2013-10-01 | Micron Technology, Inc. | Systems and devices including multi-transistor cells and methods of using, making, and operating the same |
| US7898857B2 (en) | 2008-03-20 | 2011-03-01 | Micron Technology, Inc. | Memory structure having volatile and non-volatile memory portions |
| US7969776B2 (en) | 2008-04-03 | 2011-06-28 | Micron Technology, Inc. | Data cells with drivers and methods of making and operating the same |
| US8076229B2 (en) * | 2008-05-30 | 2011-12-13 | Micron Technology, Inc. | Methods of forming data cells and connections to data cells |
| US8148776B2 (en) | 2008-09-15 | 2012-04-03 | Micron Technology, Inc. | Transistor with a passive gate |
| US8294511B2 (en) | 2010-11-19 | 2012-10-23 | Micron Technology, Inc. | Vertically stacked fin transistors and methods of fabricating and operating the same |
| US8536656B2 (en) * | 2011-01-10 | 2013-09-17 | International Business Machines Corporation | Self-aligned contacts for high k/metal gate process flow |
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| US5065273A (en) * | 1990-12-04 | 1991-11-12 | International Business Machines Corporation | High capacity DRAM trench capacitor and methods of fabricating same |
| JP3150496B2 (ja) * | 1993-06-30 | 2001-03-26 | 株式会社東芝 | 半導体記憶装置 |
| US5827765A (en) | 1996-02-22 | 1998-10-27 | Siemens Aktiengesellschaft | Buried-strap formation in a dram trench capacitor |
| JP2751909B2 (ja) * | 1996-02-26 | 1998-05-18 | 日本電気株式会社 | 半導体装置の製造方法 |
| US5937296A (en) * | 1996-12-20 | 1999-08-10 | Siemens Aktiengesellschaft | Memory cell that includes a vertical transistor and a trench capacitor |
| US5981332A (en) | 1997-09-30 | 1999-11-09 | Siemens Aktiengesellschaft | Reduced parasitic leakage in semiconductor devices |
| US5893734A (en) * | 1998-09-14 | 1999-04-13 | Vanguard International Semiconductor Corporation | Method for fabricating capacitor-under-bit line (CUB) dynamic random access memory (DRAM) using tungsten landing plug contacts |
| US6153902A (en) * | 1999-08-16 | 2000-11-28 | International Business Machines Corporation | Vertical DRAM cell with wordline self-aligned to storage trench |
| US6261894B1 (en) * | 2000-11-03 | 2001-07-17 | International Business Machines Corporation | Method for forming dual workfunction high-performance support MOSFETs in EDRAM arrays |
-
2000
- 2000-11-29 US US09/725,412 patent/US6258659B1/en not_active Expired - Lifetime
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2001
- 2001-11-14 KR KR10-2001-0070618A patent/KR100392210B1/ko not_active IP Right Cessation
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- 2001-11-28 CN CNB018197310A patent/CN100336203C/zh not_active Expired - Fee Related
- 2001-11-28 EP EP01995964A patent/EP1396010B1/en not_active Expired - Lifetime
- 2001-11-28 TW TW090129414A patent/TW512494B/zh not_active IP Right Cessation
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| Publication number | Publication date |
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| WO2002045130A2 (en) | 2002-06-06 |
| EP1396010B1 (en) | 2007-07-25 |
| KR20020042420A (ko) | 2002-06-05 |
| WO2002045130A3 (en) | 2004-01-08 |
| CN100336203C (zh) | 2007-09-05 |
| DE60129605T2 (de) | 2008-06-05 |
| US6258659B1 (en) | 2001-07-10 |
| KR100392210B1 (ko) | 2003-07-23 |
| TW512494B (en) | 2002-12-01 |
| EP1396010A2 (en) | 2004-03-10 |
| DE60129605D1 (de) | 2007-09-06 |
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