CN1675716A - Semiconductor memory device and data reading out method - Google Patents
Semiconductor memory device and data reading out method Download PDFInfo
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- CN1675716A CN1675716A CN03819523.2A CN03819523A CN1675716A CN 1675716 A CN1675716 A CN 1675716A CN 03819523 A CN03819523 A CN 03819523A CN 1675716 A CN1675716 A CN 1675716A
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- 239000003990 capacitor Substances 0.000 description 8
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- G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
- G11C11/22—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using ferroelectric elements
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Abstract
A semiconductor memory characterized by comprising a bit line, a transistor connected with the bit line, a ferroelectric memory cell connected with the bit line through the transistor, a shift circuit connected with the bit line and pulling down a data potential appearing on the bit line depending on the data stored in the memory cell, and a sense amplifier connected with the bit line and the ground potential, for amplifying the difference between the data potential pulled down by the shift circuit and the ground potential.
Description
Technical field
The present invention relates generally to semiconductor storage, be specifically related to the semiconductor storage of data storage in the ferroele ctric storage unit.
Background technology
In the ferroele ctric storer of 1T1C (1 capacitor of 1 transistor) mode, 1 bit information is stored in the storage unit.Under the situation of data " 1 ", accumulate electric charge in the storage unit, under the situation of data " 0 ", do not accumulate electric charge in the storage unit.In order to detect the storage data of this storage unit, take place greatlyyer and than the little reference potential of " 1 " data than " 0 " data, use sensor amplifier that the magnitude relationship of reference potential and data current potential is amplified.
In order to generate reference voltage, use and storage unit same circuits structure and reference cell that area is bigger than storage unit.Owing to use the storage unit of ferroele ctric to repeat polarization reversal, and long-time the continuation keep same data, makes its electrical characteristics deterioration.As for the reference cell that uses in reference voltage generating circuit, the deterioration of electrical characteristics takes place too.
About the characteristic of timeliness deterioration, it is different keeping the storage unit of " 1 " data and the storage unit of maintenance " 0 " data.Generally, reference cell has and the identical degradation characteristic of storage unit that keeps " 0 " data.Therefore, constant in order to read the necessary tolerance limit of reading of " 0 " data, irrelevant with the degree of timeliness deterioration, and for " 1 " data, along with the progress of timeliness deterioration, read tolerance limit and reduce.And because different for the access frequency of storage unit and reference cell, thereby to keep the storage unit of " 0 " data and the degradation characteristic of reference cell be not identical.
Therefore, the problem of existence is, when dispatching from the factory, owing to can not predict ferroele ctric storer deterioration in characteristics degree in the future, thereby be difficult in advance reference voltage be set for appropriate value.
Patent documentation 1
The spy opens the 2001-202776 communique
Patent documentation 2
The spy opens the 2000-285682 communique
Summary of the invention
In view of above problem, the purpose of this invention is to provide the 1T1C type ferroele ctric storer that a kind of reference voltage that does not use reference cell can detect " 0 " data and " 1 " data.
According to semiconductor storage of the present invention, it is characterized in that, comprising: bit line; The transistor that is connected with this bit line; Ferroele ctric storage unit by this bit line connection of this transistor AND gate; Shift circuit is connected with this bit line, and is to storage data that should storage unit that the data current potential that occurs on this bit line is drop-down; And sensor amplifier, being connected with earthing potential with this bit line, the data current potential after will be by this shift circuit drop-down and the potential difference (PD) of this earthing potential are amplified.
And the data read method in the semiconductor storage of the present invention is characterized in that, comprising: the step that data is read into bit line from the ferroele ctric storage unit; By from this bit line, extracting the drop-down step of data current potential that this bit line appears in electric charge out; And amplify the step of coming sense data by being somebody's turn to do by the potential difference (PD) of data current potential after drop-down and earthing potential.
Be provided with shift circuit in the present invention, this shift circuit is carried out the action that the bit line current potential is drop-down.Like this, the bit line current potential that is connected with the storage unit of data " 0 " is stabilized in the current potential lower than earthing potential.And, set appropriate amount for by drop-down amount the bit line current potential, the bit line current potential that is connected with the storage unit of data " 1 " is stabilized in the current potential higher than earthing potential.
Sensor amplifier is by using earthing potential as the reference current potential, increases the bit line current potential and with reference to the potential difference (PD) of current potential, determines sense data.Therefore, use the sensor amplifier of reference potential as earthing potential, can be judged as under the situation of positive potential is " 1 " data, is " 0 " data under the situation of negative potential.In structure of the present invention, do not use the reference voltage of reference cell like this, get final product suitable detection " 0 " data and " 1 " data.
Description of drawings
Fig. 1 is the figure of an example of the structure of expression semiconductor storage of the present invention.
Fig. 2 is the figure that action describes that reads that is used for ferroele ctric semiconductor storage of the present invention.
Fig. 3 is used for the sequential chart that the circuit operation to Fig. 2 describes.
Fig. 4 A is illustrated in the figure that the amount of polarization of the storage unit under the situation of data " 0 " changes, and Fig. 4 B is illustrated in the figure that the amount of polarization of the storage unit under the situation of data " 1 " changes.
Fig. 5 is the figure of an example of the circuit structure of the sense amplifier circuit that uses of expression the present invention.
Fig. 6 is the figure of an example of the expression circuit structure that generates the shift signal that the bit line current potential is drop-down.
Fig. 7 is the figure that the displacement of expression bit line allows the relation of signal BLSE and shift signal shift.
Fig. 8 is the figure of the timeliness deterioration of expression storage unit.
Fig. 9 is the figure of expression by the timeliness variation of the pulsewidth of the shift signal of the shift signal generative circuit generation of Fig. 6.
Figure 10 is illustrated in the figure that the timeliness of the bit line current potential under the situation of the shift signal generative circuit that uses Fig. 6 changes.
Figure 11 is used for the figure that another embodiment that reads action to ferroele ctric semiconductor storage of the present invention describes.
Figure 12 is used for the sequential chart that the circuit operation to Figure 11 describes.
Embodiment
Below, in conjunction with the accompanying drawings embodiments of the invention are elaborated.
Fig. 1 is the figure of an example of the structure of expression semiconductor storage of the present invention.
The semiconductor storage of Fig. 1 comprises: row address buffer 11, column address buffer 12, clock buffer 13, row decoder 14, column decoder 15, word line driver/anode line driver 16, memory cell array 17, WE impact damper 18, input buffer 19 writes amplifier 20, bit-line levels shifter 21, sensor amplifier 22, and output buffer 23.
In memory cell array 17, dispose in length and breadth a plurality of storage unit of ferroele ctric as memory element, corresponding each storage unit is provided with that the address that is used to read and write 1 bit data is specified and the circuit and the distribution of data transmission etc.Each storage unit is connected with bit line by controlled its cell transistor that is switched on or switched off by word line, and this bit line is connected with sensor amplifier 22.Sensor amplifier 22 by will from storage unit read on the bit line the data current potential with amplify with reference to the poor current potential of current potential, detect data.
Write under the situation that WE impact damper 18 designation datas that allow signal WE write obtaining from the outside, input buffer 19 is supplied with the input data that write from the outside and is write amplifier 20.Writing amplifier 20 will write the data amplification and supply with memory cell array 17.Sensor amplifier 22 detects sense data by amplifying from the data that memory cell array 17 is read.Output buffer 23 outputs to the outside to the sense data of supplying with from sensor amplifier 22 according to suitable sequential.
In the ferroele ctric storer,, HIGH voltage is imposed on another that be connected with anode line bring in and carry out data and write by when the data voltage of HIGH (height) or LOW (low) is imposed on an end of ferroele ctric element.By when selecting based on the word select of word line, the corresponding word line that is activated carries out the anode line selective activation data of selected storage unit are write.
The column address decoding that column decoder 15 will be supplied with from column address buffer 12, and with an alignment activation corresponding with column address.Like this, corresponding rowed transistor conducting can be carried out access to storage unit by the corresponding bit line of memory cell array 17.
Reading under the situation of action, data are read into bit line from the storage unit that is connected with the word line that is activated, detect bit line data by sensor amplifier 22.The sense data corresponding with the alignment that is activated is output to the outside by output buffer 23.Under the situation of write activity, supply with the data of input buffer 19 by being written in the storage unit that is connected with the word line that is activated with the alignment corresponding bit lines that is activated from the outside.Under the both sides' that read action and write activity situation, corresponding with the word line that is activated, the anode line selective activation that will be connected with storage unit.
Be provided with bit-line levels shifter 21 in the present invention.This bit-line levels shifter 21 is being read when action, between the both sides of word line and anode line are by the selectivity active period in, carry out the action that the bit line current potential is drop-down.Like this, the bit line current potential that is connected with the storage unit of data " 0 " is stabilized in the current potential lower than earthing potential after the non-activation with anode line.And, set appropriate amount for by drop-down amount the bit line current potential, the bit line current potential that is connected with the storage unit of data " 1 " is stabilized in the current potential higher than earthing potential after the non-activation with anode line.
Fig. 2 is the figure that action describes that reads that is used for ferroele ctric semiconductor storage of the present invention.Structure shown in Figure 2 is corresponding to the part that is associated with memory cell array 17, bit-line levels shifter 21 and the sensor amplifier 22 of Fig. 1.
Corresponding row address and being connected with the grid of nmos pass transistor 32 by the word line WL that selectivity activates.The source terminal of nmos pass transistor 32 is connected with an end of ferroele ctric storage unit 31, and drain electrode end is connected with bit line BL0 or BL1.The other end of storage unit 31 is with being connected by the anode line PL that selectivity activates with word line.
Bit line BL0 is connected with sense amplifier circuit 34 with BL1.Sense amplifier circuit 34 also with as the earth potential with reference to current potential (reference potential) is connected.And bit line BL0 is connected with BL1 and the response shift signal shift nmos pass transistor 33 that bit line potential levels is drop-down.
In in the past Up-Down (on-down) playback mode, during the word line selective activation being come storage unit carried out access, in that anode line is driven into HIGH (power supply potential VDD) afterwards from LOW (earthing potential), make anode line turn back to LOW, as a result the level that occurs on the readout bit line.Turn back to moment of LOW at bit line, the current potential that occurs on the bit line is positive potential under " 1 " data conditions, be earthing potential under " 0 " data conditions.
In the present invention, activated by selectivity and during anode line PL was HIGH, shift was set in HIGH shift signal, makes nmos pass transistor 33 conductings at word line WL.Like this, from bit line BLO and BL1, remove electric charge, the current potential of bit line BL0 and BL1 is drop-down.Afterwards, when making anode line PL turn back to LOW, the current potential of bit line BL0 and BL1 is to be stabilized in positive potential under the situation of " 1 " in the data of storage unit 31, is stabilized in negative potential under the situation that is " 0 ".
Therefore, use the sense amplifier circuit 34 of reference potential as earthing potential, can be judged as under the situation of positive potential is " 1 " data, is " 0 " data under the situation of negative potential.Like this, in structure of the present invention, there is no need to use the reference cell of reference potential generation usefulness.
Fig. 3 is used for the sequential chart that the circuit operation to Fig. 2 describes.
At first, with word line WL selective activation and be set in HIGH.Afterwards, when with anode line PL selective activation and when being set in HIGH, the current potential corresponding with the storage data of storage unit 31 appears on bit line BL0 and the BL1.In this embodiment, contain the data of " 0 ", contain the data of " 1 " at storage unit 31 internal memories that are connected with bit line BL1 at storage unit 31 internal memories that are connected with bit line BL0.
Then, between anode line PL was by the selectivity active period, shift was set in HIGH with shift signal.Like this, the electric charge on bit line BL0 and BL1 is removed, and current potential descends during shift signal shift HIGH.Afterwards, when making anode line PL turn back to LOW, the current potential of bit line BL0 and BL1 is stabilized in negative potential and positive potential separately.
Make after anode line PL turns back to LOW, the sensor amplifier activation signal SAEN that input activates sensor amplifier drives sense amplifier circuit 34.Like this, as the current potential of the bit line BL0 of negative potential, the difference of itself and earthing potential GND is exaggerated and becomes the minus side supply voltage VBB of regulation.And as the current potential of the bit line BL1 of positive potential, the difference of itself and earthing potential GND is exaggerated and becomes the positive side supply voltage VDD of regulation.
The amount of polarization that Fig. 4 A is illustrated in the storage unit under the situation of data " 0 " changes, and the amount of polarization that Fig. 4 B is illustrated in the storage unit under the situation of data " 1 " changes.
State shown in Fig. 4 A and Fig. 4 B 1. to 4. be equivalent to shown in Figure 3 during 1. to 4..Transverse axis represents to impose on the voltage of anode line PL, and longitudinal axis Pr represents the amount of polarization of storage unit.The hysteresis characteristic of the curve representation storage unit among the figure.In the storage data is under the situation of " 0 ", and the state of storage unit is positioned on the hysteresis curve of upside.In the storage data is under the situation of " 1 ", and the state of storage unit is positioned on the hysteresis curve of downside.
When the current potential of anode line PL was zero, storage unit was in state position 1..When the anode line potential setting during at HIGH, storage unit is in state 2..At this moment, the difference of the transverse axis position of the state 2. of current potential VO corresponding with the right-hand member of hysteresis curve and storage unit becomes the current potential that occurs on the bit line.Afterwards, by extracting bit line charge out, the bit line current potential reduces, and the state of storage unit moves to position 3..At this moment, the difference of the transverse axis position of the state 3. of current potential VO and storage unit is the current potential that occurs on the bit line.And when the current potential that makes anode line PL turned back to zero, the state of storage unit moved to position 4..At this moment, the difference of the transverse axis position of the state 4. of the transverse axis position of initial point O and storage unit is the current potential that occurs on the bit line.
That is, under the situation of the data shown in Fig. 4 A " 0 ", the bit line current potential is a negative level, and under the situation of the data shown in Fig. 4 B " 1 ", the bit line current potential is positive level (the negative direction of anode line current potential is corresponding with the positive direction of bit line current potential).
Is under the state 4. of generating positive and negative voltage at the bit line current potential according to the storage data, uses sensor amplifier 34 shown in Figure 2 that the difference of bit line and earthing potential is amplified and detects (reading) data.
Fig. 5 is the figure of an example of the circuit structure of the sense amplifier circuit 34 that uses of expression the present invention.The sense amplifier circuit 34 that the present invention uses and since read the current potential of object be positive and negative both, thereby be necessary to adopt the not only detection of positive potential, and the structure of problem also can not take place in the detection of negative potential.
The sense amplifier circuit 34 of Fig. 5 comprises: nmos pass transistor 41 to 45, PMOS transistor 46 to 48, and phase inverter 49.This sense amplifier circuit 34 is identical with the structure of common sensor amplifier, yet uses positive voltage VDD and negative supply voltage VBB as driving voltage.Negative supply voltage VBB is for example generated by the step-down voltage generative circuit that step-down voltage takes place by capacity coupled pumping action.
When sensor amplifier activation signal SAEN was HIGH, the difference of bit line BL and earthing potential was amplified in nmos pass transistor 45 and 48 conductings of PMOS transistor and activate sensor amplifier.
Fig. 6 is the figure of the example of the expression circuit structure that generates the shift signal shift that the bit line current potential is drop-down.
The shift signal generative circuit of Fig. 6 comprises: NAND circuit 51, phase inverter 52 and 53, ferroele ctric storage unit 54, and resistance 55.Storage unit 54 is storage unit formation components identical of using with the data storage of memory cell array 17.The electric capacity of this storage unit 54 is C, and the resistance value of resistance 55 is R.
When the bit line displacement allowed signal BLSE to be HIGH, the both sides of NAND circuit 51 were input as HIGH, and shift signal shift is HIGH.Afterwards, according to timeconstant by resistance R and capacitor C decision
CRPostpone, phase inverter 52 be input as HIGH.Like this, phase inverter 52 is output as LOW, and shift signal shift is LOW.
Fig. 7 is the figure that the displacement of expression bit line allows the relation of signal BLSE and shift signal shift.
As shown in Figure 7, shift signal shift allow from bit line displacement signal BLSE be HIGH during between T, become the signal of HIGH.Herein, T and timeconstant during
CRProportional.
Fig. 8 is the figure of the timeliness deterioration of expression storage unit 54.Storage unit 54 continues to keep same data to make the electrical characteristics deterioration owing to long-time, and its capacitor C is t minimizing in time as shown in Figure 8.Corresponding therewith, by the timeconstant of resistance R and capacitor C decision
CRAlso reduce.
Fig. 9 is the figure of expression by the timeliness variation of the pulsewidth of the shift signal of the shift signal generative circuit generation of Fig. 6.
When the capacitor C of storage unit 54 as shown in Figure 8 reduces in time, corresponding therewith, by the timeconstant of resistance R and capacitor C decision
CRDuring minimizing, as shown in Figure 9, by the shift signal shift that the shift signal generative circuit generates, its pulsewidth narrows down gradually.Like this, corresponding with the timeliness deterioration of the storage unit 31 (Fig. 2) of memory cell array 17 (Fig. 1), can suitably reduce the drop-down amount of current potential of bit line.
Figure 10 is illustrated in the figure that the timeliness of the bit line current potential under the situation of the shift signal generative circuit that uses Fig. 6 changes.
In Figure 10, transverse axis represent to storage unit read/write indegree, the longitudinal axis is represented the bit line current potential of the situation of the situation of data " 0 " and data " 1 ".Dotted line 61 is illustrated in the current potential that reads under the situation of data " 1 " on the bit line, solid line 63 expressions from the data current potential of reading " 1 " to by the bit line current potential behind the shift signal shift extraction electric charge.And dotted line 62 is illustrated in the current potential that reads under the situation of data " 0 " on the bit line, solid line 64 expressions from the data current potential of reading " 0 " to by the bit line current potential behind the shift signal shift extraction electric charge.
According to shift signal shift with current potential drop-down after, it is desirable to, the centre position of the current potential 64 of the current potential 63 of data " 1 " and data " 0 " just in time is as with reference to the earthing potential of current potential.This is because if the centre position is positioned at earthing potential, then can carries out the tolerance limit maximum and read with the data with reliability.
In Figure 10, shown in dotted line 61 and dotted line 62, along with the increase of reading/writing indegree, the data current potential of " 1 " descends gradually, and the data current potential of " 0 " rises gradually.The inclination that the data current potential of the rake ratio " 0 " that the data current potential of " 1 " descends rises is big.Therefore, suppose to fix by the drop-down potential shift amount of shift signal shift, according to shift signal shift with current potential drop-down after, the centre position of the current potential of the current potential of data " 1 " and data " 0 " descends gradually along with effluxion.
To this, when the potential shift amount is reduced like that gradually by A → B → C, by shift signal shift with current potential drop-down after, the centre position of the current potential 64 of the current potential 63 of data " 1 " and data " 0 " always is positioned near the earthing potential (current potential 0) and changes irrelevant with timeliness.
Therefore, if use the such shift signal generative circuit of Fig. 6, then as shown in Figure 9, the pulsewidth generation timeliness of shift signal shift changes and reduces gradually, and the drop-down amount of the current potential of the bit line of memory cell array 17 suitably reduces.Like this, as shown in figure 10, the centre position of the current potential of the current potential of data " 1 " and data " 0 " always is positioned near the earthing potential (current potential 0) and changes irrelevantly, can realize that the data of guaranteeing abundant tolerance limit and having reliability read with timeliness.
In addition, in the structure of Fig. 6, capacitor C is realized by storage unit 54, yet also can be realized by ordinary capacitor.In the case, the pulsewidth of shift signal shift is fixed, even effluxion, the potential shift amount of bit line is also constant.In the case, tolerance limit is compared with the situation of Figure 10 and is reduced, yet suitably sets the pulsewidth of shift signal shift if expect the timeliness of data current potential to change, and can keep for a long time and can carry out the state that normal data is read.
And, make the structure of the pulse width variations of shift signal be not limited to as the structure of Fig. 6, rely on the timeliness of storage unit 54 to change the structure that realizes, for example also can consider to adopt according to the value of in register, setting and adjust pulsewidth, suitably set the various circuit implementation methods of the structure etc. of this register value.
Figure 11 is used for the figure that another embodiment that reads action to ferroele ctric semiconductor storage of the present invention describes.Structure shown in Figure 11 is compared with structure shown in Figure 2, and nmos pass transistor 33 is replaced as buffer-type transistor 33A.The gate terminal of transistor 33A is connected with bit line, forms diode and connects.
Word line WL activated by selectivity and anode line PL HIGH during, when the bit line current potential from zero when positive direction rises, transistor 33A conducting and action are so that extract electric charge out.Like this, when anode line PL turned back to earth level GND once more, the current potential of bit line BL0 and BL1 was to be stabilized in positive potential under the situation of " 1 " in the data of storage unit 31, is stabilized in negative potential under the situation that is " 0 ".
Therefore, use the sense amplifier circuit 34 of reference voltage as earthing potential, can be judged as under the situation of positive potential is " 1 " data, is " 0 " data under the situation of negative potential.Like this, in the structure of present embodiment, owing to do not use shift signal shift, thereby there is no need to be provided with the circuit that shift signal takes place.
Figure 12 is used for the sequential chart that the circuit operation to Figure 11 describes.
At first, with word line WL selective activation and be set in HIGH.Afterwards, when with anode line PL selective activation and when being set in HIGH, the current potential corresponding with the storage data of storage unit 31 appears on bit line BL0 and the BL1.In this embodiment, contain the data of " 0 ", contain the data of " 1 " at storage unit 31 internal memories that are connected with bit line BL1 at storage unit 31 internal memories that are connected with bit line BL0.
When the data current potential appears on bit line BL0 and the BL1, transistor 33A conducting, the electric charge of bit line BL0 and BL1 is drawn out of, and its current potential descends.Afterwards, when making anode line PL turn back to LOW, the current potential of bit line BL0 and BL1 is stabilized in negative potential and positive potential separately.
Make after anode line PL turns back to LOW, the sensor amplifier activation signal SAEN that input activates sensor amplifier drives sense amplifier circuit 34.Like this, as the current potential of the bit line BL0 of negative potential, the difference of itself and earthing potential GND is exaggerated and becomes the minus side supply voltage VBB of regulation.And as the current potential of the bit line BL1 of positive potential, the difference of itself and earthing potential GND is exaggerated and becomes the positive side supply voltage VDD of regulation.
More than, the invention has been described according to embodiment, yet the invention is not restricted to the foregoing description, can carry out various distortion in the described scope of claim.
Claims (10)
1. a semiconductor storage is characterized in that, comprising:
Bit line;
The transistor that is connected with this bit line;
Ferroele ctric storage unit by this bit line connection of this transistor AND gate;
Shift circuit is connected with this bit line, and is to storage data that should storage unit that the data current potential that occurs on this bit line is drop-down; And
Sensor amplifier is connected with earthing potential with this bit line, and the data current potential after will be by this shift circuit drop-down and the potential difference (PD) of this earthing potential are amplified.
2. semiconductor storage according to claim 1, it is characterized in that, this shift circuit is the nmos pass transistor that when conducting this bit line is connected with this earthing potential, and comprises: the shift signal generative circuit, generation imposes on the shift signal of the grid of this nmos pass transistor.
3. semiconductor storage according to claim 2 is characterized in that this shift signal generative circuit can be adjusted the pulsewidth of this shift signal.
4. semiconductor storage according to claim 3 is characterized in that, this shift signal generative circuit makes the pulsewidth of this shift signal produce the timeliness variation.
5. semiconductor storage according to claim 4 is characterized in that, this shift signal generative circuit changes the pulsewidth generation timeliness variation that makes this shift signal according to the timeliness of the electric capacity of ferroele ctric storage unit.
6. semiconductor storage according to claim 1 is characterized in that, this shift circuit is the buffer-type transistor that when conducting this bit line is connected with this earthing potential, and the transistorized grid of this buffer-type is connected with this bit line.
7. semiconductor storage according to claim 1 is characterized in that, also comprises the anode line that is connected with this storage unit, and this shift circuit is connected this bit line during this anode line is activated with this earthing potential.
8. semiconductor storage according to claim 1, it is characterized in that, data current potential by this shift circuit after drop-down, be under 1 the situation in the storage data of this storage unit, be the current potential higher than this earthing potential, be under 0 the situation, to be the current potential lower in the storage data of this storage unit than this earthing potential.
9. semiconductor storage according to claim 1 is characterized in that, this sensor amplifier is driven by positive voltage and negative supply voltage.
10. the data read method in the semiconductor storage is characterized in that, comprising:
Data are read into the step of bit line from the ferroele ctric storage unit;
By from this bit line, extracting the drop-down step of data current potential that this bit line appears in electric charge out; And
Amplify the step of coming sense data by being somebody's turn to do by the potential difference (PD) of data current potential after drop-down and earthing potential.
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| PCT/JP2003/002268 WO2004077442A1 (en) | 2003-02-27 | 2003-02-27 | Semiconductor memory and method for reading data |
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|---|---|
| CN1675716A true CN1675716A (en) | 2005-09-28 |
| CN100505088C CN100505088C (en) | 2009-06-24 |
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| CNB038195232A Expired - Fee Related CN100505088C (en) | 2003-02-27 | 2003-02-27 | Semiconductor memory device and data reading out method |
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| Country | Link |
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| JP (1) | JP4154392B2 (en) |
| CN (1) | CN100505088C (en) |
| WO (1) | WO2004077442A1 (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN109416922A (en) * | 2016-06-27 | 2019-03-01 | 美光科技公司 | Multilayered memory in ferroelectric memory |
| CN114594819A (en) * | 2022-01-19 | 2022-06-07 | 之江实验室 | Circuit and method for self-adaptive regulating operating voltage capable of tracking ferroelectric capacitor process |
Families Citing this family (4)
| Publication number | Priority date | Publication date | Assignee | Title |
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| JP4638193B2 (en) * | 2004-09-24 | 2011-02-23 | パトレネラ キャピタル リミテッド， エルエルシー | memory |
| JP2006179048A (en) * | 2004-12-21 | 2006-07-06 | Sanyo Electric Co Ltd | Semiconductor device |
| JP2006216184A (en) * | 2005-02-04 | 2006-08-17 | Oki Electric Ind Co Ltd | Semiconductor memory device |
| JP2007052821A (en) * | 2005-08-15 | 2007-03-01 | Fujitsu Ltd | Ferroelectric memory |
Family Cites Families (1)
| Publication number | Priority date | Publication date | Assignee | Title |
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| JP2001319472A (en) * | 2000-05-10 | 2001-11-16 | Toshiba Corp | Semiconductor memory |
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2003
- 2003-02-27 JP JP2004568754A patent/JP4154392B2/en not_active Expired - Fee Related
- 2003-02-27 CN CNB038195232A patent/CN100505088C/en not_active Expired - Fee Related
- 2003-02-27 WO PCT/JP2003/002268 patent/WO2004077442A1/en active Application Filing
Cited By (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN109416922A (en) * | 2016-06-27 | 2019-03-01 | 美光科技公司 | Multilayered memory in ferroelectric memory |
| US10566043B2 (en) | 2016-06-27 | 2020-02-18 | Micron Technology, Inc. | Multi-level storage in ferroelectric memory |
| CN109416922B (en) * | 2016-06-27 | 2020-10-02 | 美光科技公司 | Multi-layer storage in ferroelectric memories |
| US11017832B2 (en) | 2016-06-27 | 2021-05-25 | Micron Technology, Inc. | Multi-level storage in ferroelectric memory |
| US11848042B2 (en) | 2016-06-27 | 2023-12-19 | Micron Technology, Inc. | Multi-level storage in ferroelectric memory |
| CN114594819A (en) * | 2022-01-19 | 2022-06-07 | 之江实验室 | Circuit and method for self-adaptive regulating operating voltage capable of tracking ferroelectric capacitor process |
| CN114594819B (en) * | 2022-01-19 | 2023-12-05 | 之江实验室 | Circuit and method for adaptively adjusting operating voltage for tracking ferroelectric capacitor process |
Also Published As
| Publication number | Publication date |
|---|---|
| CN100505088C (en) | 2009-06-24 |
| JP4154392B2 (en) | 2008-09-24 |
| WO2004077442A1 (en) | 2004-09-10 |
| JPWO2004077442A1 (en) | 2006-06-08 |
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