CN1525554A - Method for producing low-temperature polysilicon thin film transistor - Google Patents
Method for producing low-temperature polysilicon thin film transistor Download PDFInfo
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- CN1525554A CN1525554A CNA031053653A CN03105365A CN1525554A CN 1525554 A CN1525554 A CN 1525554A CN A031053653 A CNA031053653 A CN A031053653A CN 03105365 A CN03105365 A CN 03105365A CN 1525554 A CN1525554 A CN 1525554A
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Abstract
The invention is a manufacturing method for low temperature polysilicon thin film transistor. It forms polysilicon island type objects which are used as N-TFT and P-TFT on an insulating base board; deposits a grid electrode insulating layer and a grid electrode metal layer; patterns the grid electrode metal layer in order to form the grid electrode metal mantle and N-TFT grid electrode metal; carries on N-ion planting step to polysilicon island type objects, forms N-TFT and N-region; defines the grid electrode metal of P-TFT and the LDD structure of N-TFT by using an optical impedance pattern; carries on N+ ion planting to the polysilicon type objects, forms the S/D region of N-TFT, etches the metal mantle part where is not covered by optical impedance pattern, and forms the grid electrode metal of P-TFT; it uses the optical impedance pattern and grid electrode metal of P-TFT are used as mantle, carries on P+ ion planting to polysilicon island objects, forms the S/D region of P-TFT; eliminates the optical impedance pattern; forms S/D metal electrode of N-TFT and P-TFT; the invention can reduce the amount of mantle, and the N-TFT has LDD structure, it can upgrades the reliability of driving circuit and decreases the drain current, reduces the cost.
Description
Technical field
The invention relates to the manufacturing technology of a kind of low temperature polycrystalline silicon (LTPS) thin-film transistor, refer to a kind of CMOS improved process for making of low-temperature polysilicon film transistor especially.
Background technology
Along with thin-film transistor (thin-film transistors; TFTs) the quick progress of manufacturing technology has possessed frivolous, power saving and has not had LCD (the liquid crystaldisplay of advantages such as width of cloth ray; LCD) being widely used in various electronics such as computer, personal digital aid (PDA) (PDA), wrist-watch, notebook computer, digital camera, LCD and mobile phone produces brilliant.Add the positive input research and development of industry and adopt the production equipment that maximizes, the production cost of LCD is constantly descended, more make the demand of LCD heighten.
Present TFTLCD is divided into two kinds of amorphous silicon (a-Si) Thin Film Transistor-LCD and polysilicon (Poly-Si) Thin Film Transistor-LCDs.Low temperature polycrystalline silicon (Low TemperaturePoly-Silicon; LTPS) be Thin Film Transistor-LCD manufacturing process of new generation, so-called low temperature polycrystalline silicon (LTPS) technology mainly is to change the film of a-Si into polysilicon (Poly-Si) thin layer by annealing laser processing procedure (Laser Anneal).The transistor electronics translational speed of polysilicon improves hundred times than amorphous silicon, has that the display frame response speed is fast, advantages such as high brightness and high-res; In addition, because the electronics translational speed is fast, Poly-Si can be used as drive circuit, therefore peripheral driving circuit can be produced on the glass substrate, to alleviate its weight, reaches lightening requirement.Moreover, because LTPS TFT is incorporated into drive IC in the LCD panel, therefore the IC cost can be reduced, and the fraction defective that the processing of IC back segment is produced can be reduced, therefore also can promote yield.
In view of this, in the low temperature polycrystalline silicon processing procedure, must take the element characteristic demand of pixel internal transistor and drive circuit simultaneously into account.For reliability that can improve drive circuit simultaneously and the leakage current that reduces pixel, N-MOS with ldd structure (LDD) is preferable circuit design, because of it can reduce heat conduction to degradation phenomena that element or circuit caused, also can when back bias voltage, reduce near the drain electrode generating rate of electronics and electric hole in the vague and general layer and further reduce leakage current, to keep the required element characteristic of driving LCD.
See also Figure 1A to Fig. 1 K, these are graphic to be the steps flow chart schematic diagram of top grid (top gate) the LTPS CMOS processing procedure (peripheral driving circuit) of known techniques one relevant self-aligned.In known techniques one, used eight road light shields to produce the CMOS TFT element of peripheral driving circuit altogether, wherein N-TFT has the LDD structure.
Shown in Figure 1A, at first on an insulated substrate 1 (for example glass substrate), deposit a resilient coating 2 and an amorphous silicon film layer 3 in regular turn, the effect of this resilient coating 2 is that the impurity in avoiding this glass substrate 1 diffuses out because of follow-up high temperature process.Then, use excimer laser technology (Excimer Laser; EL) scan this amorphous silicon film layer 3, make this recrystallized amorphous silicon become polysilicon and form a polycrystalline silicon membrane 3 '.Afterwards, carry out micro image etching procedure, shown in Figure 1B, by one first photoresistance pattern 4 (using the first road light shield), will be at the polycrystalline silicon membrane 3 ' patterning on this glass substrate 1, desire a polysilicon island thing (poly island) 5 with formation, and then deposit a gate insulator 6, shown in Fig. 1 C as N-TFT and P-TFT.
Next, carry out the N+ ion implantation step of N-TFT, shown in Fig. 1 D, form one second photoresistance pattern 7 (using the second road light shield) on this gate insulator 6, wherein this second photoresistance pattern 7 this polysilicon island thing 5 that will be positioned at the LDD structure of N-TFT and area of grid partly covers and this polysilicon island thing 5 that will be positioned at whole P-TFT zone partly covers, and then this polysilicon island thing 5 is carried out the N+ ion and implant, form the S/D zone 8 of N-TFT.
Then, divest this second photoresistance pattern 7, and deposit a gate metal layer 9, shown in Fig. 1 E, carry out micro image etching procedure again, by one the 3rd photoresistance pattern 10 (using the 3rd road light shield), with these gate metal layer 9 patternings, to form the gate metal 9 ' of N-TFT and P-TFT, shown in Fig. 1 F.Afterwards, directly carry out N-ion implantation step as the cover curtain, form the LDD structure 11 of N-TFT with this gate metal 9 '.
Then, shown in Fig. 1 G, form one the 4th photoresistance pattern 13 (using the 4th road light shield), and P+ ion implantation step is carried out in the P-TFT zone, to form the S/D zone 14 of P-TFT with the whole N-TFT of cover zone.Carry out so far, the primary structure of N-TFT and P-TFT is roughly finished.
Next, divest the 4th photoresistance pattern 13, and deposit a dielectric layer 12 on this glass substrate 1, and cover this gate metal 9 ', and then this dielectric layer 12 and this gate insulator 6 are carried out micro image etching procedure, (figure does not show by a photoresistance pattern, use the 5th road light shield), form first interlayer hole 50 of N-TFT and P-TFT, to expose the S/D of N-TFT and P-TFT, shown in Fig. 1 H.Then, deposit a metal level and fill this first interlayer hole 50, then this metal level is carried out micro image etching procedure, (figure does not show by a photoresistance pattern, use the 6th road light shield), the S/D metal electrode 51 of formation N-TFT and P-TFT can be used as data line (dataline), connect with pixel region and this panel circuit external on this LCD panel, shown in Fig. 1 I.
Next; shown in Fig. 1 J; deposit a protective layer 52 on glass substrate 1; and cover this S/D metal electrode 51; this protective layer 52 is carried out micro image etching procedure, by a photoresistance pattern (figure does not show, uses the 7th road light shield); form second interlayer hole 53 of N-TFT and P-TFT, to expose S/D metal electrode 51 partly.Then, deposit an indium tin oxide layer (ITO) and fill this second interlayer hole 53, then this indium tin oxide layer is carried out micro image etching procedure, (figure does not show by a photoresistance pattern, use the 8th road light shield), form ITO connection electrode 54, can connect with this LCD panel circuit external, shown in Fig. 1 K.
In addition, see also Fig. 2 A to Fig. 2 D, these graphic top grid (top gate) LTPS CMOS processing procedures for known techniques two relevant self-aligneds differ from the steps flow chart schematic diagram of known techniques one.In known techniques two, at first form this polysilicon island thing (poly island) 5 of desiring as N-TFT and P-TFT with the step that is same as aforementioned Figure 1A to Fig. 1 C; Then deposit gate insulation layer 6.
Then, shown in Fig. 2 A, deposit a gate metal layer 19 on this gate insulator 6, carry out micro image etching procedure again, by one second photoresistance pattern 17 (using the second road light shield), will be at these gate metal layer 19 patternings, with the gate metal 19 ' that forms N-TFT and the gate metal cover 19 of P-TFT "; and divest this second photoresistance pattern 17, shown in Fig. 2 B, this gate metal cover 19 wherein " will cover fully in the part of this polysilicon island thing 5 in whole P-TFT zone.Afterwards, directly with this gate metal 19 ' and this gate metal cover 19 " as the cover curtain, carry out N+ ion implantation step, form the S/D zone 18 of N-TFT.
Then, carry out the P+ ion implantation step of P-TFT, shown in Fig. 2 C, form one the 3rd photoresistance pattern 20 (using the 3rd road light shield) in this gate metal 19 ' and this gate metal cover 19 " on; wherein the 3rd photoresistance pattern 20 will partly cover at gate metal 19 ' regional polysilicon island thing 5 parts and the polysilicon island thing 5 in whole N-TFT zone of P-TFT; and then with this gate metal cover 19 that do not covered in by the 3rd photoresistance pattern 20 " part etching oar, and the gate metal 19 ' of formation P-TFT carries out the P+ ion to this polysilicon island thing 5 then and implants and the S/D zone 24 of formation P-TFT.Then, divest the 3rd photoresistance pattern 20, shown in Fig. 2 D.This known techniques two has promptly been finished the primary structure of N-TFT and P-TFT after carrying out the 3rd road light shield.
Next, to be same as the step of earlier figures 1H to Fig. 1 K, use four road light shields to form S/D metal electrode 51 and the ITO connection electrode 54 of N-TFT and P-TFT.
In known techniques two, though only use seven road light shields altogether, produce CMOS TFT element, the N-TFT of made does not have the LDD structure.
Summary of the invention
Main purpose of the present invention promptly provides a kind of CMOS improved process for making method of low-temperature polysilicon film transistor, can reduce the light shield number of the required use of LTPS CMOS processing procedure, and makes the N-MOS circuit design with LDD structure simultaneously.
For reaching above-mentioned purpose, the present invention discloses a kind of CMOS manufacture method of low-temperature polysilicon film transistor.At first, on an insulated substrate, form the polysilicon island thing of desiring as a N-TFT and a P-TFT (poly island), deposit a gate insulator and a gate metal layer then in regular turn on this insulated substrate; Afterwards, this gate metal layer of patterning, with the gate metal cover of the gate metal that forms this N-TFT and this P-TFT, wherein, this gate metal cover will cover fully in the part of this polysilicon island thing in whole this P-TFT zone.Then, as the cover curtain, this polysilicon island thing is carried out N-ion implantation step, form the N-zone of this N-TFT with the gate metal of this N-TFT and this gate metal cover; Form a photoresistance pattern then on the gate metal cover of the gate metal of this N-TFT and this P-TFT, wherein a part of photoresistance pattern definition goes out the gate metal of this P-TFT, and another of this photoresistance pattern partly covers the gate metal that covers this N-TFT and the part gate insulator laminar surface of adjacency, to define the LDD structure of this N-TFT; Then this polysilicon island thing is carried out the N+ ion and implant, form the S/D zone of this N-TFT, and this gate metal cover part of not covered in of etching, form the gate metal of this P-TFT by this photoresistance pattern.Next, as the cover curtain, this polysilicon island thing is carried out the P+ ion implant, form the S/D zone of this P-TFT, divest this photoresistance pattern then with the gate metal of this photoresistance pattern and this P-TFT; Form the S/D metal electrode of this N-TFT and this P-TFT afterwards.
In above-mentioned manufacture method, by when forming the step of this photoresistance pattern on the gate metal cover of the gate metal of this N-TFT and this P-TFT, make the gate metal of the position of the photoresistance pattern on the gate metal that is formed on this N-TFT and this N-TFT symmetrical or asymmetric, can form the S/D zone of symmetric form or asymmetric N-TFT.
Moreover the present invention discloses a kind of LTPSCMOS manufacture method that defines the LDD structure of N-TFT by engraving method in addition.At first, on an insulated substrate, form the polysilicon island thing of desiring as a N-TFT and a P-TFT (poly island), deposit a gate insulator and a gate metal layer then in regular turn on this insulated substrate.Afterwards, this gate metal layer of patterning, with the first grid metal cap of the gate metal that forms this P-TFT and this N-TFT, wherein this first grid metal cap will cover fully in the part of this polysilicon island thing in whole this N-TFT zone; Then, as the cover curtain, this polysilicon island thing is carried out P+ ion implantation step, form the S/D zone of this P-TFT with the gate metal of this P-TFT and this first grid metal cap.Then, form a photoresistance pattern on the gate metal and this gate metal cover of this P-TFT, wherein this photoresistance pattern covers gate metal and the LDD structural region of whole this P-TFT zone and this N-TFT; Then, this first grid metal cap part that etching is not covered in by this photoresistance pattern forms the second grid metal cap of this N-TFT, and this polysilicon island thing is carried out the N+ ion implant, and forms the S/D zone of this N-TFT.Afterwards, as cover curtain, the sidewall of this second grid metal cap is carried out etching program, make this sidewall of this second grid metal cap produce retraction, and form the gate metal of this N-TFT, define the LDD structural region of this N-TFT simultaneously with this photoresistance pattern.Divest this photoresistance pattern then, as the cover curtain, this polysilicon island thing is carried out outer ion implant, form the LDD structure of this N-TFT, form the S/D metal electrode of this N-TFT and this P-TFT again with the gate metal of this N-TFT.
Beneficial effect of the present invention is, LTPS CMOS manufacture method of the present invention can reduce the use number of light shield and cost be reduced and the raising production capacity, and the N-TFT of made has the LDD structure, can improve the reliability of drive circuit and the leakage current that reduces pixel simultaneously, and yield is promoted.
Description of drawings
Figure 1A to Fig. 1 K is the steps flow chart schematic diagram of known techniques one about top grid (topgate) the LTPSCMOS processing procedure (peripheral driving circuit) of self-aligned;
Fig. 2 A to Fig. 2 D differs from the steps flow chart schematic diagram of known techniques one for the top grid LTPS CMOS processing procedure of the relevant self-aligneds of known techniques two;
Fig. 3 A to Fig. 3 G differs from the steps flow chart schematic diagram of known techniques for first embodiment of the CMOS manufacture method of low temperature polycrystalline silicon of the present invention (LTPS) thin-film transistor; Wherein:
Fig. 3 B ' is the plane graph of Fig. 3 B;
Fig. 3 G ' is the plane graph of Fig. 3 G;
Fig. 4 A to Fig. 4 B differs from the steps flow chart schematic diagram of first embodiment for second embodiment of the CMOS manufacture method of low temperature polycrystalline silicon of the present invention (LTPS) thin-film transistor; Wherein:
Fig. 4 B ' is the plane graph of Fig. 4 B;
Fig. 5 A to Fig. 5 G differs from the steps flow chart schematic diagram of known techniques for the 3rd embodiment of the CMOS manufacture method of low temperature polycrystalline silicon of the present invention (LTPS) thin-film transistor.
Embodiment
See also Fig. 3 A to Fig. 3 G, first embodiment of these graphic CMOS manufacture methods for low temperature polycrystalline silicon of the present invention (LTPS) thin-film transistor differs from the steps flow chart schematic diagram of known techniques.
At first, similarly,, form this polysilicon island thing (poly island) 5 of desiring as N-TFT and P-TFT, and then deposit this gate insulator 6 to be same as the step of aforementioned Figure 1A to Fig. 1 C.
Then, as shown in Figure 3A, deposit a gate metal layer 29 on this gate insulator 6, carry out micro image etching procedure again, by one second photoresistance pattern 27 (using the second road light shield), will be at these gate metal layer 29 patternings, with the gate metal 29 ' that forms N-TFT and the gate metal cover 29 of P-TFT "; and divest this second photoresistance pattern 27; shown in Fig. 3 B; this gate metal cover 29 wherein " will cover fully in the part of this polysilicon island thing 5 in whole P-TFT zone, Fig. 3 B ' is the plane graph of Fig. 3 B.Afterwards, directly with this gate metal 29 ' and this gate metal cover 29 " as the cover curtain, this polysilicon island thing is carried out N-ion implantation step, form the N-zone 21 of N-TFT, shown in Fig. 3 C.
Then, carry out the N+ ion implantation step of N-TFT, shown in Fig. 3 D, form one the 3rd photoresistance pattern 30 (using the 3rd road light shield) in this gate metal 29 ' and this gate metal cover 29 " on; wherein the 3rd photoresistance pattern 30 will partly and at the gate metal 29 ' of N-TFT and this polysilicon island thing 5 of LDD structural region partly cover (at this moment; just the length with this LDD structure accurately defines) at this polysilicon island thing 5 in the gate metal 29 ' zone of P-TFT; and then this polysilicon island thing 5 is carried out the N+ ion and implant; and form S/D regional 28 and the LDD structure 21 ' of N-TFT simultaneously, and shown in Fig. 3 E.
Then, with this gate metal cover 29 that is not covered in by the 3rd photoresistance pattern 30 " partially-etchedly fall, and form the gate metal 29 ' of P-TFT, shown in Fig. 3 F; then; directly with the 3rd photoresistance pattern 30 and this gate metal 29 ' as the cover curtain, this polysilicon island thing 5 is carried out the P+ ion implant, with the S/D zone 34 of formation P-TFT; afterwards; divest the 3rd photoresistance pattern 30, shown in Fig. 3 G, Fig. 3 G ' is the plane graph of Fig. 3 G.It should be noted that, when carrying out the implantation of P+ ion, for the S/D zone 28 (being the N+ zone) of N-TFT, be contra-doping (conter-dopping), therefore, employed N+ dosage and P+ dosage must be earlier through suitably allotments, so that the N+ zone that makes N-TFT still keeps N+ doping type and low resistance characteristic behind P+ ion implantation step.
LTPS CMOS processing procedure of the present invention carries out so far (having used three road light shields), the primary structure of N-TFT and P-TFT is also roughly finished, next, just, use four road light shields to form S/D metal electrode 51 and the ITO connection electrode 54 of N-TFT and P-TFT to be same as the step of earlier figures 1H to Fig. 1 K.
Moreover, utilize LTPS CMOS processing procedure of the present invention, the S/D zone that also can produce the N-TFT of asymmetrical type, this is the second embodiment of the present invention.
In a second embodiment, make the method for LTPS CMOS, major part is the steps flow chart as the aforementioned first embodiment of the present invention, but when carrying out the N+ ion implantation step of N-TFT (the 3rd road light shield), make the position of one the 3rd photoresistance pattern 40 on the gate metal 29 ' that is formed on N-TFT be asymmetric with this gate metal 29 ', shown in Fig. 4 A, LDD structure 31 length in the LDD of source area structure 31 ' that so defines the drain region that forms will be come longly; In other words, the S/D zone 38 of N-TFT just presents asymmetric, and shown in Fig. 4 B, Fig. 4 B ' is the plane graph of Fig. 4 B.
In addition, see also Fig. 5 A to Fig. 5 G, differ from the steps flow chart schematic diagram of known techniques for the 3rd embodiment of the CMOS manufacture method of low temperature polycrystalline silicon of the present invention (LTPS) thin-film transistor.
Similarly, being same as the step of aforementioned Figure 1A to Fig. 1 C, forming this polysilicon island thing (poly island) 5 of desiring as N-TFT and P-TFT, and then deposit this gate insulator 6.
Then, shown in Fig. 5 A, deposit a gate metal layer 39 on this gate insulator 6, carry out micro image etching procedure again, by one second photoresistance pattern 37 (using the second road light shield), will be at these gate metal layer 39 patternings, with the gate metal 39 ' that forms P-TFT and the first grid metal cap 39 of N-TFT "; and divest this second photoresistance pattern 37, shown in Fig. 5 B, this gate metal cover 39 wherein " will cover fully in the part of this polysilicon island thing 5 in whole N-TFT zone.Afterwards, directly with this gate metal 39 ' and this first grid metal cap 39 " as the cover curtain, this polysilicon island thing is carried out P+ ion implantation step, form the S/D zone 44 of P-TFT, shown in Fig. 5 C.
Then, shown in Fig. 5 D, form one the 3rd photoresistance pattern 45 (using the 3rd road light shield) in this gate metal 39 ' and this first grid metal cap 39 " on, wherein the 3rd photoresistance pattern 45 will partly and at the gate metal 39 ' of N-TFT and this polysilicon island thing 5 of LDD structural region partly cover at this polysilicon island thing 5 in whole P-TFT zone; Then, with this first grid metal cap 39 that is not covered in by the 3rd photoresistance pattern 45 " partly etch away; and form second grid metal cap 39 of N-TFT; wherein this second grid metal cap 39 cover the LDD structural region of N-TFT; and then this polysilicon island thing 5 is carried out the N+ ion and implant; and form the S/D zone 48 of N-TFT, shown in Fig. 5 E.
Next, with the 3rd photoresistance pattern 45 as cover curtain, use dry ecthing or wet etch techniques, sidewall (side wall) to this second grid metal cap 39 carries out etching program, make this sidewall of this second grid metal cap produce retraction, and the gate metal 39 ' of formation N-TFT also defines the LDD structural region at the N-TFT of this polysilicon island thing 5 simultaneously, shown in Fig. 5 F.Afterwards, divesting the 3rd photoresistance pattern 45, serves as the cover curtain with the gate metal 39 ' of N-TFT and P-TFT, this polysilicon island thing 5 is carried out the N-ion implant, to form the LDD structure 41 of N-TFT, shown in Fig. 5 G.
The LTPS CMOS processing procedure of the third embodiment of the present invention carries out so far (also only having used three road light shields), and the primary structure of N-TFT and P-TFT is roughly finished.Similarly, to be same as the step of earlier figures 1H to Fig. 1 K, use four road light shields to form S/D metal electrode 51 and the ITO connection electrode 54 of N-TFT and P-TFT.
With known techniques one and two mutually more as can be known, utilize manufacture method of the present invention, can reduce the light shield number of the required use of LTPS CMOS processing procedure of known techniques one, and produce the N-TFT that known techniques two is lacked with LDD structure.Therefore LTPS CMOS manufacture method of the present invention can reduce the use number of light shield and cost be reduced and the raising production capacity, and the N-TFT of made has the LDD structure, can improve the reliability of drive circuit and the leakage current that reduces pixel simultaneously, and yield is promoted.
Though the present invention discloses as above with preferred embodiment; right its is not in order to qualification the present invention, any those who are familiar with this art, without departing from the spirit and scope of the invention; when can doing a little change and retouching, so the present invention's protection range is as the criterion when looking claims scope person of defining.
Claims (10)
1. the CMOS manufacture method of a low-temperature polysilicon film transistor is characterized in that: comprising:
On an insulated substrate, form the polysilicon island thing of desiring as a N-TFT and a P-TFT;
On this insulated substrate, deposit a gate insulator and a gate metal layer in regular turn;
This gate metal layer of patterning, with the gate metal cover of the gate metal that forms this N-TFT and this P-TFT, wherein, the part that this gate metal cover will be positioned at this polysilicon island thing in whole this P-TFT zone covers fully;
As the cover curtain, this polysilicon island thing is carried out N-ion implantation step with the gate metal cover of the gate metal of this N-TFT and this P-TFT, form the N-zone of this N-TFT;
Form a photoresistance pattern on the gate metal cover of the gate metal of this N-TFT and this P-TFT, wherein the some of this photoresistance pattern defines the gate metal of this P-TFT, and another of this photoresistance pattern partly covers the gate metal that covers this N-TFT and the part gate insulator laminar surface of adjacency, to define the LDD structure of this N-TFT;
This polysilicon island thing is carried out the N+ ion implants, form the S/D zone of this N-TFT,
This gate metal cover that etching is not covered in by this photoresistance pattern partly forms the gate metal of this P-TFT;
, this polysilicon island thing is carried out the P+ ion implant as the cover curtain with the gate metal of this photoresistance pattern and this P-TFT, form the S/D zone of this P-TFT;
Divest this photoresistance pattern; And
Form the S/D metal electrode of this N-TFT and this P-TFT.
2. manufacture method as claimed in claim 1 is characterized in that: employed N+ dosage and P+ dosage are earlier through suitably allotment, so that the N+ zone that makes this N-TFT still keeps N+ doping type and low resistance characteristic behind this P+ ion implantation step.
3. manufacture method as claimed in claim 1, it is characterized in that: when forming this photoresistance pattern in the gate metal of this N-TFT and the step on this gate metal cover, make the gate metal of the position of this photoresistance pattern on the gate metal that is formed on this N-TFT and this N-TFT symmetrical, so that form the S/D zone of the N-TFT of symmetric form.
4. manufacture method as claimed in claim 1, it is characterized in that: when forming this photoresistance pattern in the gate metal of this N-TFT and the step on this gate metal cover, make the position of this photoresistance pattern on the gate metal that is formed on this N-TFT be asymmetric with the gate metal of this N-TFT, so that form the S/D zone of the N-TFT of asymmetrical type.
5. manufacture method as claimed in claim 1 is characterized in that: after the S/D metal electrode that forms this N-TFT and this P-TFT, other comprises formation ITO connection electrode step.
6. manufacture method as claimed in claim 1 is characterized in that: a resilient coating is formed between this polysilicon island thing and this insulated substrate.
7. the CMOS manufacture method of a low-temperature polysilicon film transistor is characterized in that: comprising:
On an insulated substrate, form the polysilicon island thing of desiring as a N-TFT and a P-TFT;
On this insulated substrate, deposit a gate insulator and a gate metal layer in regular turn;
This gate metal layer of patterning, with the first grid metal cap of the gate metal that forms this P-TFT and this N-TFT, wherein this first grid metal cap part that will be positioned at this polysilicon island thing in whole this N-TFT zone covers fully;
As the cover curtain, this polysilicon island thing is carried out P+ ion implantation step with the gate metal of this P-TFT and this first grid metal cap, form the S/D zone of this P-TFT;
Form a photoresistance pattern on the gate metal cover of the gate metal of this P-TFT and this N-TFT, wherein this photoresistance pattern covers whole this P-TFT gate metal and LDD structural region regional and this N-TFT;
This first grid metal cap that etching is not covered in by this photoresistance pattern partly forms the second grid metal cap of this N-TFT;
This polysilicon island thing is carried out the N+ ion implant, form the S/D zone of this N-TFT;
As cover curtain, the sidewall of this second grid metal cap is carried out etching program with this photoresistance pattern, make this sidewall of this second grid metal cap produce retraction, and form the gate metal of this N-TFT, define the LDD structural region of this N-TFT simultaneously;
Divest this photoresistance pattern;
, this polysilicon island thing is carried out the N-ion implant as the cover curtain with the gate metal of this N-TFT, form the LDD structure of this N-TFT; And
Form the S/D metal electrode of this N-TFT and this P-TFT.
8. manufacture method as claimed in claim 7 is characterized in that: use dry etching technology, the sidewall of this second grid metal cap is carried out etching program.
9. manufacture method as claimed in claim 7 is characterized in that: use wet etch techniques, the sidewall of this second grid metal cap is carried out etching program.
10. manufacture method as claimed in claim 7 is characterized in that: after the S/D metal electrode that forms this N-TFT and this P-TFT, other comprises formation ITO connection electrode step.
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