CN1585088A - Producing method for thin-film transistor array baseplate - Google Patents
Producing method for thin-film transistor array baseplate Download PDFInfo
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- CN1585088A CN1585088A CN 03154641 CN03154641A CN1585088A CN 1585088 A CN1585088 A CN 1585088A CN 03154641 CN03154641 CN 03154641 CN 03154641 A CN03154641 A CN 03154641A CN 1585088 A CN1585088 A CN 1585088A
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Abstract
A method for manufacturing TFT array substrate is carried out by: forming a grid and a scanning wire connected with the grid, forming a grid isolative layer, forming a channel layer on the isolative layer, forming a transparent layer and a metal layer above the substrate to be patterned to define source/drain and data wires and picture elements zones, forming a protective layer with metal layer of the picture element zone opened, finally, eliminating the latter metal layer with the latter protective layer as mask to form element electrodes. It reduces cost due to four optical masks needed only.
Description
Technical field
The invention relates to the manufacture method of a kind of thin film transistor (TFT) array (Thin Film Transistor Array) substrate, and particularly relevant for a kind of manufacture method that can reduce the thin-film transistor array base-plate of photomask number.
Background technology
Thin Film Transistor-LCD mainly is made of thin-film transistor array base-plate, colorful filter array substrate and liquid crystal layer, and wherein thin-film transistor array base-plate is by a plurality of thin-film transistor and pixel electrodes (PixelElectrode) of corresponding configuration with each thin-film transistor and constitute several dot structures with arrayed.And above-mentioned thin-film transistor is to comprise grid, channel layer, drain electrode and source electrode, and it is intended for the switch element of liquid crystal display.
In the known thin-film transistor manufacturing process, five road photomask manufacturing process more commonly.Wherein, the first road photomask manufacturing process is to be used for defining the first metal layer, to form the members such as grid of scan wiring and thin-film transistor.The second road photomask manufacturing process is that the channel layer and ohmic contact layer the 3rd road photomask manufacturing process that define thin-film transistor are to be used for defining second metal level, to form the members such as source/drain of data wiring and thin-film transistor.The 4th road photomask manufacturing process is to be used for the protective layer patterning.And the 5th road photomask manufacturing process is to be used for the transparency conducting layer patterning, and forms pixel electrode.
Yet, along with the development trend of Thin Film Transistor-LCD, and will face many problems and challenge towards the large scale making, for example yield reduces and production capacity descends or the like.If therefore can reduce the photomask number of thin-film transistor manufacturing process, promptly reduce the exposure engineering number of times that thin-film transistor element is made, just can reduce manufacturing time, increase production capacity, and then reduce manufacturing cost.
At United States Patent (USP) the 5th, 407, disclose the thin-film transistor manufacturing process that a kind of four road photomasks are arranged in No. 845 patents, wherein, the first road photomask manufacturing process is to be used for defining the first metal layer, to form the members such as grid of scan wiring and thin-film transistor.The second road photomask manufacturing process is to be used for defining active layers (channel layer) and to be formed on path protection layer on the active layers; utilize non-grade to remove the segment thickness of path protection layer sidewall to the etching manufacturing process afterwards; and then utilize this path protection layer as implanting mask, so that the side edge dopant ion of active layers.The 3rd road photomask manufacturing process is to be used for patterning second metal level and indium tin oxide layer, to define members such as data wiring, source/drain and pixel electrode.The 4th road photomask is to be used for the patterning protective layer, and is follow-up, utilizes protective layer for mask just removes with second metal level with pixel electrode again, exposes the indium tin oxide layer at pixel electrode place.
Summary of the invention
Therefore, purpose of the present invention just provides a kind of manufacture method of thin-film transistor array base-plate, uses number with the photomask that reduces the thin-film transistor manufacturing process, and then reduces cost of manufacture.
Another object of the present invention just provides a kind of manufacture method of thin-film transistor array base-plate, so that a kind of thin-film transistor manufacturing process that is different from known four road photomasks to be provided.
The present invention proposes a kind of manufacture method of thin-film transistor array base-plate, the method is scan wiring and the bridging line parallel with scan wiring that at first forms grid on substrate, electrically connect with grid, and the edge at substrate forms the first terminal portion simultaneously, wherein the scan wiring end is to electrically connect with the first terminal portion, and bridging line is intended for the bottom electrode of pixel storage capacitor device.Then, on substrate, form a gate insulator, cover gate, scan wiring, bridging line and the first terminal portion.Afterwards, on the gate insulator above the grid, form a channel layer and an ohmic contact layer.Then, above substrate, form a transparency conducting layer, and on transparency conducting layer, form a metal level.Subsequently, patterned metal layer and transparency conducting layer, to define source/drain, data wiring, pixel region and second portion of terminal, wherein data wiring is to electrically connect with source electrode, and its end electrically connects with second portion of terminal again, and grid, channel layer and source/drain are to constitute a thin-film transistor.Afterwards, above substrate, form a protective layer, expose the gate insulator of the pixel region and second portion of terminal and the first terminal portion top.Then; with the protective layer is mask; remove the metal level of the pixel region and second portion of terminal and the gate insulator of the first terminal portion top; expose the transparency conducting layer and the first terminal portion of the pixel region and second portion of terminal, and the transparency conducting layer that is exposed in the pixel region is pixel electrode.In addition, the pixel electrode that is formed at bridging line top is promptly as the conductive electrode of pixel storage capacitor device.
In the manufacture method of above-mentioned thin-film transistor array base-plate; on the surface of grid, scan wiring, bridging line and the first terminal portion, can optionally form a transparency conducting layer, its objective is that the surface that is used for protecting the first terminal portion can not be subjected to the damage of subsequent etch manufacturing process.If select not form this transparency conducting layer, then grid, scan wiring, bridging line and the first terminal portion need use not etched metal material.
The present invention proposes a kind of manufacture method of thin-film transistor array base-plate again, the method is scan wiring and the bridging line parallel with scan wiring that at first forms grid on substrate, electrically connect with grid, and the edge at substrate forms the first terminal portion simultaneously, wherein the scan wiring end is to electrically connect with the first terminal portion, and bridging line is intended for the bottom electrode of pixel storage capacitor device.Then, on substrate, form a gate insulator, cover gate, scan wiring, bridging line and the first terminal portion.Afterwards, on gate insulator, form a passage material layers and an ohmic contact layer, and form a photoresist layer on ohmic contact layer, wherein this photoresist layer is to expose the first terminal portion, and this photoresist layer is thick than the thickness of other parts corresponding to the thickness that is formed with the grid part on the substrate.Subsequently, be mask with this photoresist layer, remove ohmic contact layer, passage material layers and gate insulator in the first terminal portion, expose the first terminal portion.Then, remove the segment thickness of photoresist layer, and form first photoresist layer, wherein first photoresist layer is the passage material layers and the ohmic contact layer of cover grid top.Afterwards, be mask with first photoresist layer again, patterning ohmic contact layer and passage material layers, and on the gate insulator of grid top, define the ohmic contact layer of a channel layer and patterning.Then, above substrate, form a transparency conducting layer, and on transparency conducting layer, form a metal level.Afterwards, patterned metal layer and transparency conducting layer, to define source/drain, data wiring, second portion of terminal and pixel region, and in the first terminal portion that exposes, define conducting block simultaneously, wherein data wiring is to electrically connect with source electrode, and its end electrically connects with second portion of terminal again.Particularly, the conducting block in the first terminal portion of scan wiring end is to electrically connect with data wiring.Then, above substrate, form a protective layer, expose the metal level of the pixel region and second portion of terminal and the conducting block in the first terminal portion.Then; with the protective layer is mask; remove the metal level of the pixel region and second portion of terminal and the metal level of conducting block; expose the transparency conducting layer of the pixel region and second portion of terminal and the transparency conducting layer of conducting block; and the transparency conducting layer that is exposed in the pixel region is pixel electrode, and the transparency conducting layer of conducting block is to electrically connect with data wiring in the first terminal portion.In addition, the pixel electrode that is formed at bridging line top is promptly as the top electrode of pixel storage capacitor device.
Same; in the manufacture method of above-mentioned thin-film transistor array base-plate; on the surface of grid, scan wiring, bridging line and the first terminal portion, can optionally form the layer of transparent conductive layer, its objective is that the surface that is used for protecting the first terminal portion can not be subjected to the damage of subsequent etch manufacturing process.If select not form this transparency conducting layer, then grid, scan wiring, bridging line and the first terminal portion need use not etched metal material.
The manufacture method of thin-film transistor array base-plate proposed by the invention only need be used four road photomasks, therefore can reduce the required photomask number of thin-film transistor manufacturing process, and then reduces cost of manufacture.
In the manufacture method of the thin-film transistor array base-plate of four road photomasks proposed by the invention, its second photomask manufacturing process is to be used for define channel layer and ohmic contact layer, even the second photomask manufacturing process also simultaneously can make the first terminal portion come out in another embodiment.And the second photomask manufacturing process of the thin-film transistor manufacturing process of known four road photomasks is to be used for defining active layers (channel layer) and path protection layer, and therefore four road photomask manufacturing process of the present invention are a kind of methods that are different from known technology.
In addition; the manufacture method of thin-film transistor array base-plate proposed by the invention; except only needing the four road photomask manufacturing process; and its second road photomask manufacturing process and known technology part inequality; method of the present invention can also make the relation that electric connection is arranged between scan wiring and the data wiring; so, will help the ESD protection circuit or the convenience of other circuit design.
Description of drawings
Fig. 1 is the schematic top plan view according to the thin-film transistor array base-plate of a preferred embodiment of the present invention;
Fig. 2 A to Fig. 2 E is the manufacturing process generalized section according to the thin-film transistor array base-plate of a preferred embodiment of the present invention; And
Fig. 3 A to Fig. 3 I is the manufacturing process generalized section according to the thin-film transistor array base-plate of another preferred embodiment of the present invention.
Graphic sign explanation
200: substrate
201,215: transparency conducting layer
202: scan wiring
204: data wiring
205: gate insulator
206: grid
208: channel layer
209,269: ohmic contact layer
210a/210b: source/drain
210c, 210d: metal level
211: protective layer
212a, 2126: portion of terminal
214: bridging line
216: pixel electrode
216a: contact layer
219: conducting block
230: thin-film transistor
250: the pixel storage capacitor device
260: pixel region
268: the passage material layers
300: photomask
302: exposure region
304: half exposure regions
306: the non-exposed area
310,310a, 310b: photoresist layer
For above-mentioned and other purposes of the present invention, feature and advantage can be become apparent, a preferred embodiment cited below particularly, and cooperate appended graphic being described in detail below:
Embodiment
First embodiment
Shown in Figure 1, for the schematic top plan view according to a kind of thin-film transistor array base-plate of a preferred embodiment of the present invention is shown; Shown in Fig. 2 A to Fig. 2 E, be manufacturing process generalized section according to a kind of thin-film transistor array base-plate of a preferred embodiment of the present invention, among Fig. 1 by the generalized section of I-I.
Please at first provide substrate 200 simultaneously with reference to Fig. 1 and Fig. 2 A, wherein substrate 200 for example is glass substrate or plastic substrate.Afterwards, on substrate 200, form a first metal layer (M1) (not shown), and carry out the first road photomask manufacturing process, with the scan wiring 202 that defines grid 206, electrically connect with grid 206, the bridging line 214 parallel and the 212a of the first terminal portion that is formed on substrate 200 1 edges with scan wiring 202.Wherein, the 212a of the first terminal portion electrically connects with scan wiring 202, and it is follow-up to be to be used for electrically connecting with drive circuit, and bridging line 214 is intended for the bottom electrode of pixel storage capacitor device 250 subsequently.In a preferred embodiment, the material of the first metal layer for example is chromium (Cr), tungsten (W), tantalum (Ta), titanium (Ti), molybdenum (Mo), aluminium (Al) or alloy.
What is particularly worth mentioning is that, at this, can optionally additionally form layer of transparent conductive layer 201 on the surface of grid 206, scan wiring 202, bridging line 214 and the 212a of the first terminal portion, the material of transparency conducting layer 201 for example is tin indium oxide (ITO) or indium zinc oxide (IZO).In other words, can on substrate 200, deposit after the first metal layer earlier, on first metal, deposit layer of transparent conductive layer (not shown) again, then, again together with transparency conducting layer and the first metal layer patterning, and define grid 206, scan wiring 202, bridging line 214 and the 212a of the first terminal portion, and the transparency conducting layer 201 that is formed on grid 206, scan wiring 202, bridging line 214 and the first terminal portion 212a surface.If select not form this transparency conducting layer 201, then the first metal layer need use not etched metal material.
Then, please refer to Fig. 2 B, on substrate 200, form gate insulator 205, cover the first metal layer (comprising grid 206, scan wiring 202, bridging line 214 and the 212a of the first terminal portion).In a preferred embodiment, the material of gate insulator 205 for example is silicon nitride, oxidation silicon or nitrogen oxidation silicon.
Subsequently, above substrate 200, form one deck passage material layers (not shown) and one deck ohmic contact layer (not shown), and carry out the second road photomask manufacturing process, on the gate insulator above the grid 206 205, to define channel layer 208 and ohmic contact layer 209.In a preferred embodiment, the material of channel layer 208 for example is an amorphous silicon, and the material of ohmic contact layer 209 for example is the amorphous silicon through mixing.
Afterwards, please refer to Fig. 2 C, above substrate 200, deposit in regular turn after layer of transparent conductive layer (not shown) and second metal level (M2) (not shown), carry out the 3rd road photomask manufacturing process, with patterning second metal level and transparency conducting layer, and define data wiring 204, source/drain 210a/210b.
The pixel region 260 and the second portion of terminal 212b, wherein data wiring 204 is to electrically connect with source electrode 210a, and its end electrically connects with the second portion of terminal 212b again, and the second portion of terminal 212b follow-up be to be used for electrically connecting with drive circuit, at this, the data wiring 204 that is defined, source/drain 210a/210b and the second portion of terminal 212b are for having the two-layer structure of metal level (upper strata) and transparency conducting layer 215 (lower floor).In addition, the pixel region 260 that is defined also is a double-layer structure, and it comprises lower floor's transparency conducting layer 215 and upper metal layers 210C.In a preferred embodiment, the material of second metal level for example is chromium (Cr), tungsten (W), tantalum (Ta), titanium (Ti), molybdenum (Mo), aluminium (Al) or alloy, and the material of transparency conducting layer 215 for example is tin indium oxide (ITO) or indium zinc oxide (IZO).
Then, remove the ohmic contact layer 209 that is exposed by second metal level, and channel layer 208 is come out.
Subsequently; please refer to Fig. 1, Fig. 2 D and Fig. 2 E; above substrate 200, form a protective layer (not shown); and carry out the 4th road photomask manufacturing process; to form patterned protective layer 211, wherein protective layer 211 is the gate insulator 212a that expose pixel region 260, the second portion of terminal 212b and the 212a of the first terminal portion top.At this, the material of protective layer 211 for example is oxidation silicon, silicon nitride, nitrogen oxidation silicon or organic material.
Afterwards; with protective layer 211 is etching mask; remove the not metal level of protected seam 211 coverings; it comprises metal level 210c in the pixel region 260 and the metal level of the second portion of terminal 212b; and remove the gate insulator 205 of the first terminal portion 212 tops; and expose transparent transparency conducting layer 215 and the first terminal portion 212 (or transparency conducting layer in the first terminal portion 212 201) that waits electricity layer 215, the second portion of terminal 212b in the pixel region 260, wherein the transparency conducting layer 215 that is exposed out in the pixel region 260 is pixel electrode 216.So, promptly finish the making of a thin-film transistor array base-plate.
In addition, previous formed bridging line 214 is the bottom electrodes as pixel storage capacitor device 250, therefore the pixel electrode 216 that is formed on bridging line 214 tops is promptly as the top electrode of pixel storage capacitor device 250, and is formed at gate insulator 205 between bridging line 214 and the pixel electrode 216 promptly as capacitance dielectric layer.
In the manufacture method of above-mentioned thin-film transistor array base-plate, only need use four road photomask manufacturing process, wherein first photomask is to be used for defining the first metal layer, to form grid, scan wiring, bridging line and the first terminal portion.The second road photomask manufacturing process is define channel layer and ohmic contact layer.The 3rd road photomask manufacturing process is used for defining second metal level and transparency conducting layer, to define data wiring, source/drain, pixel region and second portion of terminal.And the 4th road photomask is to be used for the patterning protective layer.Follow-up, directly use protective layer just second metal level in the pixel region can be removed as mask, expose transparency conducting layer, and form pixel electrode, and the gate insulator in the first terminal portion is removed, so that the first terminal portion comes out.
Second embodiment
Shown in Fig. 3 A to Fig. 3 N, be manufacturing process generalized section according to a kind of thin-film transistor array base-plate of another preferred embodiment of the present invention, its be among Fig. 1 by the generalized section of I-I '.
Please be simultaneously with reference to Fig. 1 and Fig. 3 A, at first on substrate 200, form the first metal layer (M1) (not shown), and carry out the first road photomask manufacturing process, with the scan wiring 202 that defines grid 206, electrically connect with grid 206, the bridging line 214 parallel and the 212a of the first terminal portion that is formed on substrate 200 2 edges with scan wiring 202.Wherein, the 212a of the first terminal portion electrically connects with scan wiring 202, it is follow-up to be to be used for electrically connecting with drive circuit, the bridging line 214 follow-up bottom electrodes that are intended for pixel storage capacitor device 250, in a preferred embodiment, the material of the first metal layer for example is chromium (Cr), tungsten (W), tantalum (Ta), titanium (Ti), molybdenum (Mo), aluminium (Al) or alloy.
Same, in this embodiment, can optionally additionally form layer of transparent conductive layer 201 on the surface of grid 206, scan wiring 202, bridging line 214 and the 212a of the first terminal portion, the material of transparency conducting layer 201 for example is tin indium oxide (ITO) or indium zinc oxide (IZO).In other words, can on substrate 200, deposit after the first metal layer earlier, on the first metal layer, deposit layer of transparent conductive layer (not shown) again, then, again together with transparency conducting layer and the first metal layer patterning, and define grid 206, scan wiring 202, bridging line 214 and the 212a of the first terminal portion, and the transparency conducting layer 201 that is formed on grid 206, scan wiring 202, bridging line 214 and the first terminal portion 212a surface.If select not form this transparency conducting layer 201, then first metal needs is used not etched metal material.
Then, please refer to Fig. 3 B, on substrate 200, form gate insulator 205, cover the first metal layer (comprising grid 206, scan wiring 202, bridging line 214 and the 212a of the first terminal portion).In a preferred embodiment, the material of gate insulator 205 for example is after silicon nitride, oxidation silicon or the nitrogen oxidation silicon, forms one deck passage material layers 268 and one deck ohmic contact layer 269 on gate insulator 205.
Afterwards, carry out the second road photomask manufacturing process, this second road photomask manufacturing process comprises formation one photoresist layer 310 on ohmic contact layer 269 earlier, and a photomask 300 is set above photoresist layer 310.Wherein, photomask 300 has an exposure region 302, half exposure region 304 and a non-exposed area 306, exposure region 302 is corresponding to being formed with the 212a of the first terminal portion part on the substrate 200, non-exposed area 306 is to be formed with grid 206 parts on the counterpart substrate 200, and half exposure region 304 then is other parts on the counterpart substrate 200.
Please refer to Fig. 3 C, carry out a little shadow manufacturing process, with patterning photoresist layer 310, and formation patterned light blockage layer 310a, wherein photoresist layer 310a is the ohmic contact layer 269 that exposes portion of terminal 212 tops, and it is thick than the photoresist layer 310a thickness of other parts to cover the thickness of photoresist layer 310a of grid 206 tops.
Please refer to Fig. 3 D, with photoresist layer 310a is that etching mask carries out an etching step, to remove ohmic contact layer 269, passage material layers 268 and the gate insulator 205 of the 212a of the first terminal portion top, expose the 212a of the first terminal portion (or the transparency conducting layer 201 on the 212a of the first terminal portion).
Please refer to Fig. 3 E, carry out a photoresistance cineration step, removing the segment thickness of photoresist layer 310a, and form photoresist layer 310b, formed photoresist layer 310b is the ohmic contact layer 269 of cover grid 206 tops.
Please refer to Fig. 3 F, is etching mask with photoresist layer 310b, carries out an etching step, with patterning ohmic contact layer 269 and passage material layers 268, and defines channel layer 208 and ohmic contact layer 209.
Please refer to Fig. 3 G, above substrate 200, deposit in regular turn after layer of transparent conductive layer (not shown) and second metal level (M2) (not shown), carry out the 3rd road photomask manufacturing process, with patterning second metal level and transparency conducting layer, and define data wiring 204, source electrode 210a, drain electrode 210b, pixel region 260 and the second portion of terminal 212b, and on the 212a of the first terminal portion that exposes, define conducting block 219 simultaneously.
Wherein, data wiring 204 is and source electrode 210a electrically connects, and its end electrically connects with second portion of terminal 212 again, and the second portion of terminal 212b is follow-up to be to be used for electrically connecting with drive circuit.At this, the data wiring 204 that is defined, source electrode 210a, drain electrode 210b and the second portion of terminal 212b are for having the two-layer structure of metal level (upper strata) and transparency conducting layer 215 (lower floor).And the pixel region 260 that is defined also is a double-layer structure, and it comprises lower floor's transparency conducting layer 215 and upper metal layers 210c.In addition, the conducting block 219 on the 212a of the first terminal portion also is to comprise lower floor's transparency conducting layer 215 and upper metal layers 210d, and the conducting block 219 on the 212a of the first terminal portion is to electrically connect with data wiring 204.In a preferred embodiment, the material of second metal level for example is chromium (Cr), tungsten (W), tantalum (Ta), titanium (Ti), molybdenum, (Mo), aluminium (Al) or alloy, and the material of transparency conducting layer 215 for example is tin indium oxide (ITO) or indium zinc oxide (IZO).
Then, remove the ohmic contact layer 209 that is exposed by second metal level, and channel layer 208 is come out.
Subsequently; please refer to Fig. 1, Fig. 3 H and Figure 31; above substrate 200, form a protective layer (not shown); and carry out the 4th road photomask manufacturing process; to form patterned protective layer 211, wherein protective layer 211 exposes pixel region 260, the second portion of terminal 212b and the 212a of the first terminal portion top conducting block 219.At this, the material of protective layer 211 for example is oxidation silicon, silicon nitride, nitrogen oxidation silicon or organic material.
Afterwards; with protective layer 211 is etching mask; remove the not metal level of protected seam 211 coverings; it comprises 210c in the pixel region 260 and the metal level of the second portion of terminal 212b; and remove the metal level 210d of the conducting block 219 on the 212a of the first terminal portion simultaneously; and expose transparency conducting layer 215 in the pixel region 260; the transparency conducting layer 215 of the second portion of terminal 212b and the first terminal be the transparency conducting layer 215 on the 212a all; wherein the transparency conducting layer 215 that is exposed out in the pixel region 260 is pixel electrode 216, and the transparency conducting layer 215 of the first terminal portion 212 tops is to be contact layer 216a.
Particularly, the contact layer 216a of the 212a of the first terminal portion top electrically connects with data wiring 204, thus, the relation of electric connection is arranged just between scan wiring 202 and the data wiring 204.Owing to before in the second road photomask manufacturing process, the 212a of the first terminal portion was come out, therefore follow-up in the 3rd road photomask manufacturing process when definition second metal level and transparency conducting layer, just can on the 212a of the first terminal portion that exposes, define conducting block 219 (comprising metal level 210d and transparency conducting layer 215), and the relation of electric connection is arranged between conducting block 219 on the 212a of the first terminal portion of scan wiring 202 ends and the data wiring 204.Therefore, follow-up after the metal level 210d with conducting block 219 removes, still can make scan wiring 202 and data wiring 204 that the relation of electric connection is arranged by contact layer 216a (promptly being formed on the transparency conducting layer 215 on the 212a of the first terminal portion).And the relation of electric connection is arranged between scan wiring 202 (the first metal layer) and the data wiring 204 (second metal level), will help the convenience of ESD protection circuit and other circuit design.
For example as therein in a kind of design of ESD protection circuit; protective circuit is made of two thin-film transistors; and its grid separately is electrically to communicate each other with source electrode; and two reverse diodes have been formed; therefore if will use the design of this kind ESD protection circuit, then must make the first metal layer and second metal level that the relation of electric connection is arranged.
In addition, previous formed bridging line 214 is the bottom electrodes as pixel storage capacitor device 250, therefore the pixel electrode 216 that is formed on bridging line 214 tops is the top electrodes as pixel storage capacitor device 250, and the gate insulator 205 that is formed between bridging line 214 and the pixel electrode 216 is capacitance dielectric layer.
In the manufacture method of above-mentioned thin-film transistor array base-plate, only need use four road photomask manufacturing process, wherein first photomask is to be used for defining the first metal layer, to form grid, scan wiring, bridging line and the first terminal portion.The second road photomask manufacturing process is to be used for define channel layer and ohmic contact layer, and the first terminal portion is come out.The 3rd road photomask manufacturing process is to be used for defining second metal level and transparency conducting layer, to define data wiring, source/drain, pixel region, second portion of terminal and conducting block.And the 4th road photomask is to be used for the patterning protective layer; follow-up; directly use protective layer to admire just and second metal level in the pixel region can be removed as cover; expose transparency conducting layer; and the formation pixel electrode; and the metal level of the conducting block in the first terminal portion is removed, so that transparency conducting layer comes out.
Because the manufacture method of Fu's film transistor array base palte of the present invention only need be used four road photomasks, therefore can reduce the required photomask number of thin-film transistor manufacturing process, and then reduce cost of manufacture.
In the manufacture method of the thin-film transistor array base-plate of four road photomasks proposed by the invention; its second photomask manufacturing process is to be used for define channel layer and ohmic contact layer; even the second photomask manufacturing process also simultaneously can make the first terminal portion come out in another embodiment; and the second photomask manufacturing process of the thin-film transistor manufacturing process of known four road photomasks is to be used for defining active layers (channel layer) and path protection layer, and therefore four road photomask manufacturing process of the present invention are a kind of methods that are different from known technology.
In addition; the manufacture method of thin-film transistor array base-plate proposed by the invention; except only needing the four road photomask manufacturing process; and outside its second road photomask manufacturing process and known technology are inequality; method of the present invention can also make the relation that electric connection is arranged between scan wiring and the data wiring; so, will help the ESD protection circuit or the convenience of other circuit design.
Though the present invention discloses as above with preferred embodiment; right its is not in order to limit the present invention; anyly have the knack of this skill person; without departing from the spirit and scope of the present invention; when can doing a little change and retouching, so protection scope of the present invention is as the criterion when looking accompanying the claim person of defining.
Claims (14)
1, a kind of manufacture method of thin-film transistor array base-plate comprises:
The one scan distribution that on a substrate, forms a grid and electrically connect with this grid;
On this substrate, form a gate insulator, cover this grid and this scan wiring;
On this gate insulator above this grid, define a channel layer and an ohmic contact layer;
Above this substrate, form a transparency conducting layer;
On this transparency conducting layer, form a metal level;
This metal level of patterning and this transparency conducting layer are to define source, a data wiring and a pixel region;
Above this substrate, form a protective layer, expose this metal level in this pixel region; And
With this protective layer is mask, removes this metal level in this pixel region, exposes this transparency conducting layer in this pixel region, and forms a pixel electrode.
2, the manufacture method of thin-film transistor array base-plate as claimed in claim 1 wherein more comprises being formed with one first transparency conducting layer on the surface of this grid and this scan wiring.
3, the manufacture method of thin-film transistor array base-plate as claimed in claim 1, wherein when forming this grid and this scan wiring, an edge that more is included in this substrate forms a first terminal portion that electrically connects with this scan wiring, in definition this source/drain, this data wiring and this pixel region, more define one second portion of terminal in another edge of this substrate.
4, the manufacture method of thin-film transistor array base-plate as claimed in claim 3 wherein more comprises being formed with one first transparency conducting layer on the surface of this first terminal portion.
5, the manufacture method of thin-film transistor array base-plate as claimed in claim 3; wherein above this substrate, form in the step of this protective layer; this protective layer is this gate insulator and this second portion of terminal that exposes this first terminal portion top; so that it is follow-up in being that mask removes in the step of this metal level with this protective layer; this gate insulator of this first terminal portion top can be removed, this metal level of this second portion of terminal also can be removed.
6, the manufacture method of thin-film transistor array base-plate as claimed in claim 1, wherein when forming this grid and this scan wiring, more be included in and form a bridging line on this substrate, in order to making the bottom electrode of a pixel storage capacitor device, and follow-up this pixel electrode that is formed at this bridging line top is promptly as the top electrode of this pixel storage capacitor device.
7, the manufacture method of thin-film transistor array base-plate as claimed in claim 6 wherein more comprises being formed with one first transparency conducting layer on the surface of this bridging line.
8, a kind of manufacture method of thin-film transistor array base-plate comprises:
The one scan distribution that on a substrate, forms a grid and electrically connect with this grid, and form a first terminal portion in an edge of this substrate simultaneously, this scan wiring is and this first terminal portion electrically connects;
On this substrate, form a gate insulator, cover this grid, this scan wiring and this first terminal portion;
On this gate insulator, form a passage material layers;
Form a photoresist layer on this passage material layers, this photoresist layer exposes this passage material layers of this first terminal portion top, and this photoresist layer is thick than the thickness of other parts corresponding to the thickness of this grid part;
With this photoresist layer is mask, removes this passage material layers and this gate insulator in this first terminal portion, exposes this first terminal portion;
Remove the segment thickness of this photoresist layer, and form one first photoresist layer, this first photoresist layer covers this passage material layers of this grid top;
With this first photoresist layer is mask, this passage material layers of patterning, and on this gate insulator of this grid top, define a channel layer;
Above this substrate, form a transparency conducting layer;
On this transparency conducting layer, form a metal level;
This metal level of patterning and this transparency conducting layer, to define source, a data wiring, a pixel region and one second portion of terminal, and in this first terminal portion that exposes, define a conducting block simultaneously, wherein this data wiring is to electrically connect with this source electrode, and this conducting block in this first terminal portion is to electrically connect with this data wiring;
Above this substrate, form a protective layer, expose this pixel region, this second portion of terminal and this conducting block; And
With this protective layer is mask; remove this metal level of this pixel region, this second portion of terminal and this conducting block; expose this transparency conducting layer of this pixel region, this second portion of terminal and this conducting block, this transparency conducting layer that exposes in this pixel region is a pixel electrode.
9, the manufacture method of thin-film transistor array base-plate as claimed in claim 8 wherein more comprises being formed with one first transparency conducting layer on the surface of this grid, this scan wiring and those portion of terminal.
10, the manufacture method of thin-film transistor array base-plate as claimed in claim 8, wherein when forming this grid, this scan wiring and this first terminal portion, more be included in and form a bridging line on this substrate, in order to making the bottom electrode of a pixel storage capacitor device, and follow-up this pixel electrode that is formed at this bridging line top is promptly as the top electrode of this pixel storage capacitor device.
11,, wherein on the surface of this bridging line, more comprise being formed with one first transparency conducting layer as the manufacture method of claim 10 a described thin-film transistor array base-plate.
12, the manufacture method of thin-film transistor array base-plate as claimed in claim 8 wherein more comprises being formed with an ohmic contact layer on the surface of this channel layer.
13, the manufacture method of thin-film transistor array base-plate as claimed in claim 8, the method that wherein forms this photoresist layer is to utilize a photomask with an exposure region, half exposure region and a non-exposed area, this exposure region is corresponding to being formed with this first terminal portion part on this substrate, and this non-exposed area is corresponding to being formed with this grid part on this substrate.
14, the manufacture method of thin-film transistor array base-plate as claimed in claim 8, the method that wherein removes the segment thickness of this photoresist layer comprise utilizes a cineration step.
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| CNB031546412A CN1333432C (en) | 2003-08-21 | 2003-08-21 | Producing method for thin-film transistor array baseplate |
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| CNB031546412A CN1333432C (en) | 2003-08-21 | 2003-08-21 | Producing method for thin-film transistor array baseplate |
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| CN1333432C CN1333432C (en) | 2007-08-22 |
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