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CN1466063A - Parallel network server - Google Patents

Parallel network server Download PDF

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Publication number
CN1466063A
CN1466063A CNA021240035A CN02124003A CN1466063A CN 1466063 A CN1466063 A CN 1466063A CN A021240035 A CNA021240035 A CN A021240035A CN 02124003 A CN02124003 A CN 02124003A CN 1466063 A CN1466063 A CN 1466063A
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CN
China
Prior art keywords
controller
array
channel
network server
bus
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Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
CNA021240035A
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Chinese (zh)
Inventor
朱兴方
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Individual
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Individual
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Publication date
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Priority to CNA021240035A priority Critical patent/CN1466063A/en
Publication of CN1466063A publication Critical patent/CN1466063A/en
Pending legal-status Critical Current

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Abstract

The invention is a new net server system structure actually. The serveral processing units and several memorizing units in the structure work in parallel under the coordination of the system controller. The system server is made up of system controller, ID processing module IOPM, three independent channels controllers; controllers of channel A, B, C, processing array, RAM disc array, hard disk array and the communication or control lines of each unit. The processing array accomplishes the application service of IOPM under control of the channel A controller and the coordination of the system controller; the RAM disc array accomplishes the application service of IOPM under control of the channel B controller and the coordination of the system controller.

Description

Parallel network server
Technical field
The present invention relates to a kind of new concurrent computational system, furtherly, the present invention relates to a kind of computer system of utilizing concurrent technique and the parallel memory technology of the consistent storage network of non-characteristic.
Background technology
All modern computers all are based on Feng's Neumann formula (VonNeumann) architecture.Feng's Neumann formula model comprises 5 main system components (1) input block, (2) output unit, (3) ALU (ALU), (4) storer and (5) control module.Computer system based on this architecture can't be directly by access to netwoks owing to storer, and in a large amount of concurrent accesss to netwoks, time delay is oversize, is not suitable for doing the webserver.
Summary of the invention
Fig. 1 shows server of the present invention by system controller (1), IO processing module IOPM (2), three channel controllers independently: passage A controller (3) channel B controller (4) channel C controller (5), handle array (6), ram disc array (7), the communication of hard disk array (8) and each unit or control line are formed.System controller (1) is by link to each other with IO processing module (12), passage A controller (3) channel B controller (4) channel C controller (5) operation of control system of control bus (12).Between IO processing module IOPM (2) and passage A controller (3) channel B controller (4) the channel C controller (5) bidirectional bus (9) (10) (11) is arranged respectively.There is bidirectional bus (16) (17) (18) to link to each other between passage A controller (3) channel B controller (4) the channel C controller (5) respectively, realizes the direct exchange of 3 interchannel data.Passage A controller (3) links to each other with processor array (6) by bus (13), the operation of processor controls array (6) and and processor array (6) swap data and signal.Channel B controller (4) links to each other with ram disc array (7) by bus (14), control ram disc array (7) operation and and ram disc array (7) swap data and signal.Channel C controller (5) links to each other with hard disk array (8) by bus (15), control hard disk array (8) operation and and hard disk array (8) swap data and signal.IO processing module IOPM (2) link to each other with other equipment on the network by a plurality of universal serial bus (19) and with other network equipment swap datas, handle the data that request that other equipment send or other equipment of strong point are sent.
Description of drawings
Fig. 1 parallel network server system assumption diagram
Fig. 2 system controller figure
Fig. 3 handles array of figure
Fig. 4 ram disc array of figure
Fig. 5 hard disk array figure
Fig. 2 shows the structure of controller, it is by 2 CPU (1) (2), 2 memory RAM (6) (7), 2 controllers (6) (7) and bus (8) (10) (11) (12) (8) (5) are formed. and controller (3) (4) obtains the other side's duty by bus (8), and decision is to the control of bus (5), obtain control by controller (3) during system initialization to bus (5), controller (4) obtains the control to bus (5) when controller (3) fault, by the control of bus (5) and exchange message being finished coordination and the control to server system of the present invention.The control strategy and the control program of system is stored in (6) (7).Bus (5) is corresponding with (12) among Fig. 1.
Accompanying drawing 3 shows processing array technique, and it is by (1) (2) ... (N) a plurality of processors are formed.Processor (1) is made up of CPU (11) controller BC (12) random access memory ram (13) and bus (14) (15) (16), and other processors are identical with the composition of processor (1).Bus (13) (23) is corresponding with the bus (15) corresponding (13) among Fig. 1 with (K3).
Accompanying drawing 4 shows the ram disc array structure, and it is by (1) (2) ... (M) a plurality of processors are formed.Ram disc (1) is made up of controller BC (12) random access memory ram (11) and bus (13) (14), and other ram discs are identical with the composition of ram disc (1).Bus (13) (23) is corresponding with the bus (14) among Fig. 1 with (K3).
Accompanying drawing 5 shows the hard disk array structure, and it is by 1) (2) ... (M) a plurality of hard-disc storage subelements are formed.Hard-disc storage subelement (1) is by (11A) (11B) (11C) (11D) (11E) (11F) of a plurality of hard disks (111) (112) (113) (114) (115) (116) (117) (118) (119) that is connected on the bus (14), bus controller DBC (12) and bus (13) are formed, and other hard-disc storage subelements are identical with the composition of hard-disc storage subelement (1).Bus (13) (23) is corresponding with the bus (15) among Fig. 1 with (K3).

Claims (8)

1. parallel network server, comprise system controller (1), IO processing module IOPM (2), three channel controllers independently: passage A controller (3) channel B controller (4) channel C controller (5), handle array (6), ram disc array (7), the communication or the control line of hard disk array (8) and each unit.
2. in the parallel network server as claimed in claim 1, wherein, handle array (6) and under the coordination of the control of passage A controller (3) and system controller (1), finish from the request service of IO processing module IOPM;
3. in the parallel network server as claimed in claim 1, wherein, ram disc array (7) is finished the request service that comes from IO processing module IOPM under the coordination of the control of channel B controller (3) and system controller (1);
4. in the parallel network server as claimed in claim 1, wherein, hard disk array (8) is finished the request service that comes from IO processing module IOPM under the coordination of the control of channel C controller (3) and system controller (1);
5. in the parallel network server as claimed in claim 1, wherein, under the control of system controller (1), handle array (6), ram disc array (7), hard disk array (8), directly swap data and signal.
6. in the parallel network server as claimed in claim 1, wherein, handle array (6) and be by a plurality of and have a processor, storer and bus controller unit are formed and are handled array.
7. in the parallel network server as claimed in claim 1, wherein, ram disc array (7) is made up of a plurality of RAM of having and bus controller unit.
8. in the parallel network server as claimed in claim 1, wherein, hard disk array (8) is to have a SCSI bus by a plurality of, and 1 to 15 SCSI hard disk and bus controller are formed.
CNA021240035A 2002-06-14 2002-06-14 Parallel network server Pending CN1466063A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
CNA021240035A CN1466063A (en) 2002-06-14 2002-06-14 Parallel network server

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CNA021240035A CN1466063A (en) 2002-06-14 2002-06-14 Parallel network server

Publications (1)

Publication Number Publication Date
CN1466063A true CN1466063A (en) 2004-01-07

Family

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Family Applications (1)

Application Number Title Priority Date Filing Date
CNA021240035A Pending CN1466063A (en) 2002-06-14 2002-06-14 Parallel network server

Country Status (1)

Country Link
CN (1) CN1466063A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2008138249A1 (en) * 2007-05-10 2008-11-20 Memoright Memoritech (Shenzhen) Co., Ltd Parallel flash memory controller, chip and control method thereof

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2008138249A1 (en) * 2007-05-10 2008-11-20 Memoright Memoritech (Shenzhen) Co., Ltd Parallel flash memory controller, chip and control method thereof
US8661188B2 (en) 2007-05-10 2014-02-25 Memoright Memoritech (Wuhan) Co., Ltd. Parallel flash memory controller, chip and control method thereof

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