CN1327714C - Inputting channel of line-by-line/intelaced video frequency signal sharing and method thereof - Google Patents
Inputting channel of line-by-line/intelaced video frequency signal sharing and method thereof Download PDFInfo
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- CN1327714C CN1327714C CNB2004100151864A CN200410015186A CN1327714C CN 1327714 C CN1327714 C CN 1327714C CN B2004100151864 A CNB2004100151864 A CN B2004100151864A CN 200410015186 A CN200410015186 A CN 200410015186A CN 1327714 C CN1327714 C CN 1327714C
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Abstract
The present invention relates to an input channel and a method for line-by-line color difference component signals and interleaved color difference component signals (i.e. YPbPr/YCbCr) in a TV and discloses an input channel and a method for sharing line-by-line /interleaved video signals. The method comprises the following steps: the video signals are input to a TV receiver through YPbPr/YCbCr input terminals. Whether the input signals are in the form of the line-by-line video signals or the interleaved video signals or not is judged; according to a judged result, whether a YPbPr circuit or a YCbCr circuit is switched on or off are controlled, and the signals can pass through a corresponding input signal processing circuit. Finally, the signals are sent to a video processing circuit for further processing. Aiming at the different video input signals YPbPr or YPbPr, the present invention only needs one way of channel to realize the viewing of the component video signals through the automatic identification of the TV receiver. The present invention has the advantages of cost saving, compact circuit and convenient operation.
Description
[technical field]
The present invention relates on video equipment line by line input channel and method with interlaced video signal, relate in particular in HDTV (High-Definition Television) line by line with the input channel and the method thereof of interlacing color difference components signal (being YPbPr/YCbCr).
[background technology]
In the existing TV tech, watching line by line or during interlaced video signal (such as DVD or interlacing DVD line by line), the two-way input terminal is being arranged on television receiver usually: one tunnel input terminal YPbPr line by line, one tunnel interlacing input terminal YCbCr.The user needs to differentiate the form of input signal in use, selects different input terminals for use at different input signals.Receiver is handled when receiving different signals along separate routes.Common processing method is the input signal of progressive video signal YPbPr not to be done digital processing, through directly delivering to the electron gun that video amplifier circuit drives picture tube after the simple matrixing.Then earlier by certain digitized processing, by digital circuit output rgb signal, drive the electron gun of picture tube to obtain complete image by video amplifier circuit again for the input signal of interlaced video signal YCbCr then.Therefore have following problem in existing technology: 1) user will differentiate the input terminal of a receiver earlier when using television receiver to watch the DVD vision signal, brings certain trouble to the user.2) two of television receiver outside need designs receive terminals, inner need two of designs independently circuit handle different input signals respectively, increased the cost of television set.
[summary of the invention]
Purpose of the present invention is exactly to solve in the prior art to divide the two-way input and handle the defective of being brought with interlaced video signal line by line, input channel and method thereof that line by line a kind of/interlaced video signal is shared are proposed, line by line/and the shared YpbPr/YcbCr input terminal of interlaced video signal, handle through discerning automatically.
For achieving the above object, the present invention proposes the input channel that line by line a kind of/interlaced video signal is shared, comprise video processing unit, also comprise line by line/the shared YPbPr/YcbCr input terminal of interlaced video signal, the signal format judging unit that links to each other with the YPbPr/YCbCr input terminal, progressive signal processing unit that links to each other with the YPbPr/YCbCr input terminal and interlace signal processing unit respectively, described signal format judging unit connects progressive signal processing unit and interlace signal processing unit respectively, be used for input signal for progressive signal time control progressive signal processing unit open and the interlace signal processing unit is closed, input signal for interlace signal time control interlace signal processing unit open and the progressive signal processing unit is closed, the output of described progressive signal processing unit and interlace signal processing unit is connected video processing unit respectively.
Described signal format judging unit comprises the line synchronizing signal split circuit and is used to judge the CPU of signal format, the input of described line synchronizing signal split circuit links to each other with the YPbPr/YCbCr input terminal, output links to each other with CPU, and described CPU connects progressive signal processing unit and interlace signal processing unit respectively.
Described progressive signal processing unit is first video a/d converter, and described interlace signal processing unit is a video decoding chip.
Described CPU passes through I
2The C bus connects first video a/d converter and video decoding chip respectively.
Described line synchronizing signal split circuit is second A/D converter.
Especially, first video a/d converter and second A/D converter are integrated in the same chip.
For achieving the above object, the invention allows for the method for the shared input channel of line by line a kind of/interlaced video signal, may further comprise the steps:
1) vision signal is input to television receiver from the YPbPr/YcbCr input terminal;
2) form of judgement input signal is progressive video signal or interlaced video signal;
3) path according to judged result control YPbPr or YCbCr opens or closes, and makes signal pass through the respective input signals treatment circuit, at last signal is sent into video processing circuits and is done further processing.
Step 2) described judgement may further comprise the steps:
2-1) video a/d converter is separated the line synchronizing signal in the input signal;
2-2) line synchronizing signal is input among the CPU, CPU judges the form of input signal according to line frequency.
When judging in the step 3) that input signal is progressive video signal, may further comprise the steps: the CPU output order is turned off the decoding chip of YCbCr, sends into video processing circuits after signal is handled by video a/d converter to be for further processing; When judging in the step 3) that input signal is interlaced video signal, may further comprise the steps: the CPU output order is turned off video a/d converter, sends into video processing circuits after making signal by decoding chip to be for further processing.
At different video input signals YPbPr or YCbCr, television receiver can be discerned automatically among the present invention.Compare with existing technology, the present invention has following effect: 1) save cost, circuit is easier.From the outside, save one group of video component input terminal; Circuit internally only need do a paths and can realize the watching of component video signal, and existing technology often needs the two independent circuit.2) easy to use.From user perspective, the present invention has reduced user's wrong terminal and has caused the possibility that can not watch, brings bigger convenience to the user.
Feature of the present invention and advantage will be elaborated in conjunction with the accompanying drawings by embodiment.
[description of drawings]
Fig. 1 represents that YpbPr/YcbCr of the present invention shares the structural representation of input channel;
Fig. 2 represents that YpbPr/YcbCr of the present invention shares the flow chart of input channel.
[embodiment]
First specific embodiment of the present invention comprises: line by line/and the shared YPbPr/YcbCr input terminal of interlaced video signal, second A/D converter that is used to isolate line synchronizing signal that links to each other with the YPbPr/YCbCr input terminal, be used to judge the CPU of signal format, be used to handle first video a/d converter of progressive input signal, be used to handle the video decoding chip and the video processing circuits of interlaced video input signal, the output of YPbPr/YCbCr input terminal is told the input that two-way in parallel connects first video a/d converter and video decoding chip respectively, and the output of first video a/d converter and video decoding chip links to each other with the input of video processing circuits respectively; The output of second A/D converter links to each other with CPU, and CPU passes through I
2The C bus links to each other with video decoding chip with first video a/d converter respectively.
Its operation principle is: after vision signal enters television receiver from the YPbPr/YCbCr terminal, by second A/D converter, therefrom isolate the line synchronizing signal in the signal earlier, this synchronizing signal is input in the central processor CPU, CPU judges according to line frequency and the form of signal passes through I again
2The C bus provides instructs first video a/d converter and video decoding chip, thus the channel selector of control YPbPr or YCbCr.If CPU judges that signal is progressive signal (YpbPr), then pass through I
2The C bus is turned off the video decoding chip of YCbCr, and signal send video processing circuits to be for further processing after directly handling by first video a/d converter.If CPU judges when signal is interlace signal (YcbCr), then passes through I
2The C bus is turned off first video a/d converter, sends into video processing circuits after signal is handled through video decoding chip and is for further processing.
Be illustrated in figure 1 as second specific embodiment of the present invention, different with first embodiment is, second A/D converter and first video a/d converter are integrated in the same chip, for example be integrated in first video a/d converter, its connected mode is: the output of YPbPr/YCbCr input terminal is told the input that two-way in parallel connects first video a/d converter and video decoding chip respectively, and the output of first video a/d converter and video decoding chip links to each other with the input of video processing circuits respectively; The line synchronizing signal pin of first video a/d converter links to each other with CPU, and CPU passes through I
2The C bus links to each other with video decoding chip with first video a/d converter respectively.
The handling process of this embodiment is as shown in Figure 2:
(1) vision signal is imported from the YPbPr/YCbCr terminal;
(2) first video a/d converters are separated line synchronizing signal from input signal;
(3) line synchronizing signal is input to CPU;
(4) CPU judges the form of signal according to line frequency;
(5) if progressive video signal is then closed the YpbPr video decoding chip, make input signal enter first video a/d converter and handle, send into video processing circuits at last and be for further processing;
(6) if interlaced video signal is then closed first video a/d converter, make input signal enter the YpbPr video decoding chip and handle, send into video processing circuits at last and be for further processing.
Second embodiment compares with first embodiment as most preferred embodiment of the present invention, has simplified circuit, has saved element and cost.
Claims (9)
- One kind line by line/input channel that interlaced video signal is shared, comprise video processing unit, it is characterized in that: also comprise line by line/the shared YPbPr/YcbCr input terminal of interlaced video signal, the signal format judging unit that links to each other with the YPbPr/YCbCr input terminal, progressive signal processing unit that links to each other with the YPbPr/YCbCr input terminal and interlace signal processing unit respectively, described signal format judging unit connects progressive signal processing unit and interlace signal processing unit respectively, be used for input signal for progressive signal time control progressive signal processing unit open and the interlace signal processing unit is closed, input signal for interlace signal time control interlace signal processing unit open and the progressive signal processing unit is closed, the output of described progressive signal processing unit and interlace signal processing unit is connected video processing unit respectively.
- 2. as claimed in claim 1 line by line a kind of/input channel that interlaced video signal is shared, it is characterized in that: described signal format judging unit comprises the line synchronizing signal split circuit and is used to judge the CPU of signal format, the input of described line synchronizing signal split circuit links to each other with the YPbPr/YCbCr input terminal, output links to each other with CPU, and described CPU connects progressive signal processing unit and interlace signal processing unit respectively.
- 3. as claimed in claim 2 line by line a kind of/input channel that interlaced video signal is shared, it is characterized in that: described progressive signal processing unit is first video a/d converter, described interlace signal processing unit is a video decoding chip.
- 4. as claimed in claim 3 line by line a kind of/input channel that interlaced video signal is shared, it is characterized in that: described CPU passes through I 2The C bus connects first video a/d converter and video decoding chip respectively.
- As in the claim 2 to 4 each described line by line a kind of/input channel that interlaced video signal is shared, it is characterized in that: described line synchronizing signal split circuit is second A/D converter.
- 6. as claimed in claim 5 line by line a kind of/input channel that interlaced video signal is shared, it is characterized in that: described first video a/d converter is integrated in the same chip with second A/D converter or is discrete different chips.
- One kind line by line/interlaced video signal shares the method for input channel, it is characterized in that may further comprise the steps:1) vision signal is input to television receiver from the YPbPr/YcbCr input terminal;2) form of judgement input signal is progressive video signal or interlaced video signal;3) control YPbPr path is opened and YcbCr path pass when input signal is progressive signal, control YcbCr path is opened and YPbPr path pass when input signal is interlace signal, make signal pass through the respective input signals treatment circuit, at last signal is sent into video processing circuits and done further processing.
- 8. as claimed in claim 7 line by line a kind of/method of the input channel that interlaced video signal is shared, it is characterized in that: step 2) described judgement may further comprise the steps:2-1) video a/d converter is separated the line synchronizing signal in the input signal;2-2) line synchronizing signal is input among the CPU, CPU judges the form of input signal according to line frequency.
- As claim 7 or 8 described line by line a kind of/method of the input channel that interlaced video signal is shared, it is characterized in that: when judging that input signal is progressive video signal in the step 3), may further comprise the steps: the CPU output order is turned off the decoding chip of YCbCr, sends into video processing circuits after signal is handled by video a/d converter to be for further processing; When judging in the step 3) that input signal is interlaced video signal, may further comprise the steps: the CPU output order is turned off video a/d converter, sends into video processing circuits after making signal by decoding chip to be for further processing.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNB2004100151864A CN1327714C (en) | 2004-01-17 | 2004-01-17 | Inputting channel of line-by-line/intelaced video frequency signal sharing and method thereof |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNB2004100151864A CN1327714C (en) | 2004-01-17 | 2004-01-17 | Inputting channel of line-by-line/intelaced video frequency signal sharing and method thereof |
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| Publication Number | Publication Date |
|---|---|
| CN1642240A CN1642240A (en) | 2005-07-20 |
| CN1327714C true CN1327714C (en) | 2007-07-18 |
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| Application Number | Title | Priority Date | Filing Date |
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| CNB2004100151864A Expired - Fee Related CN1327714C (en) | 2004-01-17 | 2004-01-17 | Inputting channel of line-by-line/intelaced video frequency signal sharing and method thereof |
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Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5041910A (en) * | 1987-07-10 | 1991-08-20 | Sony Corporation | Apparatus having improved switching functions for processing video signals |
| US5267022A (en) * | 1990-11-15 | 1993-11-30 | Sony Corporation | Video signal processing apparatus for videotape recorder/reproducer capable of effecting vertical (and horizontal) emphasis and deemphasis on chrominance signals |
| US5583574A (en) * | 1993-07-14 | 1996-12-10 | Matsushita Electric Industrial Co., Ltd. | Video-data transmitter, video-data receiver, and video-data transceiver for connecting parallel video-data into serial video-data and vice versa |
| CN2496203Y (en) * | 2001-08-13 | 2002-06-19 | 美国安达视频公司 | Video signal processing apparatus with multiple video signal inputs and one video signal output |
-
2004
- 2004-01-17 CN CNB2004100151864A patent/CN1327714C/en not_active Expired - Fee Related
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5041910A (en) * | 1987-07-10 | 1991-08-20 | Sony Corporation | Apparatus having improved switching functions for processing video signals |
| US5267022A (en) * | 1990-11-15 | 1993-11-30 | Sony Corporation | Video signal processing apparatus for videotape recorder/reproducer capable of effecting vertical (and horizontal) emphasis and deemphasis on chrominance signals |
| US5583574A (en) * | 1993-07-14 | 1996-12-10 | Matsushita Electric Industrial Co., Ltd. | Video-data transmitter, video-data receiver, and video-data transceiver for connecting parallel video-data into serial video-data and vice versa |
| CN2496203Y (en) * | 2001-08-13 | 2002-06-19 | 美国安达视频公司 | Video signal processing apparatus with multiple video signal inputs and one video signal output |
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| Publication number | Publication date |
|---|---|
| CN1642240A (en) | 2005-07-20 |
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Granted publication date: 20070718 Termination date: 20120117 |