CN1323379C

CN1323379C - Data-driven circuit and method for driving data therefrom

Info

Publication number: CN1323379C
Application number: CNB031086241A
Authority: CN
Inventors: 孙文堂; 叶信宏
Original assignee: AU Optronics Corp
Current assignee: AUO Corp
Priority date: 2003-04-02
Filing date: 2003-04-02
Publication date: 2007-06-27
Anticipated expiration: 2023-04-02
Also published as: CN1534560A

Abstract

The invention provides a data driving circuit and a method for driving data by the same, the data driving circuit comprises an input module, a plurality of latches, a plurality of shift registers and a digital-to-analog converter, the method comprises the steps of using the input module to receive N-bit digital data, dividing the N-bit digital data into m groups of bit data, using the shift registers to output a plurality of switching signals in sequence to input the m groups of bit data to the latches in sequence, then inputting the latched m groups of bit data to the digital-to-analog converter in sequence according to the sequence of the switching signals, finally using the digital-to-analog converter to convert the digital data into the analog voltage signal, and outputting the analog voltage signal to a data line.

Description

Data drive circuit reaches the method by its driving data

Technical field

The invention provides a kind of data drive circuit (Data Driver) and by the method for its driving data, relate in particular to a kind of digital data driving circuit, and, reach the method for saving the space and this data line being carried out precharge (Pre-Charging) function by its at least one data line that drives a display.

Background technology

LCD (liquid crystal display, LCD) reaching relevant display device is thin little display device, and be found among numerous electric equipment products, distribution range is also extensive in the extreme, act is from the field of notebook computer and digital camera, and even all brought use to the field of space flight and medical diagnostic equipment.Thin Film Transistor-LCD wherein (TFT LCD) can be under the situation that keeps good color contrast and screen scanning refreshing frequency, the picture of plane, careful, high-res is provided, and operates under the low-power; And low temperature polycrystalline silicon LCD (the Low Temperature Poly Silicon LCD that develops of industrial community in recent years, LTPS LCD), can directly be made in driving circuit on the glass substrate, except reaching effective minimizing panel driving core number, reducing material and the packaging cost, more can increase the fiduciary level and compactization of product.

The kenel that liquid crystal display system is generally looked the input data is divided into digital interface and simulation interface, both universal standard specifications are different, and in order to reach power saving, the convenience of system combination and cost-effective purpose, more and more liquid crystal display systems are taked the mode of data with digital kenel input, therefore need digital to analog converter (Digital-to-Analog Converter) is integrated in the data drive circuit, and in order to cooperate the conversion of numeral to simulated data, usually need keep (Sample/Hold) circuit also to be integrated in the data drive circuit latch circuit (Latch) or sampling, and place before the digital/analog converter, please refer to Fig. 1, Fig. 1 is the functional block diagram of data drive circuit 10 in the prior art, shown among Fig. 1 corresponding to a pixel (Pixel) 11 three primary colors (R on the display, G, B) a data drive circuit 10, it includes a load module 12, two-stage latch unit 14,16 (first order latch unit 14 and second level latch units 16), one shift register (Shift Register) 18, and three digital to analog converters (DAC) 20r, 20b, 20g.It comprises three groups of N bit circuitry lines 12r load module 12,12b, 12g, each group N bit circuitry lines is used for receiving one and has the numerical data of N bit, the numerical data of each group N bit corresponds to pixel 11 (Pixel) three primary colors (R on the display respectively, G, B) (numerical data that corresponds on the display one group of N bit of red (R) in a pixel 11 three primary colors is DR0～DR5 to one of them, the numerical data that corresponds to one group of N bit of a pixel 11 three primary colors Smalt (B) on the display is DB0～DB5, and the numerical data that corresponds on the display one group of N bit of green (G) in a pixel 11 three primary colors is DG0～DG5), wherein N is the integer more than or equal to 2, and as shown in Figure 1, the value of N is 6, and just each group digital data is the numerical data of six bits.Two-stage latch unit 14,16 (Latch), after being electrically connected on load module 12, function with buck (Level Shift) and buffering (Buffering), each grade latch unit also includes three latch units, (first order latch unit 14 includes three latch unit 14r, 14b, 14g to correspond on the display pixel 11 (Pixel) three primary colors respectively, second level latch unit 16 includes three latch unit 16r, 16b, 16g), each latch unit all can latch N bit numerical data, so each latch unit all is necessary for the latch unit of N bit; And shift register 18 exportable switching signal SR, to correspond to once that the trichromatic three groups of N bit numerical datas of a pixel 11 (Pixel) all are sent to first order latch unit on the display, allow first order latch unit 14 carry out the function of boosting and cushioning, again data are sent to second level latch unit 16, allow second level latch unit 16 continue to carry out the function of boosting and cushioning.Digital to analog converter 20r, 20b, 20g is connected in after the second level latch unit 16, be used for receiving numerical data by 16 outputs of second level latch unit, with digital data conversion is an analog voltage signal, and export analog voltage signal respectively to data line 22r, 22b, 22g, quality according to the strong and weak control panel of analog voltage signal, and between the first order latch unit 14 and second level latch unit 16 of data drive circuit 10, another switch LP is set usually, originally the numerical data that is latched in the first order latch unit 14 all is sent to second level latch unit 16 successively, so that time of control data stream and make data enter digital to analog converter 20r, 20b, the time of 20g charging is comparatively abundant.The basic framework of above-mentioned prior art has relevant description in many patents about the digital data design of drive circuit and document.People such as Yojiro Matsueda in 1996 at SID 96Digest, deliver in " Low Temperature poly-Si TFT-LCD with integrated 6-bit Digital DataDriver " and use the fabrication techniques of LTPS on glass data drive circuit, and the data drive circuit framework of six digital bits proposed, wherein in order to cooperate the conversion of data, they propose to go in the data drive circuit latch unit is circuit integrated, and place the foregoing structure of digital to analog converter.Then, people such as Yojiro Matsueda continue to sum up " the Conceptof a System on Panel " that it proposes at IDW ' 00 p.p.171-174, analyzed the data drive circuit framework of numeral and simulation therein, and further extra memory is integrated in the system, make the conception of SOP (System on Panel) more complete.Next at US Patent 5,856,816, in " Data driver for liquid crystal display ", people such as Youn then avoid using extra memory, make in the data drive circuit framework, to utilize the register (Register) of a plurality of bits into, driving frequency is divided into lower frequency, to reduce the problem that the high frequency running is brought, though above-mentioned prior art patent and the present invention are all the digital data driving circuit, but at framework, on technical characterictic and the improved purpose great difference is arranged, and, all classify prior art of the present invention as with two pieces of documents of above-mentioned prior art.

By above-mentioned prior art as can be known, in order to latch N bit numerical data, in the data drive circuit of numeral, each latch unit just is necessary for the latch unit of N bit.More and more require today of picture quality the user, it is also important increasingly that display system can show the fineness of color, for instance, general panel can show 4096 looks if want, numerical data just must be the nibble input, that is, this moment, data drive circuit also must possess the digital to analog converter of nibble and the latch circuit or the sampling hold circuit of nibble simultaneously, if will show 262144 looks, then must be with the input of six bit numerical datas, data drive circuit also must possess the digital to analog converter of six bits and the latch circuit or the sampling hold circuit of six bits simultaneously.Yet when the resolution of panel improves, then the size of each pixel also relatively reduces, thereby the space of having limited driving circuit, therefore if will adopt the mode of this digital interface, degree of difficulty just significantly promotes, head it off generally has two kinds of ways, a kind of mode is not use the fabrication techniques of low temperature polycrystalline silicon (LTPS) on glass data drive circuit, and adopt the way of similar amorphous silicon LCD (a-Si LCD), the chip for driving group is pasted on (COG) on glass, the largest benefit of this technology avoids element to link caused problem by " line " or " pin " conduct exactly, it is to be strengthened that yet this kind work has the test of degree of stability such as thermal shock, also not as good as the low temperature polycrystalline silicon technology in the using value of small-medium size panel.In people (Toshiba Corp.) such as T.Morita in 2000 in IDW ' 00, pp.1149-1150, proposing a kind of utilization in " A 2.15 inch QCIF reflective color TFT-LCD with integrated 4-bitDAC driver " selects circuit (Selecting Circuit) to make digital to analog converter and latch circuit reach shared target, to reduce the requirement of data drive circuit to the space, thus, the number of digital to analog converter and latch circuit can significantly be reduced, yet, under this design, each latch circuit wants the bit number of deal with data still must be identical with the bit number of each group digital data simultaneously, that is to say, if numerical data is the nibble input, latch circuit also must be the latch circuit of nibble, if numerical data is the inputs of six bits, latch circuit then also must be the latch circuit of six bits, therefore, does not attain perfect in the saving in circuit and space yet.

Summary of the invention

Therefore fundamental purpose of the present invention is a kind of with a digital data driving circuit (DataDriver), cooperate a method with digital data packets timesharing transmission, to drive at least one data line of a display, reach and save the space and this data line is carried out precharge function, to address the above problem.

The invention provides a kind of method with a data drive circuit (Data Driver) driving data, this data drive circuit is used for driving a data line of a display, this data drive circuit includes a load module, it comprises N bit circuitry lines, be used for receiving one and have the numerical data of N bit, the numerical data of this N bit has m group bit data, wherein N and m are the integers more than or equal to 2, a plurality of latch units (Latch), be electrically connected on this load module, each latch unit is used for latching one group of bit data in this numerical data, and a plurality of shift registers (shift register), be used for exporting in proper order a plurality of switching signals, to control the order that these m group bit data are sent to these a plurality of latch units, an and digital to analog converter (digital to analog converter, DAC), be connected in this a plurality of latch units, be used for receiving numerical data by these a plurality of latch unit outputs, with this digital data conversion is an analog voltage signal, and export this analog voltage signal to this data line, and the N bit circuitry lines that this method includes by this load module receives this numerical data, using these a plurality of shift registers to export a plurality of switching signals in regular turn latchs so that these m group bit data are inputed to these a plurality of latch units in regular turn, order according to the switching signal of this shift register output, these m group bit data that are latched are inputed to this digital to analog converter in regular turn so that this digital to analog converter receives this numerical data, and use this digital to analog converter that this digital data conversion is this analog voltage signal, and export this analog voltage signal to this data line, wherein according to the order of the switching signal of this shift register, input to the numerical data of this corresponding digital to analog converter in these m group bit data earlier, can carry out the function of precharge (Pre-Charging) this data line.

The invention provides a kind of data drive circuit (Data Driver), be used for driving at least one data line of a display, this data drive circuit includes N group bit circuitry lines, correspond to each bit of the numerical data of a N bit (N-bits) respectively, be used for receiving this numerical data, and the numerical data of this N bit is divided into m group bit data, wherein N and m are all the integer more than or equal to 2, m shift register (shift register), be used for exporting in proper order m switching signal, be used for controlling the order of this m group bit data transmission, a plurality of latch units (Latch), be electrically connected on this N group bit circuitry lines, be used for latching the numerical data that transmits by this N group bit circuitry lines, and at least one digital to analog converter (digitalto analog converter, DAC), be used for receiving this digital signal by this latch unit output, this digital signal is converted to an analog voltage signal, and export this analog voltage signal to this data line, wherein receive each bit in the numerical data of this N bit respectively when this N group bit circuitry lines, and after the numerical data of cutting apart this N bit becomes m group bit data, the order of the switching signal that produces according to this m shift register, these m group bit data are inputed to this corresponding latch unit in regular turn to latch, and this m that is latched group bit data also input to this corresponding digital to analog converter in regular turn according to the order of the switching signal of this m shift register generation, and use this digital to analog converter that this digital signal is converted to this analog voltage signal, export this analog voltage signal to this data line.

The invention has the advantages that, method of the present invention is divided into the m group with the numerical data of N bit, and according to m the m that shift register produced an adjacent pulse signal, the time sequencing of following this m adjacent pulse signal to jump up inputs to these m group bit data in the same group of latch unit in regular turn and latchs, thus, each latch unit only need comprise N/m latch circuit (Latch Circuit), and need no longer to comprise that N latch circuit goes to handle the numerical data of N bit, thereby significantly reduced the shared space of circuit, reach the demand of saving the space.

The invention has the advantages that, input to one group of bit data of corresponding digital to analog converter earlier, can carry out the function of precharge (Pre-Charging), to increase the serviceable life and the degree of stability of circuit data line.

Description of drawings

Fig. 1 is the functional block diagram of prior art data drive circuit;

Fig. 2 is the functional block diagram of an embodiment of data drive circuit of the present invention;

Fig. 3 is the sequential chart of switching signal and six bit numerical datas among Fig. 2; And

Fig. 4 is the functional block diagram of another embodiment of data drive circuit of the present invention.

Description of reference numerals in the accompanying drawing is as follows:

10,30 data drive circuits, 11,41 pixels

12,32 load modules

14r, 14b, 14g first order 6-position (bit) latch unit

16r, 16b, 6-position, 16g second level latch unit

18 shift registers

20r, 20b, 20g, 40r, 40b, 40g 6-figure place weighted-voltage D/A converter

22r, 22b, 22g, 42r, 42b, 42g data line

34r, 34b, 34g first order 3-position latch unit

36r, 36b, 3-position, 36g second level latch unit

37r, 37b, 37g third level 6-position latch unit

38 first shift registers, 39 second shift registers

Embodiment

Being exactly of the topmost notion of the present invention is divided into m group bit data with the numerical data of a N bit, utilizes m shift register (shift register) at least again, controls this m and organizes the order that bit data are sent to latch unit.Please refer to Fig. 2, Fig. 2 has followed the similar framework of Fig. 1 prior art for the functional block diagram of an embodiment of data drive circuit 30 of the present invention, but saves space and precharge effect in order to reach, and Fig. 2 embodiments of the invention have been made some great changes.What show among Fig. 2 is a data drive circuit 30 corresponding to a pixel (Pixel) three primary colors (R, G, B) on the display, it includes a load module 32, three grades of latch units 34,36,37 (first order latch unit 34, second level latch unit 36 and third level latch unit 37), two shift registers (Shift Register) 38,39 (first shift register 38 and second shift register 39), and three digital to analog converters (DAC) 40r, 40b, 40g.It comprises three groups of N bit circuitry lines load module 32, each group N bit circuitry lines is used for receiving one and has the numerical data of N bit, the numerical data of each group N bit corresponds to a pixel (Pixel) three primary colors (R on the display respectively, G, B) (numerical data that corresponds on the display one group of N bit of red (R) in the pixel three primary colors is DR0～DR5 to one of them, the numerical data that corresponds to one group of N bit of a pixel three primary colors Smalt (B) on the display is DB0～DB5, and the numerical data that corresponds on the display one group of N bit of green (G) in the pixel three primary colors is DG0～DG5), wherein N is the integer more than or equal to 2, and as shown in Figure 1, the value of N is six, and just default in the present embodiment each group digital data is the numerical data of six bits.After three grades of latch units such as Fig. 2 are electrically connected in load module 32, with prior art have equally buck (Level Shift) and the buffering (Buffering) function, each grade latch unit also includes three groups of latch units, (first order latch unit 34 comprises three groups of latch unit 34r to correspond on the display pixel (Pixel) three primary colors respectively, 34b, 34g, second level latch unit 36 comprises three groups of

latch unit

36r, 36b, 36g, third level latch unit 37 comprises three groups of

latch unit

37r, 37b, 37g), two

shift registers

38,39 export two switching signal SR1 in proper order, SR2 (the first switching signal SR1 and second switch signal SR2), please refer to Fig. 3 this moment, Fig. 3 is two switching signal SR1, the sequential chart of the numerical data of SR2 and six bits, in Fig. 3, we are the example of six bit numerical data outputs with the numerical data DR0～DR5 that corresponds on the display one group of N bit of red (R) in the pixel three primary colors.Cooperate Fig. 3 as can be known by Fig. 2, the first switching signal SR1 and second switch signal SR2 are two adjacent pulse signals, and the time that the first switching signal SR1 jumps up is just early than second switch signal SR2.Digital to

analog converter

40r, 40b, 40g are connected in after second level latch unit 36 and the third level latch unit 37, be used for receiving numerical data by second level latch unit 36 and 37 outputs of third level latch unit, with digital data conversion is an analog voltage signal, and export analog voltage signal respectively to

data line

42r, 42b, 42g, according to the quality of the strong and weak control panel of analog voltage signal.

The embodiment of above-mentioned Fig. 2 is in order to realize pairing data drive circuit 30 frameworks of the disclosed method of the present invention, and detailed operation situation continues to be described below.In the embodiment of Fig. 2, each numerical data of organizing six bits is divided into the dibit metadata, one group of bit data is ordered and is most significant bit tuple (MSB:DR5～DR3, DB5～DB3, DG5～DG3, be to be example in Fig. 3 sequential chart) with DR5～DR3, another group bit data are then ordered and are least significant bit tuple (LSB:DR2～DR0, DB2～DB0, DG2～DG0, be to be example in Fig. 3 sequential chart) with DR2～DR0, therefore, each group bit data has comprised each three bit of the numerical data of six bits, utilize two shift registers 38 again, 39 control the order that this dibit metadata is sent to latch unit, please note, in the embodiment of Fig. 2, because each numerical data of organizing six bits all is divided into the dibit metadata, after the topmost notion of the present invention described in the preceding paragraph, m=2 just, therefore, each latch unit only need latch the numerical data of (N/m=3) bit, that is each latch unit all need only be the latch unit of three bits, also can be described as each latch unit and include the individual latch circuit of three (N/m=3) (Latch Circuit) and go to handle the numerical data of three bits, and must be as in the prior art not being the latch unit of six (N=6) bit.Please continue to consult Fig. 2 and Fig. 3, this dibit metadata (most significant bit tuple MSB, least significant bit tuple LSB) receive into by the N bit circuitry lines of load module 32 after, when the first switching signal SR1 of first shift register, 38 outputs jumps up, most significant bit tuple MSB (in Fig. 3 sequential chart be example with DR5～DR3) can be sampled the three bit latch unit 34r that (sampling) sends into the first order, 34b, 34g, partial three bit latch unit 36r, 36b, the three bit latch unit 37r of the 36g (having buck (Level Shifting) function concurrently) and the third level, 37b, among the 37g, and latch in these three grades of latch units, and connect and see and enter digital to

analog converter

40r, 40b, determine the magnitude of voltage of most significant bit tuple MSB among the 40g, afterwards when the second switch signal SR2 of second shift register, 39 outputs jumps up, least significant bit tuple LSB (in Fig. 3 sequential chart be example with DR2～DR0) can be sampled the three bit latch units that (sampling) sends into the first order, and in the partial three bit latch units (having the function of buck concurrently), and the most significant bit tuple MSB that rewriting is latched in these two groups of latch unit circuit is least significant bit tuple LSB, thus, the time that switching signal of most significant bit tuple MSB least significant bit tuple LSB data morning is jumped up inputs to digital to

analog converter

40r, 40b, 40g, please note, this moment, the three bit latch unit circuits of the third level still latched most significant bit tuple MSB, MSB is introduced into digital to analog converter 40r in advance in the most significant bit tuple, 40b, after determining the magnitude of voltage of most significant bit tuple MSB among the 40g, the signal of least significant bit tuple LSB also enters digital to analog converter 40r immediately, 40b, determine the magnitude of voltage of least significant bit tuple LSB among the 40g, the magnitude of voltage that most significant bit tuple MSB determines before adding decides the analog signal voltage of last conversion, at last this analog signal voltage is write each

bar data line

42r, 42b, 42g also writes in the pixel 41.

Embodiment by above-mentioned Fig. 2 can summarize the several important techniques features of the present invention, at first, be different from the technical characterictic that once numerical data all is sent to latch unit in the prior art, the present invention is because disclose the notion (N and m are the integer more than or equal to 2) that a N bit numerical data is divided into m group bit data, latch in the latch unit and buck so this m group bit data timesharing must be sent to, therefore need to cooperate and go up m the m that shift register a produced switching signal and come in regular turn m to be organized the bit data and input in the latch unit, in the embodiment of Fig. 2, the value of m is predetermined to be two, and numerical data is the numerical data (N=6) of one or six bits, but when real enforcement, N need not limit identical with the embodiment of Fig. 2 with the value of m, should decide on the suitable demand of industrial community, same, because m the m that shift register a produced switching signal is the notion that successively transmits for corresponding to m group bit data, shift register only needs this m group bit data timesharing to be sent in the latch unit and gets final product, the quantity of shift register need not be identical with the group number of bit data, and the switching signal that shift register is exported also need not be adjacent pulse signal, and available other patterns realize.

Moreover, present embodiment has comprised that three grades latch unit is to avoid the buck amplitude excessive and influence the degree of stability of system when considering actual enforcement, if it is single from technical characterictic of the present invention and design concept, because the present invention is divided into m group bit data with a N bit numerical data, latch in the latch unit and need the latch unit of m level to latch respectively and these m group bit data of buck at least during buck in that this m group bit data are sent to, that is to say, in the embodiment of Fig. 2, minimum in fact needs the latch unit of secondary just enough, hence one can see that, the progression of latch unit also need not limit identical with the embodiment of Fig. 2, as long as identical with the group number of bit data or be slightly larger than the group number of bit data, and should decide on the suitable demand of industrial community.As for the bit number of each latch unit in each grade latch unit (that is number of the latch circuit that comprises of each latch unit), after the present invention is divided into a N bit numerical data m group bit data, basically can be reduced to (N/m), in the embodiment of Fig. 2, each latch unit is the latch unit of three bits, but on reality is implemented, the bit number of each latch unit is as long as be the integer that is same as the integer of (N/m) or is slightly larger than (N/m), and should decide on the suitable demand of industrial community, that is to say, in the embodiment of Fig. 2, each latch unit also can make the latch unit of nibble or other bit numbers, just the bit number of each latch unit makes the bit number (N) of approaching more script numerical data, has just lost feature and the meaning of the present invention in order to save the space.

The 3rd, a present invention wherein important techniques feature is, according to the order of the switching signal of shift register, the numerical data that inputs to digital to analog converter in the m group bit data earlier can be carried out precharge function to data line, allow voltage is unlikely to once to promote too fast and lose life-span of hardware.In the embodiment of Fig. 2, most significant bit tuple MSB can be introduced into digital to analog converter 40r in advance, 40b, determine the magnitude of voltage of most significant bit tuple MSB among the 40g, to

data line

42r, 42b, 42g carries out precharge, the signal of least significant bit tuple LSB also enters digital to analog converter 40r subsequently, 40b, determine the magnitude of voltage of least significant bit tuple LSB among the 40g, the magnitude of voltage that most significant bit tuple MSB determines before adding decides the analog signal voltage of last conversion, for example, if digital to

analog converter

40r, 40b, 40g is metric analog voltage signal with binary digital data conversion directly, and six bit numerical datas are divided into two groups and are expressed as (most significant bit tuple MSB among Fig. 2 embodiment, least significant bit tuple LSB) be (110,100), that is most significant bit tuple MSB is (110), least significant bit tuple LSB is (100), MSB is introduced into digital to analog converter 40r in advance when the most significant bit tuple, 40b, among the 40g, can determine 48 volts of (1*2 of magnitude of voltage of most significant bit tuple MSB earlier ⁵+ 1*2 ⁴=48 (V)) and be precharged to

data line

42r, 42b, 42g, subsequently the signal of least significant bit tuple LSB to enter and determine last magnitude of voltage among digital to

analog converter

40r, 40b, the 40g be 52 volts.In like manner, if six bit numerical datas are (011,101), that is most significant bit tuple MSB is (011), least significant bit tuple LSB is (101), when most significant bit tuple MSB is introduced among digital to

analog converter

40r, 40b, the 40g in advance, can determine 24 volts of (1*2 of magnitude of voltage of most significant bit tuple MSB earlier ⁴+ 1*2 ³=24 (V)), subsequently the signal of least significant bit tuple LSB to enter and determine last magnitude of voltage among digital to

analog converter

40r, 40b, the 40g be 29 volts.Please note, correspond to key concept of the present invention equally, because m group bit data only need " timesharing transmission " to get final product to latch unit, and on precharge function, emphasize " inputing to digital to analog converter 40r earlier; 40b; these group bit data of 40g are to data line 42r; 42b; 42g carries out precharge function ", therefore, when the present invention implements in reality, need not limit as Fig. 2 embodiment most significant bit tuple MSB is imported digital to analog converter 40r earlier, 40b, 40g, also can realize precharge function, that is to say, the bit data that need not limit particular group must be imported digital to analog converter 40r earlier, 40b, 40g or back input digital to

analog converter

40r, 40b, 40g can adjust when making in actual demand.See also Fig. 3, Fig. 4 is that Fig. 2 embodiment is with most significant bit tuple MSB and least significant bit tuple LSB input digital to

analog converter

40r, 40b, synoptic diagram after the order of 40g is exchanged, the function of installing shown in Fig. 4 is all identical with Fig. 2 with mark, in Fig. 4, first shift register 38 and second shift register 39 are still exported the first switching signal SR1 and second switch signal SR2 in proper order, the first switching signal SR1 and second switch signal SR2 are two adjacent pulse signals, and the time that the first switching signal SR1 jumps up is also just early than second switch signal SR2, uniquely different be, the embodiment of Fig. 4 connects first shift register 38 and controls least significant bit tuple LSB, second shift register 39 connects controls most significant bit tuple MSB, make least significant bit tuple LSB early than most significant bit tuple MSB input digital to

analog converter

40r, 40b, 40g, also therefore become least significant bit tuple

LSB data line

42r, 42b, 42g carries out precharge function, for instance, if digital to

analog converter

40r, 40b, 40g is metric analog voltage signal with binary digital data conversion directly, and six bit numerical datas are divided into two groups and are expressed as (most significant bit tuple MSB among Fig. 2 embodiment, least significant bit tuple LSB) be (110,100), that is most significant bit tuple MSB is (110), least significant bit tuple LSB is (100), LSB is introduced into digital to analog converter 40r in advance when the least significant bit tuple, 40b, among the 40g, can determine 4 volts of (1*2 of magnitude of voltage of least significant bit tuple LSB earlier ²=4 (V)) and be precharged to

data line

42r, 42b, 42g, subsequently the signal of most significant bit tuple MSB to enter and determine last magnitude of voltage among digital to

analog converter

40r, 40b, the 40g be 52 volts.In like manner, if six bit numerical datas are (011,101), that is most significant bit tuple MSB is (011), least significant bit tuple LSB is (101), when least significant bit tuple LSB is introduced among digital to

analog converter

40r, 40b, the 40g in advance, can determine 5 volts of (1*2 of magnitude of voltage of most significant bit tuple MSB earlier ²+ 1*2 ⁰=5 (V)), to enter and determine last magnitude of voltage among digital to

analog converter

40r, 40b, the 40g be 29 volts to the signal of least significant bit tuple LSB subsequently, certainly, thus, the precharge effect of Fig. 4 embodiment then not as Fig. 2 embodiment come obviously.

After having stated the several important technology features of the present invention, emphasize once more that at last digital data driving circuit 30 of the present invention is to be used for a display, and in various displays, comprise LCD (LCD), low temperature polycrystalline silicon LCD (LTPS LCD), light emitting diode device (LED), Organic Light Emitting Diode (OLED) or organic macromolecular LED diode (PLED) all is contained in the scope of application of the present invention.

Compare with prior art, method of the present invention is divided into the m group with the numerical data of N bit, and in regular turn these m group bit data are inputed to according to the order of the pulse signal that shift register produced and to latch in the latch unit, thus, the number of the latch circuit that each latch unit is included just becomes number originally divided by the value after the m, significantly reduce the complexity and the space of latch unit, reach the demand of saving the space, simultaneously, the one group of bit data that inputs to corresponding digital to analog converter in these m group bit data earlier can be carried out precharge function to data line, increase the serviceable life and the degree of stability of circuit.

The above only is the preferred embodiments of the present invention, and all equalizations of doing according to claim of the present invention change and modify, and all should belong to the covering scope of patent of the present invention.

Claims

1. A method for driving data with a data driving circuit, the data driving circuit is used to drive at least one data line of a display, the data driving circuit includes:

An input module, which includes an N-bit circuit line, is used to receive an N-bit digital data, and the N-bit digital data has m sets of bit data, wherein N and m are integers greater than or equal to 2;

A plurality of latches, electrically connected to the input module, each latch is used to latch a set of bit data in the digital data; and

A plurality of shift registers are used to sequentially output a plurality of switching signals to control the order in which the m groups of byte data are transmitted to the plurality of latches; and

A digital-to-analog converter connected to the plurality of latches for receiving digital data output by the plurality of latches, converting the digital data into an analog voltage signal, and outputting the analog voltage signal to the data Wire;

The method includes:

receiving the digital data by an N-bit circuit line of the input module;

using the plurality of shift registers to sequentially output a plurality of switch signals to sequentially input the m groups of bit data to the plurality of latches for latching;

According to the order of the switching signals output by the shift register, sequentially input the m sets of bit data to be latched into the digital-to-analog converter so that the digital-to-analog converter receives the digital data; and

converting the digital data into the analog voltage signal by using the digital-to-analog converter, and outputting the analog voltage signal to the data line;

According to the sequence of switching signals of the shift register, among the m groups of bit data, the digital data first input to the corresponding digital-to-analog converter will precharge the data line.

2. The method of claim 1, wherein the number of the shift registers is an integer equal to m, and m switch signals are generated by the m shift registers.

3. The method of claim 1, wherein the number of shift registers is an integer greater than m.

4. The method according to claim 2, wherein the m switch signals generated by the m shift registers are m adjacent pulse signals, and are jumped according to the time sequence of the m adjacent pulse signals The m groups of bit data are sequentially input into the same group of latches for latching.

5. The method of claim 4, wherein at least m latches are included in the set of latches.

6. The method as claimed in claim 4, wherein any one latch in the set of latches comprises N/m latch circuits, wherein N/m is an integer.

7. The method of claim 4, wherein any one of the set of latches includes an integer number of latch circuits greater than N/m.

8. The method as claimed in claim 4, wherein the bit data of the m groups to be latched are sequentially transmitted to the corresponding group of latches according to the time sequence in which the m adjacent pulse signals jump. digital-to-analog converter.

9. The method of claim 1, wherein the display is a liquid crystal display, a low temperature polysilicon liquid crystal display, a light emitting diode, an organic light emitting diode, or an organic polymer light emitting diode.

10. A data driving circuit, used to drive at least one data line of a display, the data driving circuit comprising:

N sets of bit circuit lines, which respectively correspond to each bit of an N-bit digital data, are used to receive the digital data and divide the N-bit digital data into m sets of bit data, where N and m are all integers greater than or equal to 2;

m shift registers are used to sequentially output m switch signals to control the order of the m group of byte data transmission;

A plurality of latches, electrically connected to the N sets of bit circuit lines, for latching digital data transmitted from the N sets of bit circuit lines; and

At least one digital-to-analog converter is used to receive the digital signal output by the latch, convert the digital signal into an analog voltage signal, and output the analog voltage signal to the data line;

Wherein when the N groups of bit circuit lines respectively receive each bit in the N-bit digital data, and divide the N-bit digital data into m groups of bit data, according to the m shift registers generated The order of the switching signals, the m sets of byte data are sequentially input to the corresponding latches for latching, and the m sets of bit data to be latched are also based on the order of the switching signals generated by the m shift registers Sequentially input to the corresponding digital-to-analog converter, use the digital-to-analog converter to convert the digital signal into the analog voltage signal, and output the analog voltage signal to the data line.

11. The data driving circuit as claimed in claim 10, wherein the m switch signals generated by the m shift registers are m adjacent pulse signals, and jump according to the m adjacent pulse signals The m sets of bit data are sequentially inputted into the same set of latches in a time sequence for latching.

12. The data driving circuit as claimed in claim 11, wherein the set of latches comprises at least m latches.

13. The data driving circuit as claimed in claim 11, wherein any one latch in the set of latches comprises N/m latch circuits, wherein N/m is an integer.

14. The data driving circuit as claimed in claim 11, wherein any one latch in the set of latches includes an integer number of latch circuits greater than N/m.

15. The data driving circuit as claimed in claim 11, wherein the bit data of the m groups to be latched are sequentially transmitted from the group of latches to the The corresponding digital-to-analog converter.

16. The data driving circuit as claimed in claim 10, wherein the display is a liquid crystal display, a low temperature polysilicon liquid crystal display, a light emitting diode, an organic light emitting diode, or an organic polymer light emitting diode.