CN1310144C - Computer system, BIOS and starting method - Google Patents
Computer system, BIOS and starting method Download PDFInfo
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- CN1310144C CN1310144C CNB2005100037562A CN200510003756A CN1310144C CN 1310144 C CN1310144 C CN 1310144C CN B2005100037562 A CNB2005100037562 A CN B2005100037562A CN 200510003756 A CN200510003756 A CN 200510003756A CN 1310144 C CN1310144 C CN 1310144C
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Abstract
The present invention relates to a starting method of a computer system, particularly to a method for starting a system with a hyper-threading processor. Firstly, the processor is started in a non hyper-threading mode. Secondly, the program code of a basic input-output system (BIOS) is loaded in a quick access memory of the processor. Then, the BIOS program code stored in the quick access memory is used for initializing a main memory and a north bridge chip. Finally, after the main memory is initialized, the processor is restarted in a hyper-threading mode. By the quick access memory, the starting efficiency of the system can be raised. By switching over the non hyper-threading mode, the method can be effectively used for supporting the hyper-threading processor.
Description
Technical field
Present invention is directed to the startup method of computer system, have the method for the system of hyperthread (Hyper-Threading) processor in particular to startup.
Background technology
The 1st figure is the structure of existing computer system.Comprise processor 102, north bridge chips 104, primary memory 106, South Bridge chip 108 and ROM (read-only memory) 110.Comprise rapid-access storage 112 again in this processor 102.Store bios program code in this ROM (read-only memory) 110, be specifically designed to each element in the initialization system, for example the update cycle of storer and clock setting.Computer system 100 is when power initiation, can be introduced into POST (the Power On Self Test) stage, by the program in north bridge chips 104 and the South Bridge chip 108 execution ROM (read-only memory), be Basic Input or Output System (BIOS) (BIOS), to the whole computer system selftest of starting shooting, processor 102 and according to the bios program code initialize main memory 106 in the ROM (read-only memory) 110.The initialization of primary memory 106 comprises many complicated steps, has been that register in the north bridge chips 104 (register) is dynamically adjusted according to the factory plate model specification characteristic of primary memory 106 etc. as readwrite tests.Shown in path 2,, can all deposit in the data of bios program code in the ROM (read-only memory) 110 and the generation of execution test process in the rapid-access storage 112 in order to improve primary memory 106 initialized efficient.By this, shown in path 3, processor 102 can directly be carried out the BIOS that deposits in the rapid-access storage 112, and north bridge chips 104 is directly carried out initialization, and primary memory 106 is tested.Faster because of the speed of processor 102 access rapid-access storagies 112 than the speed of access ROM (read-only memory) 110, test and north bridge chips 104 initialized efficient so improved primary memory 106 widely.
Along with the appearance of hyperthread (Hyper-Threading) processor, said method has also run into bottleneck.General hyperthreaded processor comprises two logic processors, behind power initiation, second logic processor also must be through initialization, and rest on idle state, after first logic processor load operation system, arrange this second logic processor by operating system again, so far could really bring into play function.And the initialization of this second logic processor needs first initialize main memory 106 just can carry out.If the embodiment according to the 1st figure handles in the mode in path 2 and path 3, then can be because of second logic processor no initializtion still, there is not the fast delivery formula (No-Fill Cache) of filling up and make rapid-access storage be in, can be when data write back (write back) because of the corresponding entanglement in address, and make the initialization step generation problem of primary memory 106.
Therefore if the kind efficient with rapid-access storage 112 of desire with start-up system, just must manage to avoid not having and fill up the influence of getting soon.
Summary of the invention
The invention provides a kind of startup method, be used for computer system, this computer system comprises processor, north bridge chips and the primary memory of supporting hyperthread (Hyper-Threading), and this processor comprises rapid-access storage, and this startup method comprises the following steps.At first, this processor is started in non-hyperthread pattern, then bios program code is loaded in this rapid-access storage, and utilize this bios program code that is stored in this rapid-access storage, with this primary memory and this north bridge chips initialization.At last, behind this primary memory initialization, this processor is restarted in the hyperthread pattern.This computer system also comprises ROM (read-only memory), comprises this bios program code, loads this rapid-access storage for the start back.
This processor comprises whether a hyperthread switches the pin position, start hyperthread in order to decision; And first logic processor and second logic processor.This processor is started in the step of non-hyperthread pattern, at first provide first current potential to this hyperthread to switch the pin position, then transmit reset signal, this first logic processor is started, and this second logic processor does not start to this processor.This processor is restarted in the step of hyperthread pattern, at first provide second current potential to this hyperthread to switch the pin position, then transmit this reset signal, this first logic processor is started, and this second logic processor also starts to this processor.
Restart after the hyperthread pattern at this processor, the primary memory of further arranging in pairs or groups is with this second logic processor of initialization, and after this second logic processor is finished initialization, the load operation system.Wherein this first current potential is the logical one value, and this second current potential is the logical zero value.
Description of drawings
The 1st figure is the structural drawing and the data flow of existing computer system;
The 2nd figure is the Computer Systems Organization figure and the data flow of one of embodiment of the invention; And
The 3rd figure is the startup method of the computer system among one of embodiment of the invention the 2nd figure.
[label declaration]
102～processor
104～north bridge chips
106～storer
108～South Bridge chip
110～ROM (read-only memory)
112～rapid-access storage
202～processor
203～the first logic processors
205～the second logic processors
212～rapid-access storage
Embodiment
Present invention is directed to the startup method of computer system, have the method for the system of hyperthread (Hyper-Threading) processor in particular to startup.
In the 2nd figure, disclose the computer system 200 of one of embodiment of the invention.Except comprising north bridge chips 104, primary memory 106, South Bridge chip 108, ROM (read-only memory) 110, the hyperthreaded processor 202 of supporting hyperthread is arranged still.Comprise first logic processor 203 and second logic processor 205 in this hyperthreaded processor 202, and rapid-access storage 212.Be connected with Front Side Bus (FSB) between this north bridge chips 104 and the hyperthreaded processor 202, be connected with memory bus between this north bridge chips 104 and the primary memory 106, for example dual rate (DDR) bus.This north bridge chips 104 comprises that still the acceleration port (AGP) of drawing is to connect display card in addition, and South Bridge chip 108 is mainly used in the data link of low speed device, for example peripheral commissure interface (PCI), USB (universal serial bus) peripheral buses such as (USB), and ROM (read-only memory) 110, wherein store the program code and the value of setting of Basic Input or Output System (BIOS) (BIOS), in order to initialization and the control of carrying out each item in the system.Different with the processor 102 among the 1st figure is, hyperthreaded processor 202 is behind power initiation, and first logic processor 203 starts defaultly, and rapid-access storage 212 wherein is to be in the nothing that can not use to fill up fast delivery formula.If desire this rapid-access storage 212 of activation (Enable), then must make 205 initialization of second logic processor earlier.The initialization step complexity of second logic processor 205 needs ROM (read-only memory) 110 that set initialize routine is provided, and the interaction of collocation primary memory 106 just can be reached.Therefore initialize main memory 106 is a steps necessary in advance.
If desire when this primary memory 106 of BIOS initialization, to be apt to increase efficient with rapid-access storage 212, the words that start with existing method, can be because second logic processor 205 no initializtion still, rapid-access storage 212 is in does not have the fast delivery formula of filling up, data can't correctly write back (write back) corresponding address, and the generation problem.
Comprising a pin position in the hyperthreaded processor 202, be called A31 (not shown), is in order to provide hyperthreaded processor 202 to set opening or closing of hyperthread pattern when resetting (RESET).If the current potential of A31 is high (asserted), then the hyperthread function of this hyperthreaded processor 202 is closed when hyperthreaded processor 202 is reset, and this moment, second logic processor 205 was wherein closed, and only first logic processor 203 starts.Then hyperthreaded processor 202 can be considered single-processor, and rapid-access storage 212 enters normal mode by this, can use for normal.Actual pin position signal and communication protocol are decided by processor model and specification.
The 3rd figure is a kind of startup method provided by the present invention, switches the Push And Release of hyperthread function with pin position A31, and the convenience of rapid-access storage 212 is applied to the initialization procedure of primary memory 106, promotes starting efficiency by this.In step 302, power initiation at first, north bridge chips 104 and South Bridge chip 108 start, and north bridge chips 104 reads bios program and carries out it by South Bridge chip 108 from ROM (read-only memory) 110, whole computer system 200 beginning oneselfs are detected and initialization.In step 304, shown in the path 1 of the 2nd figure, north bridge chips 104 is made as noble potential with pin position A31, and send reset signal to hyperthreaded processor 202 to start it, hyperthreaded processor 202 is started in the pattern of closing hyperthread, and the running of first logic processor 203 and rapid-access storage 212 is just as processor by this.In step 306, shown in the path 2 of the 2nd figure, north bridge chips 104 writes rapid-access storage 212 after the bios program code that stores in the ROM (read-only memory) 110 is read subsequently.In step 308, shown in the path 3 of the 2nd figure, utilize the bios program code that is stored in the rapid-access storage 212 then, 203 pairs of primary memorys of first logic processor 106 carry out known initialization action, comprise test and set.It is efficient to compare reading of ROM (read-only memory) 110 by the access of 203 pairs of rapid-access storagies 212 of first logic processor, and the starting efficiency of system also promotes by this.After primary memory 106 initialized steps were finished, in step 310, north bridge chips 104 was made as electronegative potential with pin position A31, and sent reset signal and restart this hyperthreaded processor 202, made it to start in the hyperthread pattern, shown in the path among the 2nd figure 4.Finished initialization because of primary memory 106 this moment, just can be used to second logic processor 205 is carried out initialization.After the initialization of second logic processor 205 was finished, the hyperthread function of whole hyperthreaded processor 202 was promptly ready.In step 312, further other elements are carried out initialization and load operation system subsequently, use that the function of first logic processor 203 and second logic processor 205 is brought into play fully.
The method that the embodiment of the invention provided, because hyperthreaded processor 202 must be reset for the second time, the state and the content of having deposited in the register in the hyperthreaded processor 202 (Register) can be eliminated, so before resetting for the second time, only carry out minimum steps necessary, for example initialize main memory 106, so that the required step of carrying out once again in back of resetting for the second time tapers to minimum.In the present embodiment, hyperthreaded processor 202 is the Intel Pentium 4 that possesses the hyperthread function
Or Intel Prescott processor.This primary memory 106 can be synchronous dynamic random access memory (SDRAM) or dual rate storer (DDRRAM).But this ROM (read-only memory) 110 can be initialization ROM (read-only memory) (EEPROM).
In sum, the present invention can be applicable in the system that supports hyperthread, kind simultaneously efficient with rapid-access storage 112, and avoided not having the influence of filling up fast delivery piece.
The embodiment that more than provides has highlighted many characteristics of the present invention.Though the present invention discloses as above with preferred embodiment, so it is not in order to limiting scope of the present invention, any those skilled in the art, without departing from the spirit and scope of the present invention, when doing various changes and retouching.The branch section header carried according to regulation of this instructions is not used in and limits that to carry in its content described scope, the especially background technology may not be the known invention that has disclosed in addition, and invention description is also non-in order to limit technical characterictic of the present invention.Be with novelty of the present invention, creativeness and protection domain when look appended claim the person of being defined be as the criterion.
Claims (12)
1. a startup method is used for a computer system, and this computer system comprises processor and the primary memory of supporting hyperthread, and this processor comprises rapid-access storage, and this startup method comprises the following steps:
This processor is started in non-hyperthread pattern;
Bios program code is loaded in this rapid-access storage;
Utilization is stored in this bios program code in this rapid-access storage, with this primary memory initialization; And
Behind this primary memory initialization, this processor is restarted in the hyperthread pattern.
2. startup method according to claim 1, wherein:
This computer system further comprises ROM (read-only memory), comprising this bios program code; And
This bios program code is loaded on this rapid-access storage from this ROM (read-only memory) when tying up to start.
3. startup method according to claim 1, wherein:
This processor comprises:
One hyperthread switches the pin position, whether starts hyperthread in order to decision; And
First logic processor and second logic processor;
This processor is started in the step of non-hyperthread pattern to be comprised:
Provide first current potential to this hyperthread to switch the pin position; And
Transmit a reset signal to this processor, this first logic processor is started, and this second logic processor does not start; And
This processor is restarted in the step of hyperthread pattern to be comprised:
Provide one second current potential to this hyperthread to switch the pin position; And
Transmit this reset signal to this processor, this first logic processor is started, and this second logic processor also starts.
4. startup method according to claim 3, this startup method further comprises the following steps:
Restart after the hyperthread pattern this second logic processor of initialization at this processor; And
After this second logic processor is finished initialization, the load operation system; Wherein this first current potential is the logical one value, and this second current potential is the logical zero value.
5. computer system comprises:
Processor is supported hyperthread, comprises rapid-access storage;
Primary memory;
ROM (read-only memory) is in order to store bios program code; And
North bridge chips; Wherein:
Behind power initiation, this north bridge chips starts in non-hyperthread pattern this processor;
After this processor entered this non-hyperthread pattern, this north bridge chips read this bios program code, and this bios program code is loaded in this rapid-access storage;
This processor utilization is stored in this bios program code in this rapid-access storage, with this primary memory initialization; And
Behind this primary memory initialization, this north bridge chips restarts in the hyperthread pattern this processor.
6. computer system according to claim 5, wherein:
This processor comprises whether a hyperthread switches the pin position, start hyperthread in order to decision; And first logic processor and second logic processor;
This north bridge chips provides first current potential to this hyperthread to switch the pin position, and transmits this first reset signal to this processor, and this processor is started in this non-hyperthread pattern; And
Under this non-hyperthread pattern, this first logic processor starts, and this second logic processor does not start.
7. computer system according to claim 6, wherein:
This north bridge chips provides second current potential to this hyperthread to switch the pin position, and transmits this second reset signal to this processor, and this processor is restarted in this hyperthread pattern;
Under this hyperthread pattern, this first logic processor starts, and this second logic processor also starts; And
This first current potential is the logical one value, and this second current potential is the logical zero value.
8. computer system according to claim 7, wherein:
Restart after this hyperthread pattern this second logic processor of initialization at this processor; And
This computer system is carried out the loading of operating system after this second logic processor initialization is finished.
9. Basic Input or Output System (BIOS), be stored in the ROM (read-only memory) of computer system, this computer system also comprises processor and the primary memory of supporting hyperthread, this processor comprises rapid-access storage, and this Basic Input or Output System (BIOS) system is in order to carry out the following step when this computer system starting:
This processor is started in non-hyperthread pattern;
Bios program code is loaded in this rapid-access storage;
Utilization is stored in this bios program code in this rapid-access storage, with this primary memory initialization; And
Behind this primary memory initialization, this processor is restarted in the hyperthread pattern.
10. Basic Input or Output System (BIOS) according to claim 9, wherein:
This bios program code is to be stored in this ROM (read-only memory); And
This Basic Input or Output System (BIOS) is read out this bios program code from this ROM (read-only memory), and writes this rapid-access storage.
11. Basic Input or Output System (BIOS) according to claim 10, wherein:
This processor comprises also whether a hyperthread switches the pin position, start hyperthread in order to decision; And first logic processor and second logic processor;
This Basic Input or Output System (BIOS) starts in the step of non-hyperthread pattern this processor, comprising:
Make first current potential be applied to hyperthread and switch the pin position; And
Make reset signal be transferred into this processor, this first logic processor is started, and this second logic processor does not start;
This Basic Input or Output System (BIOS) restarts in the step of hyperthread pattern this processor, comprising:
Make second current potential be applied to this hyperthread and switch the pin position;
Make this reset signal be transferred into this processor, this first logic processor is started, and this second logic processor also starts.
12. Basic Input or Output System (BIOS) according to claim 11, wherein:
Restart after the hyperthread pattern this second logic processor initialization at this processor; And
After this second logic processor is finished initialization, start the operating system, wherein this first current potential is the logical one value, this second current potential is the logical zero value.
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| Application Number | Priority Date | Filing Date | Title |
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| CNB2005100037562A CN1310144C (en) | 2005-01-11 | 2005-01-11 | Computer system, BIOS and starting method |
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| CNB2005100037562A CN1310144C (en) | 2005-01-11 | 2005-01-11 | Computer system, BIOS and starting method |
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| CN1310144C true CN1310144C (en) | 2007-04-11 |
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| CN100428158C (en) * | 2005-12-28 | 2008-10-22 | 技嘉科技股份有限公司 | Method and device for fast initialization of BIOS |
| CN101788916B (en) * | 2010-02-09 | 2014-06-04 | 华为终端有限公司 | Method and device for configuring chip |
Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20040268108A1 (en) * | 2003-06-30 | 2004-12-30 | Lechong Chen | Parallel execution of enhanced EFI based BIOS drivers on a multi-processor or hyper-threading enabled platform |
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Patent Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20040268108A1 (en) * | 2003-06-30 | 2004-12-30 | Lechong Chen | Parallel execution of enhanced EFI based BIOS drivers on a multi-processor or hyper-threading enabled platform |
Non-Patent Citations (3)
| Title |
|---|
| Initial observations of the simultaneous multithreading Pentium4 processor Nathan Tuck,Dean M. Tullsen,Proceedings of the 12th International Conference on Parallel Architectures and Compilation Techniques 2003 * |
| Initial observations of the simultaneous multithreading Pentium4 processor Nathan Tuck,Dean M. Tullsen,Proceedings of the 12th International Conference on Parallel Architectures and Compilation Techniques 2003;计算机的一些核心技术的发展 马维新，计算机工程与设计，第18卷第25期 2004 * |
| 计算机的一些核心技术的发展 马维新，计算机工程与设计，第18卷第25期 2004 * |
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