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CN1308797C - Spi兼容串行存储器的识别方法 - Google Patents

Spi兼容串行存储器的识别方法 Download PDF

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CN1308797C
CN1308797C CNB038257300A CN03825730A CN1308797C CN 1308797 C CN1308797 C CN 1308797C CN B038257300 A CNB038257300 A CN B038257300A CN 03825730 A CN03825730 A CN 03825730A CN 1308797 C CN1308797 C CN 1308797C
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CN1720496A (zh
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R·V·迪卡洛
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Artemis Acquisition LLC
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Atmel Corp
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    • GPHYSICS
    • G06COMPUTING; CALCULATING OR COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14Handling requests for interconnection or transfer
    • GPHYSICS
    • G11INFORMATION STORAGE
    • G11CSTATIC STORES
    • G11C7/00Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • GPHYSICS
    • G06COMPUTING; CALCULATING OR COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • GPHYSICS
    • G11INFORMATION STORAGE
    • G11CSTATIC STORES
    • G11C7/00Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/20Memory cell initialisation circuits, e.g. when powering up or down, memory clear, latent image memory
    • GPHYSICS
    • G11INFORMATION STORAGE
    • G11CSTATIC STORES
    • G11C2216/00Indexing scheme relating to G11C16/00 and subgroups, for features not directly covered by these groups
    • G11C2216/12Reading and writing aspects of erasable programmable read-only memories
    • G11C2216/30Reduction of number of input/output pins by using a serial interface to transmit or receive addresses or data, i.e. serial access memory

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Abstract

一种识别串行外设接口(SPI)兼容的串行接口存储器的方法。一微处理器向安装在SPI总线上的一SPI设备发送一单一指令(16)以请求识别信息。含有JEDEC制造商识别码ID(36)、设备识别码ID(34)以及其它任一扩展设备信息(18)的一个字节字符串被发回微处理器。当制造商识别码ID超过1字节时,该字节字符串可能含有一条或多条连续码。字节字符串(32)还包括一字节(26)用于说明微处理器所需读取的扩展设备的字节数量。包括了发出命令(16)和接收回复(18)的识别过程在一个操作中完成。

Description

SPI兼容串行存储器的识别方法
技术领域
本发明涉及存储装置的识别方法,特别地,涉及串行接口存储装置的识别方法。
技术背景
非易失存储器都设置成并行接口编排或串行接口编排。以往,并行接口更为流行,因为其快速、随机存取性能使得它适用于直接代码执行。近年来,串行接口则越来越普遍地应用于存储个人爱好和配置数据,提供低引脚数、低能耗以及更小的封装。并行接口采用独立输出和地址针脚,并且存储器呈矩形阵列。串行接口通常采用双线接线配置,有时将第三根接线用于时钟信号。也有其它接线排列,但时钟信号总是存在的。
已转让给本发明受让人的第4,451,903号、名称为“用于半导体的编码产品和编程信息的方法”的美国专利,示出了一个并行接口。该专利的图4示出了规定在存储器中编码时代表非易失存储器参数的多少。在这个实施例中,包括设备制造商在内的15个不同参数被编码。
串行接口的日益普遍导致串行外设接口(SPI)协议的发展。SPI将串行接口设备的针脚标准化,并且将一组这样的针脚定义为一SPI总线。
尽管串行接口存储器的制造商们(每个制造商根据JEDEC出版物106被指派一制造商识别码,JEDEC出版物106使在设备上编码的制造商识别码标准化)数量正在增加,但是,一旦这些设备安装在一SPI总线上,还没有一种通用的电子方法来识别这些串行接口存储器或者SPI设备。这是有问题的,因为不同的设备具有不同的特性,如电压范围、擦除时间等,并且可能具有不同的架构和命令集。如果多个不同的SPI设备安装在一个SPI总线上,为在系统中运行,就必须一一识别这些不同的设备。
目前通用的用于识别并行非易失存储器的方法,如通用闪存接口(CFI)规范所包括的方法,即采用一个单一、通用指令来识别不同供应商的设备,但这些方法不能运用在串行设备中,因为串行设备中没有允许随机存取并行设备中信息的地址线和数据线。(参阅“通用闪存接口(CFI)规范”,SharpAP-003-CFI-E)。与并行设备可能有16条或更多的地址线以及8至32条数据线不同,以及如上所述与并行设备可以随机存取不同,串行设备有三条线并且是顺序存取信息。明显地,需要有一种方法,通过设备制造商和供应商的专门信息,如设备密度、设备系列和设备版本,不仅可以识别任何和所有安装在系统的SPI总线上的SPI设备,而且还可以识别扩充的设备信息,如加工工艺、模压版本(die revision)、电压值等。
发明内容
本发明提供一种命令与回复串行通信方法以获得有关所安装的SPI存储器的信息。一个请求信息的单一指令发到一SPI设备上,SPI设备回复不定长的的字节字符串,这个字节字符串包括设备制造商的信息、设备识别码、任何扩展的设备信息,如加工工艺、模压版本、电压值、扇区大小、页面大小,擦除次数等。该回复指明了JEDEC制造商识别码(ID)(基于JEDEC出版物106),并且当一个字节不能说明JEDEC制造商识别码(ID)时,可能包括一条或多条连续码(遵守JEDEC出版物106的规定)。该设备按照供应商规定的格式以两个字节识别,如指明设备密度、设备系列和设备版本信息的格式。此外,该回复还包括指明扩展设备信息字符串的长度的一个字节;这定义了获得有关SPI设备的其它信息必须读取的相关字节的数量,同时还防止相关的微处理器读取不必要的数据
附图说明
图1示出了根据本发明的命令和回复串行通信顺序的时序图,横向表示时间,纵向表示数据包幅值。
图2示出了命令和回复通信协议的时序图,这是图1所示协议的另一实施例。
具体实施方式
本发明讨论的不同实施例中所有的设备都是遵循串行外设接口(SPI)协议并且连接在相关微处理器上的串行非易失(“NV”)存储器。如图1所示,一串行NV存储器有至少三条线,芯片选择信号(CS)10、串行入(SI)12和串行出(SO)14。图1还示出了一时钟信号(SCK)38。图1和图2所示的每个转换(transition)都表示8个比特和8个时钟周期。
参见图1,为了识别串行NV存储器,一微处理器在一数据包中以编码脉冲形式向所要求信息的设备发出一命令16以识别该设备、其制造商、以及提供任何扩展设备信息,如:加工工艺、模压版本、电压值、扇区大小、页面大小,擦除次数等。这个命令16,在一实施例中是8比特运算代码(opcode)10011111(9FH),在设备中进入计时。运算代码16必须是专用的,即,不能与其它运算代码功能共享。
为了响应运算代码16,一回复18,即包括一不定长的字节字符串的一数据包,退出计时。在一实施例中,回复18的第一个字节20,即字节n给出根据JEDEC出版物106规定的JEDEC制造商识别码ID 36。回复的次两个字节22、24表示设备的识别码ID数据34。该两个字节22、24是供应商规定数据用以说明特定的信息,如设备密度、设备系列和设备版本的。第四个字节26指明了扩展设备信息字符串32的长度;换句话说,它告诉微处理器为了获得所有关于设备的信息有多少额外的字节需要读取。例如,使用16进制符号,00H表示0个额外字节的扩展信息,01H表示1个额外的字节,0FH表示15个额外的字节,10H表示16个额外的字节,等等,一共可以规定254个信息字节(FFH为以后的扩展而预留)。在这个实施例中,示出了2个扩展设备的信息字节,字节X 28和字节X+1 30。如上所述,扩展设备信息字节32是供应商规定字节用于说明详细的设备信息,如加工工艺、模压版本、电压范围、扇区大小、页面大小和擦除次数,等等。
当JEDEC指派的制造商不能用一个字节来识别时,JEDEC出版物106还提供连续码(7FH)。(JEDEC出版物106要求制造商识别码ID字节包括七个数据比特和一个校验码。因为识别码已分配给多于128个制造商(他们的识别码可以用七个数据比特表示),所以连续码用于说明在后续的制造商“库”注册的制造商(例如,制造商库2列出了从第129到第256个制造商,制造商库3列出了从第257到第384个制造商,等)。多个连续码可以用来表示哪个制造商库含有制造商识别码。例如,没有连续码表示了第一个库中的制造商识别码,一个连续码表示了第二个库中的制造商识别码,两个连续码表示了第三个库中的制造商识别码,等等)。当遇到连续码7FH时,微处理器须继续读取说明制造商识别码ID的字节。第一个非-7FH的字节表示制造商识别码数据的最后一个字节。
如图2所示,根据识别命令16来自设备的回复18可包括随同制造商识别码ID数据36一起的连续码38。这里,连续码7FH 38代表字节n,JEDEC制造商识别码ID 40代表字节n+1。回复18还包括设备识别码ID数据34和如图1所描述的扩展设备信息字符串32。(在其它实施例中,可能出现一个以上的连续码)
如上述图1和图2所示,关于设备的所有可获得信息可以在一个操作中获得。这种识别方法不需要将任何存储地址数据发送到一设备上,因此可以用来识别任何装置而无需改变任何设备的密度(1-Mbit、64-Mbit、256-Mbit等)。换句话说,不需要为了识别设备而将哑字节(dummy bytes)发送到该设备中。

Claims (9)

1.一种用于识别与串行界面存储器兼容的一串行外围界面的方法,包括:
a)采用一个单一指令从所述设备中请求制造商和设备信息;以及
b)接收一不定长的计时字节字符串,所述字符串包括来自所述设备的所请求信息和任何扩展的供应商规定信息,其中,所述计时的字节字符串表示一识别有关所述设备供应商规定信息的扩展信息字符串的长度;所述信息的请求和接收在一次操作中完成。
2.如权利要求1所述的方法,其特征在于,所请求信息的接收还包括读取所请求的信息。
3.如权利要求1所述的方法,其特征在于,所述字节字符串表示设备的制造商。
4.如权利要求1所述的方法,其特征在于,所述字节字符串表示设备的数据。
5.如权利要求4所述的方法,其特征在于,还包括根据供应商的规定格式来识别设备数据。
6.如权利要求3所述的方法,其特征在于,还包括根据JEDEC制造商识别规定来识别设备的制造商。
7.如权利要求6所述的方法,其特征在于,还包括使用至少一个用于提供一JEDEC制造商识别规定的连续码。
8.如权利要求1所述的方法,其特征在于,所述字节字符串以“n”字节识别所述设备的制造商。
9.如权利要求1所述的方法,其特征在于,所述字节字符串以2个字节识别所述设备的数据。
CNB038257300A 2002-10-30 2003-09-25 Spi兼容串行存储器的识别方法 Expired - Lifetime CN1308797C (zh)

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US10/284,597 US7032039B2 (en) 2002-10-30 2002-10-30 Method for identification of SPI compatible serial memory devices

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AU (1) AU2003301772A1 (zh)
CA (1) CA2503812A1 (zh)
NO (1) NO20052563D0 (zh)
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