CN1388534A

CN1388534A - Data writing method of semiconductor memory and semiconductor memory

Info

Publication number: CN1388534A
Application number: CN02126275.6A
Authority: CN
Inventors: 野口充宏; 合田晃; 竹内祐司
Original assignee: Toshiba Corp
Current assignee: Kioxia Corp
Priority date: 2001-02-20
Filing date: 2002-02-20
Publication date: 2003-01-01
Anticipated expiration: 2022-02-20
Also published as: TW550576B; CN1270325C; JP2009277348A

Abstract

A semiconductor integrated circuit device includes a first data transfer line electrically connected to a first memory cell block, a second data transfer line electrically connected to a second memory cell block, a charge circuit which charges any one of the first and second data transfer lines, a first data store circuit, second and third data store circuits electrically connected to the first data store circuit, a charge/discharge circuit which charges or discharges a voltage node on the basis of the data held in the third data store circuit, a first connecting circuit which electrically connects the voltage node to any one of the first and second data transfer lines, a fourth data store circuit, and a second connecting circuit which electrically connects the fourth data store circuit to the voltage node.

Description

The method for writing data of semiconductor storage and semiconductor storage

Technical field

The present invention relates to conductor integrated circuit device, even be particularly related to the consecutive storage unit narrow method for writing data that also can reduce the Nonvolatile semiconductor memory device of the data perturbation that produces owing to capacitive coupling at interval, and Nonvolatile semiconductor memory device.

Background technology

Can the tunnel type dielectric film will be passed through, the electric charge that utilizes tunnel current to be injected into electric charge accumulation layer place by raceway groove is implemented storage as digital bit (binary digit) type information, measure with the electricity of the corresponding mos field effect transistor of this quantity of electric charge (MOSFET) and lead variation, and then the Nonvolatile semiconductor memory device that information is implemented to read comes out.Yet Highgrade integration along with storage unit, the formerly formation of Nonvolatile semiconductor memory device and writing mode in the technology, can make the capacitive coupling of storage unit electric charge accumulation interlayer increase, and then have the problem that may get muddled by the data in the write sequence adjacent memory unit.Below at first with reference to Figure 37 to Figure 43, the problem that technology example is formerly existed describes.

Figure 38 A, Figure 38 B represent in the technology formerly a kind of and non-type (NAND type) or with the circuit diagram of the cell block of type (AND type) EEPROM (Electrically Erasable Programmable Read Only Memo) (EEPROM).

In Figure 38 A, Figure 38 B, reference number M0～M15 and M0 '～M15 ' represents storage unit, reference number 49 and 49 ' expression by for example with non-type (NAND type) piece and a memory cell block forming with type (AND type) piece.Memory cell block 49,49 ' is connected with some data select lines (WL0-WL15).And memory cell block 49 also is connected with memory cell block selection wire SSL, GSL, and what reference number BL1, BL2 represented is the data conveyer lines, they according to not shown and the mutually orthogonal direction configuration of data select line.Each storage unit within the memory cell block 49, the point of crossing that is formed on data conveyer line and data select line is located, and logarithm is executed maintenance factually and taken out independently.Here, storage unit for example has the electric charge accumulation layer and transistor represent data with the quantity of electric charge in this electric charge accumulation layer for conduct.These memory cell blocks 49 can form a plurality of memory cell arrays 1 along data conveyer line direction and the formation of data select line direction.

Figure 39 show include read amplifying circuit, a memory cell array 1 of technical examples formerly, and the floor plan example of sensor amplifier 46.In Figure 39,, data select line WL0-WL15 and piece selection wire SSL, GSL have been omitted in order to understand figure easily.

In Figure 39, reference number BL1x, BL2x (x=a, b, c ... k) expression is the data conveyer lines, and they are connected with as shown in figure 38 memory cell block 49,49 ' respectively, and are connected with a sensor amplifier x by transistor Q1x, Q2x.Alphabetical a, the b of note, c ... k is that following target sum also can be for a plurality of for the simple expression employed subscripts of some array storage unit floor plan (index).In other words be exactly, for sensor amplifier owing to need be provided with the transistor bigger than storage unit 1, thus a sensor amplifier 46 will share by some data conveyer lines so that dwindle the area that sensor amplifier occupies.And this sensor amplifier 46 can be a kind of device that the storage unit implementation data is read of being used for, and can be also used as the data of write storage unit are implemented the temporary transient register of preserving usefulness.This sensor amplifier 46 can also be connected the data input that writes, reads respectively with the data line I/O, the I/OB that are connected with output buffer 45.Below in a conventional manner, will be called line direction, will be called column direction along the direction of data conveyer line along the direction of data select line.

The occasion that writes for the storage unit M1 ' implementation data in memory cell block 49 ' in the technology circuit formerly as shown in figure 38, can by with the data register output voltage as with the mode that writes the corresponding magnitude of voltage of data, the data conveyer line BL2 of these connections is implemented to adjust.Meanwhile, for the tunnel type dielectric film of non-volatile memory cells in storage unit applies very high voltage so that electric current flows, to compare the programmed control voltage Vpgm with quite big potential difference (PD) with the data conveyer line current potential of implementing to write, the pulse type that injects the enough time with charge carrier is applied to data select line WL1 place.For this occasion, necessarily the data of storage unit M1 ' mistake can not be write to memory cell block 49 ' adjacent memory unit piece 49 in.And, necessarily the data of storage unit M1 ' mistake can not be write to storage unit M1 ' adjacent memory unit M0 ' in.In this technical examples formerly, owing to these storage unit M0 ', M1 ', M1 are connected with a sensor amplifier 46, so can not implement writing of arbitrary data simultaneously to a plurality of storage unit that are connected with a sensor amplifier.

Figure 40 shows the write sequence that can go wrong in the technical examples formerly.

Process flow diagram when Figure 40 represents storage unit M1 that belongs to two adjacent column and the write operation of M1 ' difference implementation data.This example imagination is formed on the identical trap, and can execute the short-access storage of wiping in the lump factually by logarithm, and the original state of storage unit all is in state " 11 ", and the negative electric charge of accumulating that promptly is set as the electric charge accumulation layer is to be decreased to minimum state.For this formation of technical examples formerly, write the order of data at first array storage unit that is connected with data conveyer line BL1, at first by I/O, I/OB, to write data latching after reading the data register place of amplifying circuit 46, the data that write to first row are implemented to write, and will be stored in the data register place in the sensor amplifier 46 to the threshold decision result that first column data is implemented the storage unit read, write, what whether whole storage unit of distinguishing first row had subsequently finished write operation distinguishes operation (SE120).Adopt this mode, just can form threshold distribution shown in the dotted line among Figure 41, for example storage unit M1 '.Corresponding among Figure 41, and according to the convention in the technology formerly with the occasion of four value threshold distribution, set rise by the lower side of threshold ratio corresponding with the value of " 11 ", " 10 ", " 00 ", " 01 " successively.

Subsequently, write (SE121) to following arbitrary data of direction adjacent memory unit M1 embodiment as " 11 ", " 10 ", " 00 ", " 01 ".Adopt this mode, just can make the negative charge of electric charge accumulation layer among the storage unit M1, along with the value increase of each data.Here, as the negative charge increase of electric charge accumulation layer among the storage unit M1, its voltage also will rise.Here, the electric charge accumulation layer is in electric floating state, so, will make the voltage of the middle electric charge accumulation layer of storage unit M1 ' increase along with the increase of negative charge amount among the storage unit M1 by the capacitive coupling between the electric charge accumulation layer among electric charge accumulation layer among the storage unit M1 ' and the storage unit M1.The increase of this threshold value with storage unit M1 ' adjacent memory unit M1 in data will increase rapidly when " 01 ", and for " 11 " time, will remain unchanged.Because the data among the storage unit M1 may be arbitrary value, thus will produce " threshold amplitude increase " shown in the solid line among Figure 41, and also formerly the technology example can not be implemented control to this increase in the write operation of SE120.

Therefore, when transporting the row operation (SE122) that enforcement is read to the data among the storage unit M1 ' subsequently, because described " increase of threshold amplitude ", can make the difference of implementing to read the threshold value of judgement usefulness and implementing to write between fashionable threshold value diminish, thereby can make the probability that the error in data of " 10 " is read as " 00 ", and the probability increase that the error in data of " 00 " is read as " 01 ".

On the other hand, also exist and the same problem of technical examples formerly even belong to the storage unit of adjacent lines.Figure 42 represents the storage unit that belongs to two adjacent lines process flow diagram that writes of implementation data respectively.The original state of storage unit is state " 11 ", and the negative electric charge of accumulating that is set as the electric charge accumulation layer is to be decreased to minimum state.

At first to the storage unit M1 ' that is connected with WL1, embodiment is as a certain data write operation (SE123) of " 11 ", " 10 ", " 00 ", " 01 ".Adopt this mode, just can form threshold distribution shown in the dotted line among Figure 43, for example storage unit M1 '.Subsequently, to along a certain data write operation of column direction adjacent memory unit M0 ' embodiment as " 11 ", " 10 ", " 00 ", " 01 ".Adopt this mode, the negative charge of electric charge accumulation layer increases with the value of each numerical value among the storage unit M0 '.And as the negative charge increase of electric charge accumulation layer among the storage unit M0 ', its voltage also will rise.Here, the electric charge accumulation layer is in electric floating state, so the capacitive coupling between the electric charge accumulation layer among electric charge accumulation layer and the storage unit M0 ' among the storage unit M1 ' will make the voltage of the middle electric charge accumulation layer of storage unit M1 ' increase along with the increase of negative charge amount among the storage unit M0 '.The increase of this threshold value with storage unit M1 ' adjacent memory unit M0 ' in data will increase rapidly when " 01 ", and for " 11 " time, will remain unchanged.Data among the storage unit M0 ' can be arbitrary value.Therefore, with " the threshold amplitude increase " that produces shown in the solid line among Figure 43, and,, can not implement control to the increase of this threshold value so formerly technical examples is implemented write operation at SE123 because storage unit M0 ' is connected with a sensor amplifier 46 with M1 '.

Therefore, when the program (SE125) the subsequently data among the storage unit M1 ' being implemented to read, because described " increase of threshold amplitude ", can make the difference of reading the threshold value of judgement usefulness and implementing to write between fashionable threshold value diminish, thereby can make the probability that the error in data of " 10 " is read as " 00 ", and the probability increase that the error in data of " 00 " is read as " 01 ", and then can produce the data corruption that data " 00 " is taken as data " 01 ", and the data corruption that data " 10 " is taken as data " 00 ".

Self-evident, belong to the problem in the storage unit of adjacent lines, be owing to read the formation that amplifying circuit is connected and cause with one by a data conveyer line.

And, misread out in order not occur, just the threshold distribution of storage unit need be extended to higher threshold value place always.Yet here, self electric field of accumulating electric charge will make the data retention characteristics when threshold ratio is higher, be lower than the data retention characteristics of threshold ratio when low, so be difficult to obtain the good data retention performance.

And as shown in Figure 38 A, storage unit be connected in series form with non-type (NAND type) memory cell block in, the storage unit for being connected with storage unit series connection that implementation data is read must apply the voltage higher than threshold distribution maximal value to grid.Therefore, repeat to read action and make negative charge be injected into the electric charge accumulation layer, and then its threshold value is risen, the threshold value of " 11 " is increased, and then become data corruption and wrong reason of reading or the like problem.

As mentioned above, formerly this Nonvolatile semiconductor memory device in the technology is writing the consecutive storage unit implementation data, has the problem that data is changed owing to capacitive coupling.

Summary of the invention

The present invention is exactly the invention that addresses the above problem usefulness, the method for writing data that a kind of semiconductor storage provided by the invention is used, but its described semiconductor storage can have implementation data first memory cell block of write operation once more that includes one first storage unit at least, but and the implementation data that includes second storage unit adjacent at least second memory cell block of write operation once more with first storage unit, and the step of this method for writing data can comprise:

Step to the described first storage unit implementation data write operation;

After to the described first storage unit implementation data write operation, to the step of the described second storage unit implementation data write operation;

After to the described second storage unit implementation data write operation, to the step of described first storage unit implementation data judgement;

And when data no show that described data judged result is described first storage unit, to the described first storage unit implementation data step of write operation once more.

And, the method for writing data that a kind of semiconductor storage provided by the invention is used, but its described semiconductor storage can have the implementation data memory cell block of write operation once more that includes two first storage unit adjacent one another are, that be the form that is connected in series or is connected in parallel and second storage unit at least, and the step of this method for writing data can comprise:

Step to the described first storage unit implementation data write operation;

And a kind of conductor integrated circuit device provided by the invention is characterized in that and can have:

But implementation data is first memory cell block of write operation once more, and described first memory cell block has one first storage unit at least;

But implementation data is second memory cell block of write operation once more, and described second memory cell block has second storage unit adjacent with described first storage unit at least;

The first data conveyer line, the described first data conveyer line directly is connected with described first memory cell block, or by described first memory cell block being implemented to select the alternative pack of usefulness be electrically connected with described first memory cell block;

The second data conveyer line, the described second data conveyer line directly is connected with described second memory cell block, or by described second memory cell block being implemented to select the alternative pack of usefulness be electrically connected with described second memory cell block;

Charging circuit, described charging circuit are used for an enforcement charging to described first data conveyer line and the described second data conveyer line;

First data holding circuit, described first data holding circuit has two voltage stable point at least;

Second data holding circuit, described second data holding circuit is electrically connected with described first data holding circuit;

The 3rd data holding circuit, described the 3rd data holding circuit is electrically connected with described first data holding circuit;

Charging and discharge circuit, described charging and discharge circuit are used for according to the data that remain on described the 3rd data holding circuit first voltage node being implemented charge or discharge;

First connecting circuit, described first connecting circuit are electrically connected in described first voltage node and described first, second data conveyer line;

The 4th data holding circuit, described the 4th data holding circuit has two voltage stable point at least;

And second connecting circuit, described second connecting circuit makes described the 4th data holding circuit be electrically connected with described first voltage node.

But implementation data is the memory cell block of write operation once more, and described memory cell block has and includes two first storage unit adjacent one another are, that be connected in series or be connected in parallel and second storage unit at least;

The data conveyer line, described data conveyer line directly is connected with described memory cell block, or by described memory cell block being implemented to select the alternative pack of usefulness be electrically connected with described memory cell block;

Charging circuit, described charging circuit is implemented charging to described data conveyer line;

Charging and discharge circuit, described charging and discharge circuit are implemented charge or discharge according to the data that remain on described the 3rd data holding circuit place to first voltage node;

First connecting circuit, described first connecting circuit make described first voltage node be electrically connected with described data conveyer line;

And second connecting circuit, described second connecting circuit is electrically connected described the 4th data holding circuit and described first voltage node.

First memory cell array, but described first memory cell array includes and has mutual edge and data conveyer line implementation data first, second memory cell block of write operation once more of the direction configuration of quadrature and a plurality of storage unit of being connected in series or being connected in parallel mutually, and along with the described data conveyer line direction of quadrature data select line that form, that described first, second memory cell block is connected in parallel mutually, and the data that three values are above of the storage unit in described first memory cell array are implemented storage as logical value;

And second memory cell array, but described second memory cell array include have for described first memory cell array along with described data conveyer line implementation data the 3rd, the 4th memory cell block of write operation once more of the direction configuration of quadrature and a plurality of storage unit of being connected in series or being connected in parallel mutually, with the data select line shared data selection wire of described first memory cell array, the storage unit in described second storage unit is implemented storage with the data of two-value as logical value.

And a kind of conductor integrated circuit device provided by the invention can have:

But implementation data is a plurality of first memory cell blocks of write operation once more;

But and a plurality of second memory cell blocks of writing once more of implementation data;

It is characterized in that from described a plurality of first memory cell blocks and described a plurality of second memory cell block erase data, described a plurality of first memory cell blocks are implemented write operation, and remain on the erase status implementation data when reading at described a plurality of second memory cell blocks, so that the data of described a plurality of second memory cell blocks are consistent with the data in described a plurality of first memory cell blocks.

Description of drawings

The schematic block diagram that Fig. 1 uses as the semiconductor storage of first embodiment of the invention for expression.

The schematic plan arrangenent diagram that Fig. 2 uses as a memory cell array in the semiconductor storage of first embodiment of the invention and a floor plan example reading amplifying circuit for expression.

The process flow diagram that Fig. 3 uses as the data write activity example of the semiconductor storage of first embodiment of the invention for expression.

The threshold distribution synoptic diagram that Fig. 4 uses for the threshold setting among the relevant Fig. 3 of explanation.

Fig. 5 reads the process flow diagram that the action example is used for expression as the data of the semiconductor storage of first embodiment of the invention.

The threshold distribution synoptic diagram that Fig. 6 uses for the threshold setting among the relevant Fig. 5 of explanation.

The schematic block diagram that Fig. 7 uses as the semiconductor storage of second embodiment of the invention for expression.

The process flow diagram that Fig. 8 uses as the data write activity example of the semiconductor storage of second embodiment of the invention for expression.

The threshold distribution synoptic diagram that Fig. 9 uses for the threshold setting among the relevant Fig. 8 of explanation.

The schematic block diagram that Figure 10 uses as the semiconductor storage of third embodiment of the invention for expression.

Figure 11 is the figure of a piece example usefulness of expression sensor amplifier 46.

Figure 12 A, Figure 12 B, Figure 12 C, Figure 12 D, Figure 12 E are the figure of the practical circuit of expression data register R1, R2.

Figure 13 A, Figure 13 B, Figure 13 C, Figure 13 D, Figure 13 E, Figure 13 F, Figure 13 G, Figure 13 H, Figure 13 I, Figure 13 J, Figure 13 K are for representing the figure of the practical circuit that data register TR3 uses.

Figure 14 A, Figure 14 B, Figure 14 C, Figure 14 D, Figure 14 E, Figure 14 F are the figure of the practical circuit of indication circuit 10.

Figure 15 A, Figure 15 B are the figure of the fortune row logic of indication circuit 10.

The process flow diagram that Figure 16 uses as the data reversal action example of the semiconductor storage of third embodiment of the invention for expression.

Figure 17 be illustrated in can data reproduction data register R1 and can the data register R2 of data reproduction between a process flow diagram that example is used of implementation data exchange.

Figure 18 reads the process flow diagram that the action example is used for expression as the data of the semiconductor storage of third embodiment of the invention.

Figure 19 is the figure of explanation to the threshold setting among Figure 18.

Figure 20 is the process flow diagram of using as the data write activity example of the semiconductor storage of third embodiment of the invention.

The process flow diagram that Figure 21 uses for the SE36 among Figure 20.

The process flow diagram that Figure 22 uses for the SE37 among Figure 20.

The process flow diagram that Figure 23 uses for the SE38 among Figure 20.

The process flow diagram that Figure 24 uses for the SE39 among Figure 20.

The process flow diagram that Figure 25 uses for the SE40 among Figure 20.

The process flow diagram that Figure 26 uses for the SE41 among Figure 20.

The process flow diagram that Figure 27 uses for the SE42 among Figure 20.

Figure 28 is the circuit diagram of a circuit example of expression sensor amplifier 46 usefulness.

Figure 29 is the circuit diagram of a circuit example of expression sensor amplifier 46 ' usefulness.

Figure 30 A, Figure 30 B are synoptic diagram that the threshold setting variation is used of explanation.

Figure 31 A uses the equivalent circuit diagram of a memory cell examples in the semiconductor storage of the present invention first, second, third embodiment for expression.

Figure 31 B uses the planimetric map of a memory cell examples in the semiconductor storage of the present invention first, second, third embodiment for expression.

Figure 32 A is the sectional view along the line 32A-32A among Figure 31 B.

Figure 32 B is the sectional view along the line 32B-32B among Figure 31 B.

Figure 33 A, Figure 33 B use the sectional view of a memory cell examples in the semiconductor storage of fourth embodiment of the invention for expression.

Figure 34 A uses the equivalent circuit diagram of a memory cell examples in the semiconductor storage of fifth embodiment of the invention for expression.

Figure 34 B uses the planimetric map of a memory cell examples in the semiconductor storage of fifth embodiment of the invention for expression.

Figure 34 C is the sectional view along the line 34C-34C among Figure 34 B.

Figure 34 D is the sectional view along the line 34D-34D among Figure 34 B.

Figure 35 A uses the equivalent circuit diagram of a memory cell examples in the semiconductor storage of sixth embodiment of the invention for expression.

Figure 35 B uses the planimetric map of a memory cell examples in the semiconductor storage of sixth embodiment of the invention for expression.

Figure 35 C is the sectional view along the line 35C-35C among Figure 35 B.

Figure 35 D is the sectional view along the line 35D-35D among Figure 35 B.

Figure 36 A uses the equivalent circuit diagram of a memory cell examples in the semiconductor storage of seventh embodiment of the invention for expression.

Figure 36 B uses the planimetric map of a memory cell examples in the semiconductor storage of seventh embodiment of the invention for expression.

Figure 36 C is the sectional view along the line 36C-36C among Figure 36 B.

Figure 36 D is the sectional view along the line 36D-36D among Figure 36 B.

The schematic block diagram that Figure 37 uses for a kind of semiconductor storage in the technology formerly.

Figure 38 A is the equivalent circuit diagram of expression with non-type (NAND type) unit.

Figure 38 B is the equivalent circuit diagram of expression with type (AND type) unit.

Figure 39 is for the memory cell array in the technology formerly and read the schematic plan arrangenent diagram that amplifying circuit is used.

Figure 40 is the illustrative diagram that illustrates that the program that goes wrong in the technology is formerly used.

Figure 41 illustrates formerly the illustrative diagram that the threshold value distribution problem is used to occur in the technology.

Figure 42 is the illustrative diagram that illustrates that the program that goes wrong in the technology is formerly used.

Figure 43 illustrates formerly the illustrative diagram that the threshold value distribution problem is used to occur in the technology.

Embodiment

Below with reference to the description of drawings embodiments of the invention.

(first embodiment)

Fig. 1 and Fig. 2 represent the schematic block diagram used as the semiconductor storage of first embodiment of the invention, with and memory cell array and read the schematic plan arrangement plan that amplifying circuit is used.In the following description, give identical reference number with part identical among Figure 37 and Figure 43, and omitted repeated detailed description.And in Fig. 2, in order to understand easily figure, the memory cell array 1 that is being provided with along the paper left and right directions and write sequence storage have also been omitted with the memory cell block in the memory cell array 7 49,49 ' common storage unit control gate WL0～WL15, SSL, GSL.

Memory cell array 1 can be made of memory cell block 49, the 49 ' seniority among brothers and sisters non-volatile memory cells being implemented be connected in series or be connected in parallel as shown in Figure 2.And, also be provided with the data in the data conveyer line of memory cell array 1 are implemented to read, or read amplifying circuit 46 what write that data implement to keep usefulness.This amplifying circuit 46 of reading can be also used as data register, and can will for example constitute as main body with flip-flop circuit.Reading amplifying circuit 46 also is connected with data inputoutput buffer 45.This connection can be passed through to implement control from the output signal of the column decoder 48 of addressing impact damper 47 receiver address signals, and then the data that will be applied to data input/output interface I/O place write to memory cell array 1 place and can sense data from IO interface I/O.In order to carry out the selection of storage unit, promptly, also be provided with line decoder 3 in order to select grid SSL, GSL to implement control to data control gate WL0～WL15 and piece to memory cell array 1.

As shown in Figure 1, substrate electric potential control circuit 42 is for the current potential of the p type trap 23 that forms memory cell array 1 (referring to Figure 32 etc.) being implemented control and be provided with, and is preferably in to implement to wipe to form the above erasing voltage of 10V that can boost when handling.But also form circuit 41a, fashionable with box lunch to writing by the storage unit implementation data of selecting in the memory cell array 1, can produce than supply voltage higher write voltage Vpgm.Except this Vpgm produces circuit 41a, also be provided with in addition and write fashionable can the generation in data and be applied to writing circuit 41b, when data are read, being applied to reading of non-selected storage unit place circuit 41c takes place of non-selected storage unit place, apply to the storage unit of selecting that the first voltage Vref that threshold determination voltage uses produces circuit (41d) and the second voltage Vref produces circuit (41e) with voltage Vread with medium voltage Vpass.For writing, wipe and read various states, all can implement control here, so that apply needed voltage output to Data Control line drive 2 by control circuit 40.Voltage Vpgm can for more than the 6V to the voltage below the 30V, voltage Vpass can for more than the 3V to the voltage below the 15V.And, voltage Vread can for more than the 1V to the voltage below the 9V, for the occasion that is with non-type (NAND type) array format, preferably adopt than the voltage that writes about the high 1V of upper threshold read interference so that can guarantee enough read currents and reduction.Produce circuit (41d) and second voltage Vref generation circuit (41e) as the first voltage Vref, each threshold value that can be set in consecutive storage unit is for example located the centre of separating threshold value of the threshold distribution of " 10 " and " 00 ".Data Control line drive 2 be a kind of can be according to the output of line decoder 3, described voltage output is applied to the on-off circuit that writes or read control gate WL0～WL15, SSL on the needed storage unit, GSL place.

Be provided with two voltage Vref in the present embodiment and produce circuit 41d and 41e, so for implementing the occasion that antecedent writes to each consecutive storage unit, the output that can set voltage Vref generation circuit 41e for produces the high Δ V of output of circuit 41d than voltage Vref.This Δ V preferably can be set as the degree that equates with the threshold value ascending amount of this storage unit in the occasion of consecutive storage unit being implemented write.

And in the present embodiment, also form the write sequence storage with memory cell array 7, make the output of Data Control line drive 2 and memory cell array 1 shared.Adopt this form of the composition, each data conveyer line all can be stored the write sequence of adjacent memory unit.

And this write sequence storage forms one for data conveyer line direction to each memory cell block 49, and is connected in parallel with the data conveyer line respectively with memory cell array 7.Assessment of this data conveyer line and write sequence and storage be with sensor amplifier 46 ', with and data register be connected, and carry out the write sequence storage with the writing of memory cell array 7, wipe, the input and output of read-out voltage and signal thereof.

Write sequence assessment and storage can write needed number for minimum cutting apart with the number of sensor amplifier 46 '.For block, Fig. 1 represents four that with dashed lines is divided into memory cell array 1.Be four blocks of supposition here, yet this block number can be natural number, be preferably 2 from the angle of geocoding ^m(m=0,1,2 ...) individual.If block is 2 ^mIndividual, then prepare (2 ^m+ m+1) with last sensor amplifier 46 ', can also utilize for example Hamming code symbol, with bit error correction to 1 bit of the cell array 7 of write sequence storage.Be in the explanation below, the sensor amplifier number that is included in the cell array 7 of write sequence storage is j.

The input and output of sensor amplifier 46 ' can be connected to reading with the steering logic 40 that writes enforcement control usefulness with foundation storage unit write sequence information.And, can be with the address of the physical address of storage unit and logical address being implemented conversion as adda according to storage unit write sequence information, and with its input as steering logic 40.The output of steering logic 40 is connected with control circuit 4 with the verification of wiping of wiping the position of checking treatment according to the positional information control of cutting apart the page or leaf record.Thisly wipe verification, can be used as and cut apart a page sensor amplifier signal, and implement to cut apart the column decoder 48 of usefulness and be connected respectively cutting apart page or leaf with the output of control circuit 4.In the drawings for simply and not expression, the control signal of control sensor amplifier action is connected with control signal sel1, sel2 with control circuit 40.

Below to using the storage unit structure in first embodiment to describe.Storage unit structure as described below also can use in second, third embodiment as described later.

Figure 31 A and Figure 31 B are the schematic equivalent circuit diagram of expression respectively and non-type (NAND type) memory cell block 49 usefulness, and schematic plan view.In the following description, with the structure of non-type (NAND type) memory cell block 49 ' because and identical with non-type (NAND type) memory cell block 49, so also represent with reference number 49.

In Figure 31 B, the memory cell block of expression shown in Figure 31 A is the structure that three row are connected in parallel.And in Figure 31 B,, only represent the structure of control grid electrode below 27 in order to understand the structure of storage unit easily.

Shown in Figure 31 A, non-volatile memory cells M0～the M15 that is made of the MOS type with electric charge accumulation electrode 26 (MOS type) transistor is the form of being connected in series, and the one end is connected with the data conveyer line that is labeled as BL with transistor S1 by selection.Its other end is connected with the common source line that is labeled as SL with transistor S2 by selection.These transistors all are formed on the same p type trap 23.The control electrode of each storage unit M0～M15 is connected with the data conveyer line that is labeled as WL0～WL15 respectively.For from selecting a memory cell block and be connected with the data conveyer line along a plurality of memory cell blocks of data conveyer line, this selection is selected to be connected with connecting line SSL with piece with the control electrode of transistor S1.Select to select connecting line GSL to be connected with piece, to form so-called and non-type (NAND type) memory cell block 49 (zone shown in the dotted line) with the control electrode of transistor S2.In the present embodiment, control wiring SSL by selecting grid and GSL and memory cell data control is with the electric charge accumulation electrode 26 of the wiring WL0～WL15 electric conductor with layer, to implementing along paper left and right directions adjacent memory unit to connect and formation.At memory cell block 49 places, the piece selection wire of SSL, GSL can be to form more than at least one stick and along the direction identical with data select line WL0～WL15, so that can realize densification here.In the present embodiment, be connected with 16=2 in memory cell block 49 expressions ⁴The example of individual storage unit, the storage unit that is connected with data select line with the data conveyer line can be for a plurality of, yet are preferably 2 from the angle of implementing geocoding ⁿIndividual (n is a positive integer).

Figure 32 A is that the sectional view of this figure and storage unit is suitable along the sectional view of the line A-A among Figure 31 B.Figure 32 B is the sectional view along the line B-B among Figure 31 B.

Shown in Figure 31 B, Figure 32 A and Figure 32 B, can be 10 in boron impurity concentration ¹⁴Centimetre ^-3(cm ^-3)～10 ¹⁹Centimetre ^-3(cm ^-3) between p type silicon area (semiconductor regions) 23 in, by by for example saying that thickness is 3 millimicrons of (nm)～15 millimicron silicon oxide layers that (nm) forms, or the tunnel gate insulating film that forms of oxynitride film 25,25SSL, 25GSL, form thickness and be 10 millimicrons of (nm)～500 millimicron (nm), by being added with 10 ¹⁸Centimetre ^-3(cm ^-3)～10 ²¹Centimetre ^-3(cm ^-3) phosphorus or the polysilicon of arsenic the electric charge accumulation layer 26,26SSL, the 26GSL that form.These can not form the element separation location of dielectric film 24 that is made of silicon oxide layer, but form with 23 autoregistrations of p type silicon area.And, this can be after p type silicon area 23 places be deposited with oxynitride film 25 and electric charge accumulation layer 26 comprehensively, by the patterning mode, p type silicon area 23 is implemented such as the degree of depth is the corrosion of 0.05 micron (μ m)～0.5 micron (μ m), form by being embedded into into dielectric film 24.Like this since oxynitride film 25 and electric charge accumulation layer 26 can be formed on the whole plane that does not have step part, so can carry out the film forming that homogeneity is higher, characteristic is consistent.

Thereon, can also be by by thickness being silicon oxide layer or oxynitride film or the piece dielectric film 50,50SSL, the 50GSL that constitute by silicon oxide layer/silicon nitride film/silicon oxide layer of 5 millimicrons of (nm)～30 millimicron (nm), form thickness and be 10 millimicrons of (nm)～500 millimicron (nm), by being added with concentration 10 ¹⁷Centimetre ^-3(cm ^-3)～10 ²¹Centimetre ^-3(cm ^-3), the polysilicon of for example phosphorus, arsenic or boron or the like impurity, or the lit-par-lit structure of tungsten silicide (WSi) and polysilicon, or the control gate 27 of the lit-par-lit structure of nickel silicide (NiSi), molybdenum silicide (MoSi), Titanium silicide (TiSi), cobalt silicide (CoSi) and polysilicon formation.This control gate 27 can extend to the block edge place along the paper left and right directions by the mode that is connected with consecutive storage unit piece 49 among Fig. 3 1B always, forms data select line WL0～WL15.And p type silicon area 23 preferably can pass through n type silicon area 22, applies voltage respectively independently with p type silicon substrate 21, so that can reduce to wipe the load of booster circuit when handling, suppresses the electric power that consumes.And, fashionablely can use the FN tunnel current writing, implement to write fashionable comparing with utilizing thermionic current, can suppress power consumption more expeditiously.In the grid shape in the present embodiment, because dielectric film 24 lids are covering the sidewall of p type silicon area 23, so this sidewall can be owing to the corrosion operation not be exposed state before forming floating gate electrode 26, thereby can prevent that gate electrode 26 is positioned at than p type silicon area 23 position of downside more.Therefore, at the boundary of 24 of p type silicon area 23 and dielectric films, will be difficult to form and make the parasitic transistor that the grid electric field is concentrated, threshold value is low.Owing to can not produce because electric field is concentrated writing threshold value decline phenomenon, reaching so-called bypass (sidewalk) phenomenon of occurring, have the more transistor of high reliability so can produce.

Shown in Figure 32 B, in the both sides of these gate electrodes, also being formed with clamping, by thickness be the n type diffusion layer 28 side wall insulating film 43, that form source electrode or drain electrode that the silicon nitride film of 5 millimicrons of (nm)～200 millimicron (nm) or silicon oxide layer constitute.Utilize these diffusion layers 28, electric charge accumulation layer 26 and control gate 27, can form with the quantity of electric charge that the is stored in electric charge accumulation layer 26 place floating grid type EEPROM (Electrically Erasable Programmable Read Only Memo) (EEPROM) as quantity of information, the length of this grid is 0.5 micron (μ m) with down to more than 0.01 micron (μ m).Forming the n type diffusion layer 28 of source electrode or drain electrode, can be 10 according to the surface concentration of its phosphorus, arsenic, antimony ¹⁷Centimetre ^-3(cm ^-3)～10 ²¹Centimetre ^-3(cm ^-3), the degree of depth is that mode between 10 millimicrons of (nm)～500 millimicron (nm) forms.These n type diffusion layers 28 are common by consecutive storage unit, realize being connected with non-type (NAND type).

In the drawings, reference number 26SSL, 26GSL are the gate electrodes that is connected with the piece selection wire that is equivalent to SSL, GSL respectively, and are formed on in one deck with floating gate electrode in the described floating grid type EEPROM (Electrically Erasable Programmable Read Only Memo) (EEPROM).Longer by the gate length that makes gate electrode 26SSL, 26GSL than the gate length of the gate electrode of storage unit, such as can for 1 micron (μ m) with down to the mode more than 0.02 micron (μ m), can guarantee to implement to have bigger conducting/disconnection ratio when piece is selected with non-selection, and then can prevent mistake and read and miss and write phenomenon.

By being formed on the one-sided n type diffusion layer 28d that constitutes source electrode or drain electrode of 27SSL, can be connected with the data conveyer line 36 that constitutes by tungsten and tungsten silicide, titanium, titanium nitride or aluminium or the like (BL) by contact 31d.Here, the mode of data conveyer line 36 (BL) by being connected by the adjacent memory unit piece in Figure 31 B, is formed up to block boundary along the paper above-below direction always and partly locates.On the other hand, be formed on the n type diffusion layer 28S of one-sided formation source electrode of 27SSL or drain electrode, can be connected with the source electrode line that is labeled as SL by contact 31s.This source electrode line SL can in Figure 31 B, be formed up to block boundary along the paper left and right directions always and partly locate by the mode that is connected by the adjacent memory unit piece.Certainly, be formed up to the mode that block boundary is partly located along the paper left and right directions always, can also form source electrode line by making n type diffusion layer 28S.These be labeled as BL contact, be labeled as the contact of SL, can be used in the conductive material of the polysilicon that was coated with in n type or the p section bar material and tungsten, tungsten silicide, aluminium (Al), titanium nitride (TiN), titanium (Ti) or the like, and these conductive materials are packed into contact hole and the electric conductor zone that constitutes.And, between these contacts BL, contact SL and described transistor, also can use for example by silicon dioxide (SIO ₂) and the interlayer dielectric 28 that constitutes of silicon nitride (SiN) implement to fill.And the place, top at contact BL also is formed with by for example silicon dioxide (SIO ₂), the dielectric film protective seam 37 that constitutes of silicon nitride (SiN) or polysilicon or the like, and not shown, by the upper wiring of for example tungsten (W), aluminium (Al) and copper (Cu) or the like formation.

Fig. 2 represents to include memory cell array 1 and the sensor amplifier 46 of reading amplifying circuit, and a floor plan example of memory cell array 7 and sensor amplifier 46 '.In Fig. 2,, omitted data select line WL0～WL15 and piece selection wire SSL, GSL, and that these selection wires are memory cell blocks 49,49 ' of paper left and right directions is common in order to see figure easily.

In Fig. 2, reference number BL1x, BL2x (x=a, b, c ... k) expression data conveyer line, they are connected respectively with the memory cell block shown in the figure 49,49 ', and are connected with a sensor amplifier x by transistor Q1x, Q2x.Alphabetical a, the b of note, c ... k is the simple additional subscript of using (index) in order to represent a plurality of storage unit floor plan forms, and following target sum also can be for a plurality of.Expression is respectively disposed two structure along data conveyer line direction and data select line direction in Fig. 2, but a plurality of in order to prevent from also can to dispose along the capacity coupled influence of data select line direction adjacent memory unit, considers to be preferably 2 from the angle of geocoding ⁱ(i is a positive integer) is individual.In the time of need being provided with than the big transistor of memory cell array 1 at the sensor amplifier place, a sensor amplifier 46 can be common by some data conveyer lines, so that can reduce the shared area of sensor amplifier.Fig. 2 represents that the data conveyer line BL that is connected with sensor amplifier is respectively two occasion, yet also can be one or four, considers to be preferably 2 from the angle of simplifying address encoding circuit ⁿ(n is a positive integer) is individual.

Particularly for the occasion that is two, and following two adjacent storage unit of direction both sides in the arbitrary data storage unit, the storage unit of reading for implementation data simultaneously.Therefore, adjacent data is implemented once to read,, reduce the adjacent data number of buffers, thereby can simplify circuit so can shorten data readout times for reducing in the influence that follows direction consecutive storage unit threshold value.

In order to prevent to adopt the formation that on a data conveyer line, only connects a sensor amplifier 46 along the capacity coupled influence of data conveyer line direction adjacent memory unit.Sensor amplifier 46 is a kind of amplifiers that the storage unit implementation data is read of being used for, and can be also used as the data of write storage unit are implemented the temporary transient data register of preserving usefulness.This amplifying circuit 46 of reading can also pass through transistor Qxa, Qxb (x=a, b, c ... k), reading, write data line I/O, the I/OB that the data inputoutput buffer 45 of usefulness is connected respectively with implementation data connects jointly.Here, for the data conveyer line capacitive coupling noise that the voltage fluctuation that can reduce owing to connecting line I/O, I/OB produces, connecting line I/O, I/OB are formed, along the line direction of storage unit to reduce the area that connects up.

And in Fig. 2, reference number BL1xd, BL2xd (x=a, b, c ... j) expression is read the data conveyer line that storage unit in proper order is connected with storage unit.Here, belong to the memory cell block 49,49 ' of memory cell array 7 that storage unit is read order, identical with the memory cell block 49 that belongs to memory cell array 1,49 ' the form of the composition.Be included in the memory cell block 49,49 ' in the memory cell array 7, can be formed on the p type silicon area (p type trap) 23 identical with memory cell block 49,49 ' in the memory cell array 1, and preferably make erasing voltage and write voltage, is identical with respect to the storage unit that is included in the memory cell array 1 with storage unit in being included in memory cell array 7, so that can reduce the deviation of characteristic.

Sensor amplifier 46 ' is that a kind of write sequence is stored with the data in the memory cell array implements to read the amplifier of usefulness, and can be also used as the register of the data that write to storage unit being implemented temporary transient preservation usefulness.This sensor amplifier 46 ' can also pass through transistor Qxda, Qxdb (x=a, b, c ... j), write, read with implementation data respectively common connection of data line I/O ', I/OB ' that the control circuit 40 of usefulness is connected.And the gate electrode of transistor Q1xd and Q1x is connected with the common control line sel1 that extends along the paper left and right directions of Fig. 2, and the gate electrode of transistor Q2xd and Q2x is connected with common control line sel2 along the paper left and right directions extension of Fig. 2.Can carry out the control of data select line with control line sel1, sel2 with little wiring area thus.

The present invention compares with the example of technology formerly that is not provided with the memory cell array 7 that enforcement is stored to the storage unit write sequence, and in the memory cell array portion 1 of Fig. 2, data conveyer line direction does not increase, and can less ground holding circuit area.And in Fig. 2, reading the amplification control signal is shared by sensor amplifier 46 and 46 ', so for the storage unit that is connected with same data select line, the unit 7 that can simultaneously write sequence be stored and the unit 1 of data storage are as the structure that carries out program composition, wipes and read.By adopting this structure,, also can reduce the increase of the line number signal that the unit caused that the write sequence storage is set significantly the both sides of sensor amplifier and memory cell array even form the unit area 7 of write sequence storage.In circuit as shown in Figure 2, formerly the technology example is compared the wiring that always extends to the outside that is increased, the needed transistor Qxda of minimum block number drive wire, and connecting line I/O ', I/OB ', mostly be most (block number+2) bar, if, can under condition, easily implement planar configuration unlike the wiring layer of technology increase formerly so in wiring, use and the identical wiring layer of connecting line BL of technology formerly.And, between the unit area 7 of write sequence storage and memory cell array 1, do not need to implement trap and separate, also remain smaller interval between them so can make.

Here to sensor amplifier and data register 46,46 ', to present embodiment owing to can use the amplifying circuit of reading that for example Japanese kokai publication hei 7-182886 number (U.S. Pat 5452249) disclosed, every bit can both verification use, and narrate among the 3rd embodiment as described later read amplifying circuit, so omit.Full content in the U.S. Pat 5452249 all is introduced in this application with the form of list of references.

Below with reference to Fig. 3 and Fig. 4, the data write activity of present embodiment is described.In the following description for two state of value, state " 0 " is illustrated in the state that electric charge accumulation layer 26 has for example electronics or the like charge carrier injection, threshold value is risen, and state " 1 " is illustrated in the original state that the floating gate electrode place in the electric charge accumulation layer 26 does not have charge carrier to inject, threshold value is descended.For four state of value, erase status is taken as " 11 " in the following description, makes threshold value begin to be followed successively by " 10 ", " 00 ", " 01 " from a lower side at write state.Therefore, utilize so-called Gray code, even read, also can not produce the mistake of two bits, thereby can reduce the probability of error in data owing to adjacent threshold distribution produces mistake.

Here, the memory cell block that implementation data writes, the known mode logarithm of electronics that can be by for example wiping electric charge accumulation layer 26 or the like is executed factually and is wiped, and becomes state " 1 ", or state " 11 ".The initial value of the data register in the sensor amplifier 46,46 ' is made as the data erase state that is in.Self-evident, by suitable voltage reversal or the like mode, can make the condition counter-rotating of state " 1 " and " 0 " easily.

Reference number below with reference among Figure 38 describes storage unit.In order to understand explanation easily, consider the storage unit M1 ' that is connected with data line BL2a is implemented the occasion that four Value Datas write here.To write mark enough with two-value with Fig. 3 and the corresponding antecedent of Fig. 4, write " 00 " or " 01 " state of mark with the antecedent of storage unit M1 ' same page, the state that the storage unit M1 that connects near the expression earlier writes storage unit M1 ' implementation data, state " 11 " expression be in addition various states.On the other hand, write state " 00 " or " 01 " of mark with the antecedent of storage unit M1 same page, the state that expression earlier writes storage unit M1 implementation data than adjacent storage unit M1 ', state " 11 " expression various states in addition.

At first, the data among the storage unit M1 with the adjacent data conveyer line BL1a of data conveyer line BL2a are read at the data register place in reading amplifying circuit 46.Storage unit M1 is formed on and storage unit M1 ' position adjacent place here, for belonging to the storage unit of same block, so, can pass through data conveyer line BL1x (x=a, b, c simultaneously by its action ... k) data of storage unit are implemented to read.Meanwhile, (x=a, b, c with data conveyer line BL1xd read in the data register place in sensor amplifier 46 ' ... data (SE6) in the unit of the write sequence storage that j) is connected.At this moment sense data is judged the threshold value of usefulness, can be for higher than state " 11 " upper threshold and than the low value of state " 01 " threshold value lower limit, and preferably be taken as the value at the only about half of place of state " 01 " threshold value lower limit and state " 11 " upper threshold, so that can guarantee maximum safety coefficient easily.Read action by this, can whether be with the unit of write sequence storage read state, promptly whether be state " 00 " or state " 01 ", be stored in and be arranged in the data register place of reading amplifying circuit 46 '.

Subsequently, implement to judge, judge whether unit that write sequence is stored is in state " 00 " or state " 01 " (SE7) by read the data that amplifying circuit 46 ' locates by 40 pairs of control circuits.Unit for the write sequence storage is in the occasion of state " 11 ", owing to be the state that enforcement does not write to consecutive storage unit M1, will continue the action that enforcement writes to storage unit M1 '.In other words be exactly, page register in reading amplifying circuit 46 is in after the initial value of erase status, write data by external connection line I/O, be sent to purpose and cut apart page register 46 places (SE11 '), when antecedent writes the state of being labeled as " 01 " or state " 00 ", when promptly being in write state, being sent to by control circuit 40 and being positioned at the data register place of reading within the amplifying circuit 46 '.

Subsequently, the storage unit that is comprising storage unit M1 ' is implemented verification read (SE8), and the antecedent that belongs to same page with storage unit M1 ' is write mark, when only wiping bit, implement to append and write (SE12 ', SE13).SE8 is one and implements to write once more and not make the unnecessary threshold value that writes to rise according to the antecedent that has write being write mark, reduces writing the program that stress applies with respect to tunnel type dielectric film 25.

At SE7, be in the occasion of state " 0 " in the unit of write sequence storage, make consecutive storage unit M1 become the state that antecedent writes.For this occasion, the data of a page or leaf of reading by SE6, temporarily store back (SE10) at the temporary storage device place by for example data inputoutput buffer 45, page register with 46 is in after the initial value of erase status, to write data again is sent to purpose from external connection line I/O and cuts apart page register 46 (SE11), and,, antecedent is labeled as " 11 " when writing, when promptly being in non-write state, can send it to data register in 46 ' from control circuit 40.Write mark for belonging to the antecedent that writes down with one page, implement to append simultaneously to write (SE12) with storage unit M1 '.The threshold distribution situation of storage unit M1 when here, being illustrated in Fig. 4 and writing data and be four value threshold values.Before the program of SE12, be the threshold distribution shown in the dotted line among Fig. 4, but as illustrating in the technical examples formerly, after SE12, because capacitive coupling and threshold value is partly risen, shown in the solid line among Fig. 4, distribution range is wide threshold distribution.In the present embodiment, can pass through data inputoutput buffer 45 subsequently, at SE10 the data that temporarily are stored in storage unit M1 in the temporary storage device, that comprise one page are implemented to transmit (SE14), being located at antecedent writes the state of being labeled as " 11 ", when being non-write state, is sent to data register place in 46 ' by control circuit 40.And, by the data of storage unit M1 are implemented to append the mode that verification writes, shown in the dot-and-dash line among Fig. 4, make the maximal value of threshold distribution scope keep certain substantially and minimum is risen, thereby reduce its dispersion of distribution (SE15).Adopt this mode, can increase the separation width of write state threshold distribution, and as read decision threshold and write mark according to antecedent and change, also can keep the voltage security coefficient of threshold value.Here, can make the variable quantity of storage unit threshold value, be changed to state " 01 " always by state " 11 " by the SE12 program.Special needs to be pointed out is, for the state " 11 " of expression erase status, with measuring the judgement of sensor amplifier that positive threshold value uses to the threshold value that is in minus side, because the variation of operating point is difficult to mensuration, so it need be extended to more than the 2V.Therefore, the variable quantity of threshold value is 4V during to state " 01 " by state " 11 ", this is sizable, in contrast to this, the changes of threshold amount that the present invention can make storage unit by the SE15 program less than write about the threshold distribution width (＜0.5V 〉, so SE15 is decreased to formerly below the 0.5V/4V of technology example～0.125 times the influence that storage unit M1 ' threshold value is risen, and promptly it can be suppressed to be very little value.

Yet the temporary storage device here also can adopt the data register that is formed within the sensor amplifier 46, and this can reduce data and transmit the needed time, and the electric power of the required consumption of driving data lines I/O.

Below with reference to Fig. 5 and Fig. 6, describe read action as the data of present embodiment.

In order to understand explanation easily, consider the occasion of reading here by the storage unit M1 ' implementation data that is connected with data line BL2a.At first, read the data of the storage unit M1 on the data conveyer line BL1a that is connected with data line BL2a in the data register in sensor amplifier 46.Here, storage unit M1 is formed on storage unit M1 ' and follows direction position adjacent place, and for belonging to the storage unit of same block.At this moment, the data (SE1) in the unit of the write sequence storage that is connected with data conveyer line BL1ad are read at the data register place in sensor amplifier 46 ' simultaneously.At this moment, sense data is judged the threshold value of usefulness, can be for higher than the upper threshold of state " 11 " and than the low value of threshold value lower limit of state " 10 ".Read action by this, can investigate or antecedent write storage unit M1, or be stored in data register in the sensor amplifier 46 ', the data of the storage unit M1 in the block are in the state of wiping.

Subsequently, implement to judge, judge whether storage unit M1 implements to write (SE2) than storage unit M1 ' antecedent by utilizing the data in 40 pairs 46 ' of control circuits and 46.Be in occasion for the unit of write sequence storage for the write state of state " 00 " or state " 01 ", or the data of the storage unit M1 within the block all are position " 11 ", are the occasion of erase status, owing to storage unit M1 is not implemented write operation after storage unit M1 ' writes, so when reading judgment threshold and be first setting value (SE4), storage unit M1 ' is implemented to read (SE5).First reads threshold value as shown in Figure 6, is the threshold distribution of the storage unit of erase status " 11 " according to consecutive storage unit, preferably is located at threshold value and separates the cardinal principle centre position of width and sentence just to separate in the width in threshold value and put into decision threshold.On the other hand, be in the occasion of state " 11 " for the unit of write sequence storage, and some occasion that is not in erase status " 11 " in the data at the storage unit M1 place within the block, it after storage unit M1 ' writes the state that enforcement writes to storage unit M1, so when reading judgment threshold and be second setting value (SE3), storage unit M1 ' is implemented to read (SE5).Second reads threshold value can be as shown in Figure 6, suppose according to SE10～SE15, implement the threshold distribution append this storage unit M1 writing after to consecutive storage unit M1 ', preferably be located at threshold value and separate the cardinal principle centre position of width and sentence just and in threshold value separation width, put into decision threshold.By can clearly knowing the second threshold ratio first threshold rising Δ V among Fig. 6.This Δ V is approximately (threshold value of consecutive storage unit when state is " 01 ")-(threshold value of consecutive storage unit when state is " 11 ").

Aforesaidly read, write, not only can be applied to follow direction, be the storage unit M1 of storage unit M1 ' for consecutive storage unit, also can be applied to for consecutive storage unit along column direction, be storage unit M0 ' and the M2 ' of storage unit M1 ', as long as will be in the said write order relevant storage unit M1 partly be rewritten as storage unit M0 ' or storage unit M2 ', data line BL2x is replaced with data line WL1, data line BL1x replace with data line WL0 or WL2 gets final product.

J.H.Chern is at paper IEEE Electron Device Letters, 13.No.1.pp32 point out in～34 (1992), share the capacity C of the adjacent electric charge accumulation interlayer of direction along source electrode, drain electrode, when the thickness of electric charge accumulation layer be T, electric charge accumulation interlayer be spaced apart S, when the length of electric charge accumulation layer in source/drain extreme direction is W, if the thickness of tunnel insulator film is below 1/10 of interval of electric charge accumulation interlayer, proportional with following formula, this is known.

C &Proportional; 1.064 (\frac{T}{S}) {(\frac{T}{T + 0.5 S})}^{0.695} + (\frac{W}{W + 0.8 S}) {(\frac{T}{T + 0.5 S})}^{0.804}

For the occasion of T＜0.5S in the above-mentioned formula, the electric field of electric charge accumulation layer is terminal with the source, so the electric capacity of electric charge accumulation interlayer is represented only less than { T/ (T+0.5S) } item.In contrast, occasion for T＞0.5S, source/drain is more weak to the shield effectiveness of electric charge accumulation layer electric field, will sharply rise so compare the electric capacity of electric charge accumulation interlayer with the occasion of T＜0.5S, thereby the threshold variation between consecutive storage unit is increased.In other words be exactly, in the present invention because adjacent memory unit is shared source electrode and drain electrode, so be that the twice of electric charge accumulation layer thickness T can be given full play to its effect when following at the interval of electric charge accumulation interlayer S.

The advantage that can obtain when adopting present embodiment is as follows.

1. in the present embodiment the data that write of consecutive storage unit are all implemented verification and write.Therefore, even after consecutive storage unit implements to write, also threshold distribution can be remained within the smaller scope.

2. after the piece initial erase, do not need storage unit is implemented to wipe processing, only implement write operation, so threshold distribution can be remained within the smaller scope.Therefore, when the trap potential in the short-access storage is returned back to 0V, no longer need turnaround time afterwards in long erasing time, so can implement write-in operation at high speed.And, no longer need to use to apply the circuit that negative voltage is used, so can make the circuit and the trap simple structureization of Data Control line drive 2 at the grid place.Particularly reading the needed time (period) when data is tR, the data write time that comprises verification is tW, the delivery time that the temporary storage device implementation data is transmitted is when being tt, write state is judged only needs the time suitable with tW, so can (implement write operation in the time of tR+2 * tW+2 * tt) in up.

3. compare with two pages of parts among as described later second embodiment, temporary storage device can be one page part, thus can further reduce the occupied area of temporary storage device, and can reduce power consumption.

4. compare with the occasion of wiping among as described later second embodiment,, do not apply and wipe stress and write stress again, so can obtain to have the more storage unit of high reliability at the page or leaf of not implementing to write of cutting apart.

5. compare with as described later the 3rd embodiment, it can also be applied in the occasion of storage two Value Datas in the storage unit.

6. owing to be respectively arranged with the unit of write sequence storage with respect to partition member, thus can in each block, set write sequence arbitrarily, thus can be to threshold value enforcement correction.

And, even the data in memory cell array 7 memory cell arrays 1 of write sequence storage usefulness are the occasion of the above multi-value data of two values, also can implement storage to two Value Datas, thereby can obtain enough threshold value safety coefficient, and the mistake that can reduce the memory cell array 7 of write sequence storage usefulness is read probability and data corruption probability.

(second embodiment)

Fig. 7 is the schematic block diagram of expression as second embodiment of the invention.

Present embodiment and first embodiment are identical substantially, only are the forms of the composition that memory cell array 7, sensor amplifier 46, the second voltage Vref of write sequence storage produces circuit (41e), and corresponding write sequence and first embodiment are different.And, in the present embodiment with first embodiment in identical part, and identical voltage relationship all is denoted by like references, so omitted the detailed description to them here.

In Fig. 7, data input and output connecting line I/O or I/OB link to each other with control circuit 40 then.And connecting by the output signal of circuit of control circuit 40 to the control underlayer voltage, and the SE126 by as described later, the timing that weak erase operation is used is implemented in control.

In the following description, transistorized conducting state (ON), expression gate electrode place is applied with the voltage higher than transistor threshold, thereby make the source electrode of metal insulatioin semiconductor field effect transistor (MISFET) and the state that drain electrode is in conducting, transistorized blocking state (OFF), be illustrated in the gate electrode place and be applied with the voltage littler, thereby make the source electrode of metal insulatioin semiconductor field effect transistor (MISFET) and the state that drain electrode is in blocking-up than transistor threshold.Transistorized threshold value is electric current between source electrode and the drain electrode gate voltage when being 40 nanoamperes (nA) * (channel width)/(grid long) of flowing through.And in the present embodiment, because the logical circuit of conventional complementary metal oxide semiconductor (CMOS) (CMOS) constitutes simple, so get threshold value on the occasion of transistor be that example describes, for the occasion that does not have to specify, control voltage when providing is provided the Vcc forward voltage that for example is set within 0.5V～15V scope, then logic is current potential " H ", circuit is in conducting state, for example establish 0V ground voltage (GND) control voltage when providing is provided, then logic is current potential " L ", and circuit is in blocking state.Self-evident, be the transistorized occasion of negative value even adopt threshold value, threshold value is included within the variation range of gate voltage.

In the present embodiment, can also make the threshold value of consecutive storage unit after implementing to write, and the threshold value unanimity of consecutive storage unit when being in erase status, for example says and unify for reading judgment threshold.

Below with reference to Fig. 8 and Fig. 9, the data write activity as present embodiment is described.Here, the memory cell block that implementation data writes, for can be by for example wiping electronics on the electric charge accumulation layer 26 or the like known mode, logarithm be executed the memory cell block of wiping factually.The initial value of the data register in the sensor amplifier 46,46 ' is set the data erase state for.And be understood that, by making suitably counter-rotating or the like mode of voltage, can implement counter-rotating to the condition of state " 1 " and " 0 " easily.

Reference number below with reference among Figure 38 describes storage unit.In order to understand explanation easily, only consider that the storage unit M1 ' that is connected with data line BL2a implements the occasion that four Value Datas write here.

At first, the data register in sensor amplifier 46 is read the data among the storage unit M1 with the adjacent data conveyer line BL1a of data conveyer line BL2a.Here, storage unit M1 is formed on and storage unit M1 ' position adjacent place, for belonging to the storage unit of same block, by this action, the while is sense data conveyer line BL1x (x=a, b, c also ... k) data in the storage unit (SE120).At this moment, the threshold value that sense data is judged, can be for higher than the upper threshold of state " 11 " and than the low threshold values of threshold value lower limit of state " 10 ", and preferably be taken as the threshold values at only about half of place between the threshold value lower limit of the upper threshold of state " 11 " and state " 10 ", be easy to guarantee safety coefficient most.Read action by this, can be with the state of reading of storage unit, promptly whether be state " 10 ", " 00 " or state " 01 ", be stored in the data register place that is arranged in sensor amplifier 46 '.

Then connecting line I/O is energized to after the voltage vcc in advance, makes the transistor Qxa that belongs in the sensor amplifier 46 of cutting apart page or leaf be in conducting state (ON), it is threshold voltage (SE121) that the voltage of judgement connecting line I/O is for example established Vcc/2.At this moment, occasion when being erase status " 11 " to belonging to whole bits of cutting apart page or leaf in the memory cell array 1, then connecting line I/O is output as current potential " H ", is Vcc, even when a storage unit has write state, then connecting line I/O is output as current potential " L ", even, also can implement apace to judge so do not investigate the state of sensor amplifier one by one.

Subsequently, be in the occasion of erase status belonging to whole bits of cutting apart page or leaf,, and continue storage unit M1 ' is implemented write operation because consecutive storage unit M1 is a write state not.In other words be exactly, after the page register of sensor amplifier 46 is in the initial value of erase status, will writes data and be sent to purpose by external connection line I/O and cut apart page register 46 places (SE132), and implement write operation (SE133).

On the other hand,, become consecutive storage unit M1 is implemented the state that antecedent writes when belonging to the bit write state of cutting apart page or leaf record useful.For this occasion, a page data that belongs to storage unit M1 is implemented to read (SE122), and after temporarily transmitting by for example data inputoutput buffer 45 and being stored to temporary storage device 1 (SE123), a page data that belongs to storage unit M1 ' is implemented to read (SE124), and temporarily transmit and be stored to temporary storage device 2 places by for example data inputoutput buffer 45.

Subsequently, to storage unit M1 with wipe a little less than the storage unit on the data select line that storage unit M1 ' is connected is all implemented, reduce its threshold value (SE126), storage unit M1 is changed to the distribution shown in solid line by the distribution shown in the dot-and-dash line among Fig. 9.The slippage of this threshold value is the also big value of threshold value increase maximal value than consecutive storage unit.If for instance, as the weak erase mode among the SE126, can make with storage unit M1 and remain 0V with the data select line that storage unit M1 ' is connected, another data select line is in float (floating) state, and can make the trap that forms memory cell array 1 usefulness by making voltage rise to the mode of 5V between (s) to 1 second to 20V in 10 microseconds (μ s).

For cutting apart page or leaf accordingly, the data in the temporary storage device 2 with to write the data fetch logic long-pending, and are stored in (SE127) in the temporary storage device 2.At this moment, for the non-page or leaf of cutting apart accordingly, then still adopt the data in the temporary storage device 1.

Subsequently, with the data in the temporary storage device 2, be sent to behind the register place in the sensor amplifier 46 (SE128),, implement to append write operation (SE129) for the page or leaf that belongs to storage unit M1 ' by data inputoutput buffer 45.Here, Fig. 9 represents it is when writing data and being four Value Datas, the threshold distribution of storage unit M1.Before the program of SE129, be the threshold distribution shown in solid line among the figure, after SE129,, capacitive coupling partly rises owing to making threshold value, be as the threshold distribution dotted line among Figure 49, that the dispersion of distribution is wideer.In the present embodiment, can pass through data inputoutput buffer 45 subsequently, to implementing to transmit (SE130) by the data that temporarily are stored in storage unit M1 in the temporary storage device 1, that comprise one page at SE123, and can be by the data among the storage unit M1 are implemented to append the mode that verification writes, shown in the dot-and-dash line among Fig. 9, make the maximal value of threshold distribution width keep certain substantially and minimum rises, thereby can reduce the dispersion of distribution (SE131).Adopt aforesaid this mode, can make threshold distribution be substantially equal to the threshold value of consecutive storage unit when being in erase status, write threshold distribution after the consecutive storage unit and equal the threshold values that writes substantially.

Adopt this mode, the dispersion of distribution of threshold distribution in the time of can increasing write state, and as make and read decision threshold and write mark according to antecedent and change, also can guarantee the voltage security coefficient of threshold value.Here, the SE129 program makes the changes of threshold amount of storage unit, is changed to state " 01 " by state " 11 " always.Particularly for erase status " 11 ", owing to the variation of the sensor amplifier minus side threshold determination of using in the positive threshold value of mensuration because of operating point is difficult to measure, so need be extended to more than the 2V.Therefore, changes of threshold amount by state " 11 " during to state " 01 " is quite big, be 4V, in contrast to this, can the changes of threshold amount of storage unit be decreased to write about the threshold distribution width by the SE131 program (＜0.5V 〉, so the influence that SE131 rises to storage unit M1 ' threshold value is decreased to formerly below the 0.5V/4V of technology example～0.125 times, promptly it can be suppressed to very little value.

Certainly, Biao Shi

temporary storage device

1,2 here also can be arranged on the outside of semiconductor storage, also can be formed in the data register within the amplifying circuit 46 read of data line (I/O).But be formed on the data register within the amplifying circuit 46 read of data line (I/O), can reduce the electric power that data transmit needed time and the required consumption of driving data lines I/O.

Reading of present embodiment moved with formerly technical examples is identical, so omitted the detailed description to them here.

Aforesaidly read, write operation, not only can be applied to consecutive storage unit be line direction, promptly to storage unit M1, occasion for storage unit M1, also can be applied to consecutive storage unit and be column direction, promptly to the occasion of storage unit M1 ' for storage unit M0 and M2, can be with the storage unit M1 part in the said write order, be rewritten as storage unit M0 ' or storage unit M2 ', with data line BL2x replace with data line WL1, data line BL1x replaces with data line WL0 or WL2.

And in the present embodiment, owing to detect the write state of each consecutive storage unit for block, thus the write sequence of each block is implemented to set arbitrarily, and can implement to revise to threshold value.

Second embodiment also has advantage as follows except having the advantage identical with first embodiment.

1. can all implement verification and write the data that write in the consecutive storage unit in the present embodiment.Even therefore after consecutive storage unit is implemented to write, also can make the threshold distribution width remain smaller value.

2. can there be no datat to write in the present embodiment, makes and read judgment threshold and remain certain value according to consecutive storage unit.Therefore, can implement read operation with the same high speed of the example of technology formerly.

3. do not need to be provided with memory cell array in the present embodiment, so can further dwindle circuit area as the write sequence storage of using among first embodiment and the 3rd embodiment as described later.

4. compare with as described later the 3rd embodiment, present embodiment can also be applied to the occasion of storage two Value Datas in the storage unit.

Certainly, with the circuit formation of present embodiment, SE122～SE131 is implemented replacement, thereby can obtain to use the formation of reading process flow diagram as shown in Figure 5 with SE10～SE15.

And constitute with the circuit of first embodiment, SE10 and SE122～SE131 are implemented to replace, also obtain and the identical formation of technical examples formerly, for this occasion, the advantage of the formation aspect advantage with circuit formation aspect respectively is identical, and for the advantage of reading, write the aspect, identical with the advantage of utilizing program description to cross respectively.

(the 3rd embodiment)

Figure 10 represents the schematic block diagram used as third embodiment of the invention.

Present embodiment is identical substantially with first embodiment, only is the form of the composition that the second voltage Vref produces circuit (41e), and writes with the read routine and first embodiment different.And in the present embodiment, need that no longer reading after cutting apart amplified the selection signal and be applied to column decoder 48 places, thereby can select signal apply to reading to amplify in the lump by verification control circuit 4.And, in the present embodiment with first embodiment, second embodiment in identical part, and identical voltage relationship all is denoted by like references, so omitted the detailed description to them here.

In the present embodiment, be a plurality of threshold values that in a storage unit, store more than two values, such as be four value threshold values that two bits that are stored together are implemented writing of each bit while can implement verification with respect to consecutive storage unit.Adopt this mode, can also implement compensation the changes of threshold that the consecutive storage unit capacitive coupling produces.And in the present embodiment, a kind of concrete form of the composition of reading amplifying circuit 46 is disclosed also.

Figure 11 represents a circuit block example as the sensor amplifier 46 of the 3rd embodiment.

As shown in Figure 11, but this sensor amplifier 46 is selected charging and discharge circuit mainly by data register R1, the R2 of data regeneration, and data register TR1 and data register TR3 constitute.Here, but data register R1, R2 by data regeneration have two voltage stable point at least, so be a kind ofly the voltage of at least one voltage stable point can be applied to input and output voltage node place, and have the Voltage Feedback that makes described input and output node place data register to described voltage stable point function.This data register can also be made of the flip-flop circuit that phase inverter shown in Figure 12 A～Figure 12 E, that be the reverse form that is connected in parallel constitutes.But also be formed with the voltage node N3 that forms data input, output usefulness at the data register R1 place of data regeneration.Also can form the voltage node N4 of the counter-rotating output of forming voltage node N3.And data register R1 keeps the signal Ф 7 of usefulness to be connected with control data.The input of data register TR3, lead-out terminal are connected with data register R1, and are applied with the data output control signal Ф 5 of data register TR3.For the sub occasion of separating of the data input pin of data register TR3, also can apply data retentive control signal Ф 6 with lead-out terminal.

Aforesaid voltage node N3 and selects charging and selects an input/output terminal in the discharge circuit to be connected.Select charging and select discharge circuit to be connected, so that the data of voltage node N3 can be remained on data register TR1 place with data register TR1.The signal Ф 4 that uses as data retentive control signal, and, be applied to data register TR1 place as the signal Ф 3 of the data output control signal of data register TR1.Can utilize the maintenance data among the data register TR1, control is implemented in the selection charging of voltage node N2.Here, charging, discharge switching signal Ф 2, and to the signal Ф 10 that voltage node N2, voltage node N3 implement conducting, non-conduction control usefulness, be applied to and select charging and select the discharge circuit place.By making the mode of signal Ф 2 counter-rotatings, can also utilize the maintenance data among the data register TR1, control is implemented in the selection discharge of voltage node N2.

By voltage node N2 logarithm reportedly line sending BL1, BL2 implement the transistor Q3 of charging usefulness, and the signal Ф 11 of control usefulness is implemented in charging, N2 is connected with voltage node.Voltage node N2 also is connected with some data conveyer line BL1, BL2 by transistor Q1, Q2.At transistor Q1, the Q2 of Figure 11 be and as shown in Figure 2 transistor Q1x, Q2x (x=a, b, c ... k) identical transistor.The bar number of the data conveyer line that is connected with voltage node N2 in order to prevent can be some along data select line direction adjacent memory unit capacitive coupling influence, yet is considered to be preferably 2 from the angle of geocoding ⁱ(i is a positive integer) is individual.

Voltage node N2 also is connected with voltage node N1 by transistor Q5.Transistor Q5 is connected with the signal Ф 9 that its conducting of control is used.And voltage node N2 also has by making the register that is connected with control line sel1, sel2, signal Ф 9, Ф 11, Ф 13, Ф 3 be in the mode of blocking state, and the data that are floating state are implemented the function of the data register TR2 of storage temporarily.Have the good data retention performance in order to guarantee bigger electric capacity, can also be connected with electric capacity at voltage node N2 place be the capacitor C1 of 0.01 picofarad (pF) to 10 picofarads (pF).

But the input and output terminal on the data register R2 of voltage node N1 and implementation data regeneration is connected.Voltage node N1 also is connected with shared data line I/O by transistor Q4.This transistor Q4 and as shown in Figure 2 transistor Qxa (x=a, b, c ... k) identical, its shared data line I/O extends along the data select line direction, and is shared by a plurality of amplifying circuits of reading.In aforesaid circuit, signal Ф 2～Ф 7, signal Ф 9～Ф 11, control line sel1, sel2 are extended along the direction of data select line, and share by a plurality of

sensor amplifiers

46,46 '.Adopt this form of the composition, can reduce a plurality of sensor amplifiers 46,46 ' are implemented the line number signal of control usefulness, and then reduce wiring to reduce circuit area.The input signal Ф 1 of transistor Q4 also is connected with column decoder.

Figure 12 A～Figure 12 E shows a kind of concrete form of the composition of data register R1 and R2.In the following description, expression signal Ф 7 is changed to the occasion of current potential " H " data of voltage node N3 is implemented to keep by current potential " L ", and during current potential " H ", continue to keep the example of these data, yet it is self-evident, by adopting the appropriate signals circuit for reversing and with the mode of p transistor npn npn replacement n transistor npn npn, can be formed in when being changed to current potential " L " example of can logarithm executing maintenance factually easily by current potential " H ".Below in the explanation to reverse signal, be used in and add oblique line "/" expression before the signal name.

And in Figure 12 A～Figure 12 E, data register R2 can also replace voltage node N3 with voltage node N1, replaces signal Ф 7 with signal Ф 8.These are that reverse being connected in parallel of phase inverter formed flip-flop circuit, in Figure 12 A, by with signal Ф 7 as the SAP input signal, with the reverse signal of signal Ф 7 mode as the SAN input signal, implementation data latchs.In the example that makes with complementary metal oxide semiconductor (CMOS) (CMOS) phase inverter of Figure 12 A, can reduce transistor size to greatest extent, to reduce circuit area.

At the formation example shown in Figure 12 B is the example that uses the piece phase inverter in the voltage node N3 of phase inverter side, and it is compared with constitute example shown in Figure 12 A, has two following advantages.

1. because Ф 7 can be only implemented charging to the gate capacitance of Ф 11 and Ф 10,, and then can adopt thinner signal wire to implement floor plan so can reduce drive signal line Ф 7 needed electric currents.And, the input of Ф 7 and grid is connected, and not with form the source/drain that curtage exports and be connected, so the potential change of the sensor amplifier that is being connected in parallel with Ф 7, can not be passed to other sensor amplifier places, thereby can realize stably moving by Ф 7.

2. by making Ф 7 be in the mode of current potential " L ", can make voltage node N3 be in floating state, and not change, thereby can implement latch the value of voltage node N3 with the voltage of voltage node N4.

And, formation example shown in Figure 12 C, except the advantage of Figure 12 B 1., also has following advantage, because the transistor Q11, the Q12 that are connected with Ф 7 constitute by N NMOS N-channel MOS N (NMOS), thereby can constitute sensor amplifier with the littler area of the bigger P-channel metal-oxide-semiconductor of specific area (PMOS) transistor area.And be the occasion of current potential " L " for signal Ф 7, can block flowing to the direct current that earth point (GND) locates by the Vcc place and run through electric current, thereby can reduce power consumption.

Figure 12 D is except the advantage of Figure 12 B, and Ф 7 ' also can be the signal identical with Ф 7.If make the signal of Ф 7 ' high more Zao than Ф 7 to the rising of current potential " H " by current potential " L ", then voltage node N3 at first is in floating state, thereby can import data to it implements to latch, in contrast, if the signal of Ф 7 by current potential " L " to the rising of current potential " H " morning than signal Ф 7 ', then voltage node N4 at first is in floating state, thereby can implement to latch to the input data of voltage node N4.Because sort circuit can be implemented input operation when voltage node N3 or voltage node N4 are in floating state, so, the data stabilization among the data register TR3 is restored if adopt formation example shown in Figure 13 A, Figure 13 H～Figure 13 K.And make Ф 7 and Ф 7 ' be the occasion of current potential " L ", can also block flowing to the direct current that earth point (GND) locates by the Vcc place and run through electric current, thereby can reduce power consumption.

Figure 12 E makes Ф 7 be the occasion of current potential " L " except the advantage of Figure 12 B, and blocking-up flows to the direct current that earth point (GND) locates by the Vcc place and runs through electric current, thereby can reduce power consumption.

Complementary metal oxide semiconductor (CMOS) (CMOS) phase inverter of routine word represent to use to(for) data register R1, R2, yet can also use electric erazable programmable type (EE) phase inverter that forms by N NMOS N-channel MOS N (NMOS) and form with the phase inverter of the high impedance load of replacing P-channel metal-oxide-semiconductor (PMOS), device action mode with this form of the composition is similar, so omitted the detailed description to them.

Figure 13 A～Figure 13 K represents the concrete formation example of of data register TR3.In the following description, implementation data kept when expression signal Ф 6 was changed to current potential " L " by current potential " H ", and during current potential " L ", continue to keep the example of these data, yet it is self-evident, by the mode that adopts the appropriate signals circuit for reversing and replace the n transistor npn npn with the p transistor npn npn, also can constitute easily can implementation data maintenance when being changed to current potential " L " by current potential " H " example.In the following description, expression is to be in floating state during the current potential " L " with Ф 5, the example of implementation data output during being current potential " H ", yet it is self-evident, by the mode that adopts the appropriate signals circuit for reversing and replace the n transistor npn npn, also can be formed in the example that implementation data is exported when being changed to current potential " L " by current potential " H " easily with the p transistor npn npn.

Formation example shown in Figure 13 A～Figure 13 C is the data holding circuit identical with dynamic storage, and Ф 5 and Ф 6 share.Just as shown in the drawing, current potential V1 represents to form the voltage node of the voltage between being located by Vdd place to earth point (GND).Can keep data with this circuit as the capacitor C2 quantity of electric charge.These can use line number signal and few, the littler area forming circuit of composed component number.

Formation example shown in Figure 13 D～Figure 13 K is to get to be stored in the quantity of electric charge that transistor Q7 goes up the gate electrode place as data, its counter-rotating output is implemented the circuit of output by transistor Q17, transistor Q18.Just as shown in the drawing, current potential V1 represents to form the voltage node that for example constitutes earth point (GND).By adopting the sort circuit form of the composition, the input and output of data are separated, do not destroy thereby can not read to produce, no longer need to destroy the data register of implementing to restore usefulness, and can easily regularly implement to adjust input and output to reading to data.And, even keeping data is the occasion signal charge disappearance of current potential " H ", remain on the threshold value of transistor Q17 as node the gate electrode of transistor Q17, when Ф 5 being implemented to read when current potential " H ", can make output node and node V1 remain on conducting state, and then can obtain bigger signals security coefficient.

But can adopt the data register circuit of the implementation data regeneration shown in Figure 12 A～Figure 12 E to constitute for data register TR3, yet when the circuit of employing shown in Figure 13 A～Figure 13 C constitutes, the transistor formed number can be decreased to below three, power lead also can be with of V1, so can produce littler circuit.

Figure 14 A～Figure 14 F represents to select to charge and selects discharge circuit and data register TR1, promptly selects that of charge/discharge circuit 10 is concrete to constitute example.Following table is shown in Ф 4 and Ф 12 is kept by the occasion implementation data that current potential " H " is changed to current potential " L ", and during current potential " L ", continue to keep these data example, yet it is self-evident, by the mode that adopts the appropriate signals circuit for reversing and replace the n transistor npn npn, can also be formed in the example of implementation data maintenance when being changed to current potential " L " easily by current potential " H " with the p transistor npn npn.Following table is shown in Ф 3 and is being in floating state for during the current potential " L ", the example of the occasion of implementation data output during current potential " H ", yet it is self-evident, by the mode that adopts the appropriate signals circuit for reversing and replace the n transistor npn npn, also can be formed in the example that implementation data is exported when being changed to current potential " L " by current potential " H " easily with the p transistor npn npn.And be illustrated in Ф 2 for during the current potential " L " voltage node N2 being implemented to select to discharge, voltage node N2 is implemented to select during Ф 2 is current potential " H " occasion of charging.Here, as Ф 3, because the slippage of the threshold value Vth of transistor Q20 is reduced, and the current potential of voltage node N2 is charged to Vcc-Vth always, be more than the Vcc+Vth so be preferably in signal Ф 3 for making voltage under the occasion of current potential " H ".

For Ф 10, Ф 3, Ф 4, can also be by the mode that adopts the appropriate signals circuit for reversing and replace the n transistor npn npn with the p transistor npn npn, be formed in the example of implementation data maintenance when being changed to current potential " L " easily by current potential " H ".

Sort circuit at first considers to make Ф 3, Ф 4, Ф 10, Ф 12, Ф 13, Ф 14 to be in the original state of " L ".Connecting line VBL is in Vcc.At Ф 4 places that constitute shown in Figure 14 A～Figure 14 D in the example, and constitute the pulse that Ф 4 in the example and Ф 14 places apply " H " shown in Figure 14 E, Figure 14 F, with the data transfer at the voltage node N3 place gate electrode place to the transistor Q21 subsequently, make Ф 4 and Ф 14 be in current potential " L ".Ф 12 places in the formation example shown in Figure 14 C and Figure 14 D, and constitute the pulse that Ф 4 in the example and Ф 13 places are applied for current potential " H " shown in Figure 14 F, so that with the irrelevant condition of the current potential of voltage node N3 under, with the data transfer at voltage node N2 place gate electrode place to transistor Q21.Subsequently, make Ф 12 and Ф 13 be in current potential " L ".Then, by transistor Q3 voltage node N2 is charged to after the Vcc, transistor Q3 conducting makes Ф 10 be in current potential " L ", thereby makes voltage node N2 be in floating state, makes data register TR2 be in the data hold mode.By making Ф 10 be fixed on current potential " L ", make Ф 2 be fixed on 0V or Vcc, make Ф 3 be changed to the mode of current potential " H " by current potential " L ", can be with the quantity of electric charge that remains on transistor Q21 gate electrode as data, and voltage node N2 is implemented charging, discharge operation according to these data.This move is called as to be selected charging and selects discharge.

What Figure 15 A and Figure 15 B represented respectively is the logical diagram that the sort circuit selection is charged and moved when moving and selecting to discharge.The output that is illustrated in voltage node N2 by the cingens part of thick line obtains being stored in the counter-rotating of the primary data at transistor Q21 gate electrode place.I.e. expression is by implementing to select discharging action, at the data reversal signal of program acquisition shown in Figure 16.And, in program shown in Figure 16, such as described in the first embodiment, determine the occasion of the logical value sequence number of four value threshold values at the use Gray code, threshold value is followed successively by " 11 ", " 10 ", " 00 ", " 01 " by low order, so need be to implementing counter-rotating in proper order as " 0 " of position, back bit, the threshold value of " 1 ".By adopting selection discharge circuit as present embodiment, can constitute with very simple circuit, 46 high speeds are carried out the counter-rotating that formerly technical examples was difficult to realize in sensor amplifier.Therefore, the data inputoutput buffer 45 that can reduce by implementation data counter-rotating usefulness transmits the needed time towards the external buffer implementation data, and can reduce the needed power consumption of driving data lines I/O.

Be understood that by top explanation, can utilize and select charge/discharge circuit 10, the data of voltage node N2 or voltage node N3 are remained on gate electrode place on the transistor Q21, and can implement to select charging and discharge to node N2 according to these data.And, can be by Ф 4 places in shown in Figure 14 A～Figure 14 D, constituting example, and shown in Figure 14 E, Figure 14 F, constitute the mode that Ф 4 in the example and Ф 14 places are applied for the pulse of current potential " H ", make between node N2 and node N3 to be in conducting state.

Below for simplicity, only the action form of component number selection charge/discharge circuit 10 minimum, shown in Figure 14 A is described.Figure 14 B can realize the circuit operation identical with Figure 14 A.Figure 14 C and Figure 14 D are owing to the circuit that includes shown in Figure 14 A and Figure 14 B, so be understood that they can realize same action when signal Ф 12 is in current potential " L ".Figure 14 E, Figure 14 F are because Ф 14 is in current potential " H " usually, so when Ф 13 places apply the signal identical with Ф 10 places, can realize same action.

Figure 17 represents then, the data content of data register R1 and R2 is implemented a program example of exchange.In the following description, though so-called data reproduction represent to be applied to the input and output node by the voltage that a stable point will change on a small quantity, also with the Voltage Feedback at described input and output node place to described stable point place, the logical signal amplitude is restored.Realize with R1 and R2 in the present embodiment.For adopting data register circuit shown in Figure 13 A～Figure 13 K and shown in Figure 14 A～Figure 14 F, because the supply voltage node has only one, so can not implement regeneration to two-value data.As Figure 16 and program shown in Figure 17, can under the state that the maintenance data of data register TR3 is not all produced destruction, implement.

Use the performance that recovers to the data of so-called data register R1 by data register TR3 below, but this means the occasion that makes the voltage of output logic amplitude voltage decline in data register TR3 output owing to charge leakage and array noise or the like, utilize the regeneration of data register R1 implementation data, data are remained on data register R1 place.This is for example to instigate that Ф 7 is in current potential " L " and is in the state that data are read, and is in " H " afterwards at Ф 5, can be changed to the mode of current potential " H " by current potential " L " by making Ф 7, the data of data register TR3 is implemented to keep the program of usefulness.By the data transmission expression such order of data register R1 to data register TR3 place, promptly be in the data hold mode, be that Ф 7 is under current potential " H " state at data register R1, by Ф 6 is transmitted by the mode that current potential " L " is changed to current potential " H ", subsequently by making signal Ф 6 be changed to current potential " L ", at data register R1 storage and data register TR3 independent data by current potential " H ".And, so-called by the data transmission of data register R1 to data register TR1 place, can implement by following order, at first be in the data hold mode at data register R1, be that Ф 7 is under the state of current potential " H ", make Ф 4 be changed to current potential " H " by current potential " L ", the current potential that makes data register TR1 is with after the output potential of data register R1 equates, make Ф 4 be changed to current potential " L " by current potential " H ", and it is so-called by the data transmission of data register R1 to data register TR2 place, can implement by following order, at first be in the data hold mode at data register R1, be that Ф 7 is under the state of current potential " H ", make Ф 10 be changed to current potential " H " by current potential " L ", the current potential that makes data register TR2 is with after the output potential of data register R1 equates, make Ф 7 be changed to current potential " L " by current potential " H ", so-called by the data transmission of data register TR2 to data register R1 place, can implement by following order, at first make data register R1 be in data and read state, be that Ф 7 is under the state of current potential " L ", make Ф 10 be changed to current potential " H " by current potential " L ", the data at data register TR2 place are sent to voltage node N3 place, make Ф 7 be changed to current potential " H " subsequently, and be in the data hold mode by current potential " L ".

Below with reference to Figure 18 and Figure 19, describe read action as the data of present embodiment.

In the present embodiment, be a plurality of threshold values that in a storage unit, store more than two values, such as be four value threshold values, be stored in two bits of one, while can implement the write operation that each bit is implemented in verification at consecutive storage unit.Therefore as shown in Figure 19, after implementing to wipe processing, the data (first bit) of the logical address circuit 1 of block will be write at first, be stored in accordingly in two adjacent unit with two values of state " 11 " and state " 00 ", simultaneously the correspondence graph of physical address and logical address implemented storage.Subsequently, for the occasion that data (second bit) need be write to logical address circuit 2 places, need implement to append to write in the threshold value of described storage unit, be about to " 11 " and " 00 " interdependent appended bits ground as the data of being write as " 11 " and " 10 ", " 00 " and " 01 " four values respectively.In order to understand explanation easily, suppose four Value Datas below, in two bits of write-once, the data definition that will implement at storage unit k1 place to write is position, back bit, and the data definition that will implement at storage unit k2 place to write is the anteposition bit.In the 3rd embodiment, can also set the data content in the memory cell array 7 of write sequence storage, so that write fashionable " 11 " (not the writing) that be, write fashionable " 00 " (the writing) that be at logic array 2 antecedents at logic array 1 antecedent.To implement below that the address table after the conversion is shown adda between described physical address and logical address.The mark that these logical addresses rewrite, can be with unit planar configuration shown in Figure 2, the mode similar with first embodiment realizes, if value " 11 " and " 00 " in the storage two-value data are sufficient, cut apart the data of page or leaf and the storage unit of the data of row writes simultaneously, reads and wipes with storage is same, this is clearly.Constitute with the element circuit identical, form the expression piece and wipe the mark (initially writing mark) whether processing implements write state afterwards with the logical address overwrite flags.Set like this, being about to wipe consecutive storage unit in the corresponding block in back, all not implement the occasion of write operation be state " 11 " (not writing), and the occasion of at least one storage unit wherein having been implemented write operation is that state " 00 " writes).If these marks are distributed to the memory cell array 7 that logical address overwrite flags and position, back bit are read simultaneously, and to initially writing the memory cell array 7 that mark and anteposition bit are read simultaneously, just can use and memory cell array 1 identical formation, only increase a data conveyer line and promptly can implement storage the information of a block, and no longer need new storage unit and wiring, thereby can make circuit area smaller.

To the reading, write and the timing of checkout action of data one by one, can be by for example open, so just omit by Japanese kokai publication hei 7-182886 number (U.S. Pat 5452249).In the present embodiment, owing to data register R1 being used as reading to amplify to move, to select charge/discharge circuit 10 to be used for checkout action, so read action and the content of data register R1, data register TR2 produced destroy by data, content by checkout action to data register TR1 produces destruction, destroys but can not produce the data content at data register TR3 and data register R2 place.

Storage unit k1 and k2 by Figure 18 to Figure 27 are adjacent memory unit, and expression is one the 2 bits storage unit of per 1 bit storage respectively, and adjacent direction can be line direction, also can be column direction.

By the program shown in the SE21 of Figure 18,, the data among the storage unit k1 are implemented to read according to the threshold decision value that is positioned between threshold value " 11 " and " 10 ".At this moment, sense data is judged the threshold value of usefulness, can be as shown in figure 19, can be than state " 11 " upper threshold height and than the low threshold values of state " 10 " threshold value lower limit, and preferably be taken as the value at state " 11 " upper threshold and state " 10 " the only about half of place of upper threshold, so that can guarantee maximum safety coefficient easily.Therefore, this result has the occasion of the threshold value higher than judgment threshold in storage unit, and current potential " H " is remained on data register R1 place, has the occasion of the threshold value lower than judgment threshold in storage unit, with current potential " L ", remains on data register R1 place.

Subsequently, by reading " different " that amplifying circuit 46 ' or control circuit 40 generate and read logical address adda.To sort circuit be described by Figure 29 below.Adopt this form of the composition, can be in erase status at storage unit k1, k2, with logical address 1 is implemented antecedent and is write that fashionable to read the address be 1 occasion and logical address 2 is implemented antecedents to write the fashionable address of reading be 2 occasion, then its " different " is " 1 " (current potential " L "), thereby " 11 " in four values, " 10 " can be read as " 1 ", " 00 " or " 01 " conduct " 0 " is read.Can utilize the program of SE30 and SE31, storage unit k2 is then carried out threshold determination between " 00 " and " 01 " to storage unit k1, this just easily carries out.In contrast, to logical address 1 implement that antecedent writes the time to read the address be 2 occasion and logical end electronic circuit 2 is implemented antecedents to write the fashionable address of reading be 1 occasion, then its " different " is " 0 " (current potential " H "), thereby " 11 " in four values, " 01 " can be read as " 1 ", " 10 " or " 00 " conducts " 0 " are read.At this moment the threshold value of " 10 " and " 00 " is for being positioned at the threshold value between " 11 " and " 01 " threshold values, so can the data of reading be remained on data register TR2 place at SE21, at SE24 the data of reading are remained on data register TR1 place, represent by selecting discharge as SE25 subsequently, can be occasion taking-up " 1 " current potential " L " of " 11 " or " 01 " at data register TR2), take out " H " in the occasion of " 10 " or " 00 ".SE21, SE24, SE25 are the programs of storage unit k1 implementation data being read usefulness, SE26～SE28 is the similar program of storage unit k2 implementation data being read usefulness, these data can be remained on data register R1, R2 place, and can export connecting line I/O place to by transistor Q4 successively.

Here, the data of data register R2 output and be at transistor Q5 under the state of blocking-up by the program of SE26 to SE27 in by SE25 can be carried out simultaneously, therefore can reduce to external data and read the needed time.Special needs to be pointed out is, read the needed time (period) when data and be tR, data export the outside needed time to when being tt2, can be (4 * tR+1 * tt2) or greater than (time of 2 * tR+2 * tt2) reads with maximum time in a piece is read.

Below with reference to Figure 20～Figure 27, the data write sequence as present embodiment is described.

At first, will write data and be sent to data register TR3 and data register R2 place (SE32) at SE32.Imagine the occasion that in storage unit, has write data in the following description, so, will be called in the data that SE32 transmits to append and write data in order to make word clearer.Like this, just can be different with first embodiment, second embodiment, when beginning, the write activity program implements to transmit to writing data, begin to the time of data transmission thereby can shorten by write activity.By SE33, SE33 ', SE34 and SE35, make wipe after data be the occasion of initial value, with implementing to write the fashionable logical address that writes data of appending in logical address 1 than logical address 2 antecedents is 1 occasion, to write the address of reading of the fashionable logical address that writes data be 2 occasion with implement antecedents in logical address 2, and then different is " 1 " (current potential " L ").At this moment, data line can be divided into two groups of k1 and k2 in a word, and with " 0 " conduct " 00 ", verification implemented in " 1 " conduct " 11 " write.Wherein more detailed procedure is represented at SE36, shown in SE36, can be after consecutive storage unit k1 and k2 implementation data be write, respectively storage unit k1 and k2 enforcement verification are read, and by storage unit k1 and k2 are implemented respectively to write once more, even owing to the electric capacity between consecutive storage unit makes the occasion of changes of threshold, also can implement to revise, reduce to the threshold difference of consecutive storage unit.Particularly after wiping, implement the occasion write, and occasion smaller in the capacitive coupling of adjacent block and that write can ignore the time, having only because of the capacitive coupling between consecutive storage unit makes the unit of changes of threshold is the unit that enforcement writes, by reducing the calibration voltage step-length, the threshold difference correction between consecutive storage unit can also be reduced to the degree of calibration voltage step-length.

Implementing to write the fashionable logical address that writes data of appending in logical address 1 than logical address circuit 2 antecedents is 2 occasion, with antecedent logical address 2 being implemented to write the fashionable address of reading of appending the logical address that writes data is 1 occasion, and then different is " 0 " (current potential " H ").Here, investigation is confirmed corresponding block is initially write the mark of confirming usefulness, in the occasion that is initial write operation, described data line can be divided two groups of k1 and k2, can " 0 " as " 00 ", " 1 " is write as " 11 " enforcement verification.For other occasion, data line is divided into two groups of k1 and k2, in the occasion of the storage unit threshold value of implementing to write for " 11 ", can according to append write data " 0 ", " 1 " and become " 10 ", " 00 " writes, in the occasion of the storage unit threshold value of implementing to write for " 00 ", can write data " 0 ", " 1 " and become " 00 ", " 01 " according to appending, and then write.At this moment, because the data during to " 00 " and " 11 " implement to write, thus will as shown in figure 19, write owing to append to the storage unit adjacent memory unit enforcement of the data of " 00 ", can make the threshold value rising.Yet the threshold value rising value in the technology example formerly, be { (threshold value when consecutive storage unit is " 01 ")-(threshold value when consecutive storage unit is " 11 ") } * (rate constant) to the maximum, be { (threshold value when consecutive storage unit is " 10 ")-(threshold value when consecutive storage unit is " 11 ") } * (rate constant) to the maximum and can be suppressed in the present embodiment.

As from shown in the SE37 to SE42, implement after a secondary data writes at consecutive storage unit k1, storage unit k2 is implemented verification to be write, because the threshold value rising part that SE37 and SE40 produce, can implement to revise with SE38 and SE40, so compare with the occasion that storage unit k1 enforcement verification is write, subsequently storage unit k2 enforcement verification write, can reduce the deviation of threshold value.By using, with the formation of Figure 11, just the threshold value that can suppress to produce owing to the capacitive coupling between consecutive storage unit rises as Figure 20～process flow diagram shown in Figure 27.

And storage unit k1 and k2 owing to be suitable for present embodiment along the column direction adjacent memory unit of inner structure, can further reduce the write error of data than technology formerly as storage unit M0 and M1.Its reason will be described below.Formerly have the storage unit of lowest threshold in the technology, consider that the threshold value of two storage unit adjacent with this storage unit is the occasion of Vthr for " 11 ".When considering that here implementation procedure is handled, make the boost in voltage of the data select line of Vthr threshold value with Vpass, make the data select line of " 11 " threshold value use the voltage Vpgm higher to boost, thereby make the storage unit of " 11 " threshold value remain on non-write state than voltage Vpass.At this moment, be that the storage unit factor of Vthr rises current potential according to the capacitive coupling between selection wire and tunnel current potential in threshold value, proportional to the potential difference (PD) of boosting, promptly proportional after the electric charge that induces with the place, tunnel with (Vpass-Vthr) at Vpass.Therefore, if Vthr rises more, then non-selected storage unit tunnel current potential descends more, when particularly voltage Vthr is formed on state for the storage unit both sides of " 11 " for the storage unit of " 10 " state, if voltage Vpgm is applied to the control line place that threshold value is used for the storage unit of " 11 ", just may produces write error.Corresponding is, utilize the program of one-time continuous that storage unit k1 and k2 are implemented write operation in the present invention, so a storage unit adjacent memory unit threshold value before will writing is suppressed to below 1/2 of technology formerly for the probability of " 01 ", therefore compare with the threshold value wrting method of technology example formerly, also can reduce the mistake that makes the Data Control line when boosting to Vpgm, remain the storage unit of non-write state and write.

Figure 28 represents the integrated circuit figure of the sensor amplifier 46 that present embodiment uses.The difference of this circuit diagram is, the voltage node of data register TR2 is divided into two parts by transistor Q32, article two, the data conveyer line is connected with the data register TR2 that separates respectively, data register R1 place also be formed with and connecting line I/O between implement the transistor Q4 ' that input and output are used, between data register R2 and transistor Q21, be formed with signal Ф 14.At this circuit diagram, if Ф 17 and Ф 18 are in current potential " H ", Ф 3, Ф 4 and Ф 15 are in current potential " L ", Ф 12 and Ф 6 are in current potential " H ", with implementing to drive Ф 14 with Ф 5 identical signals, the signal that Ф 16 and Ф 1 are provided by column decoder is implemented to drive, then come down to for example Japanese kokai publication hei 7-182886 number (U.S. Pat 5452249) disclosed, read that amplifying circuit is connected in parallel and the circuit equivalent that constitutes by two that can implement every bit verification, so can be respectively with respect to data conveyer line BLxa, BLxb (x=1,2), two-value data is implemented to write simultaneously, read and erase operation.

On the other hand, by making Ф 14 and Ф 16 be in current potential " L ", Ф 15 is in current potential " H ", be in current potential " H " along with one among sense data conveyer line signal Ф 17 and the Ф 18, another is in the mode of current potential " L ", can be according to present embodiment with aforesaid four Value Datas, read, write to two numbers reportedly in the line sending, so only can adopt on for example Japanese kokai publication hei 7-182886 number (U.S. Pat 5452249) disclosed formation, add six transistors, be transistor Q32, Q19, Q22, the transistor that is connected with Ф 17, the transistor that is connected with Ф 18, and the mode of transistor Q24, easily constitute a kind of four value N-type semiconductor N memory circuits that can reduce the changes of threshold that produces by the consecutive storage unit capacitive coupling.

In the present embodiment, Figure 29 represents a kind of physical circuit of the sensor amplifier 46 ' that is connected with the memory cell array 7 of write sequence storage.Because the write sequence judged result of present embodiment can utilize data register R1 to read, so as shown in figure 29, output N3 to data register R1, and the N4 that obtains its counter-rotating output, can implement output control by transistor Q40 and Q41 according to the signal that provides by control circuit 40, thereby can form the adda value and " different " that provide by addressing impact damper 47, output is inputed to control circuit 40 places.Like this, read amplifying circuit 46 ' except reading amplifying circuit 46, can also by minimum be that six transistor is realized the output of " different ", thereby can realize the present invention with very little area occupied.And, owing to can adopt the circuit identical to constitute 46 ' with 46, thus can make the timing design of circuit easy, and can except sensor amplifier 46,46 ' middle Ф 1, share control line, thus the wiring area can further be reduced.

The formation of sensor amplifier 46 ' as shown in figure 11 can keep R1, R2 and TR3 implementation data, and can be independently reads data among R1 and the R2 at the I/O line.Here by the illustrated conditional branching of Figure 18～Figure 27, can carry out according to the data that are stored among 46 ' the R1, so except the data input and output of implementing towards connecting line I/O, read amplifying circuit 46 and 46 ' the shared amplification control line of reading, and can be by implementing control by 40 couples of transistor Q40 of control circuit and Q41, utilize and share signal, therefore can reduce the area that timing generation circuit and wiring take reading amplifying circuit 46 and 46 ' enforcement driving.

Present embodiment is illustrated in to be implemented to wipe after the processing, will with the data that write to the logical address circuit 1 in the block at first (first bit), be stored in two examples in the consecutive storage unit accordingly with " 11 " and " 00 " this two value, yet can also adopt shown in Figure 30 A, to write data (first bit) at first is stored in two consecutive storage units accordingly with " 11 " and " 00 " this two value, and make second bit respectively with " 11 " and " 00 ", " 10 " and " 01 " corresponding method, or adopt shown in Figure 30 B, will with write data (first bit) and " 11 " and " 00 " this two value at first and be stored in accordingly in two consecutive storage units, and make second bit respectively with " 11 " and " 01 ", " 10 " and " 00 " corresponding method.And, in Figure 30 A and Figure 30 B, can make the max-thresholds of first bit be " 10 " lower than " 00 ", particularly storage unit k1 and k2 are as storage unit M0 and M1, be along the column direction adjacent memory unit in the NAND structure, by implementing the mode of present embodiment, the mistake that can further reduce data writes.

Figure 19, Figure 30 A and Figure 30 B represent the setting value of judgment threshold and the relation between threshold distribution.For example in Figure 19, " 00 " threshold value is owing to the threshold value that the consecutive storage unit capacitive coupling produces rises to maximum, so threshold values is wideer than the threshold value width of the threshold value of " 10 " and " 01 ".Therefore, can guarantee the threshold value of " 00 " and " 01 " threshold value separate width, than the threshold value of the threshold value of " 10 " and " 00 " to separate width bigger.

And in Figure 30 A and Figure 30 B, the threshold value of " 10 " is owing to the threshold value that the consecutive storage unit capacitive coupling produces rises to maximum, so threshold values is wideer than the threshold value width of the threshold value of " 00 " and " 01 ".Therefore, can guarantee the width that separates between the threshold value of the threshold value of " 10 " and " 00 ", can than between the threshold value of the threshold value of " 00 " and " 01 " to separate width bigger.

If employing present embodiment, at first after all pieces are wiped, after data are written in adda and are 0 storage block, with with described storage block identical address pair and adda quite and data in the different storage block of address bit when implementing to read, no matter how, the data identical with writing data are implemented to read after wiping.Therefore, even do not apply adda, also can after wiping, implement to read to the data of initial record.

And self-evident, present embodiment have first embodiment 2., 4., 6. advantage, and have the advantage that first embodiment and second embodiment are had jointly.

(the 4th embodiment)

Figure 33 A, Figure 33 B represent to constitute as the storage unit in the fourth embodiment of the invention.

Present embodiment adopts the NAND cell block of MONOS type grid, replaces the NAND cell block by the type grid of floating among first, second and the 3rd embodiment.

Schematic cross sectional view shown in Figure 33 A, Figure 33 B, corresponding with the sectional view of line A-A, line B-B on the NAND cell block shown in Figure 32 A, Figure 32 B respectively.Its planimetric map is identical with Figure 31 B, so given omission here.

Shown in Figure 33 A, Figure 33 B, non-volatile memory cells M0～the M15 that is made of as MOS type (MOS type) transistor npn npn of electric charge accumulation layer 26 silicon nitride (SiN) and silicon hydroxide (SION) is implemented to be connected in series, the one end is connected with the data conveyer line that is labeled as BL with transistor S1 by selecting.The other end is connected with the shared source electrode line that is labeled as SL with transistor S2 by selection.Each transistor all is formed on the trap.In Figure 33 A, Figure 33 B, can be 10 in boron impurity concentration ¹⁴Centimetre ^-3(cm ^-3)～10 ¹⁹Centimetre ^-3(cm ^-3) between p type silicon area (semiconductor regions) 23, by for example saying that thickness is the silicon oxide layer of 1 millimicron of (nm)～10 millimicron (nm), or the tunnel gate insulating film that constitutes of oxynitride film, form thickness and be electric charge accumulation layer 26 3 millimicrons of (nm)～50 millimicron (nm), that constitute by silicon nitride (SiN), silicon hydroxide (SION).On this electric charge accumulation layer 26 again by by for example thickness being interlayer dielectric 50 2 millimicrons of (nm)～10 millimicron (nm), that constitute by silicon oxide layer, and then form lit-par-lit structure by for example polysilicon or tungsten silicide (WSi) and polysilicon, or the lit-par-lit structure of nickel silicide (NiSi), molybdenum silicide (MoSi), Titanium silicide (TiSi), cobalt silicide (CoSi) and polysilicon composition, thickness is the control gate 27 of 10 millimicrons of (nm)～500 millimicron (nm).This control gate 27 extends to block edge with consecutive storage unit piece 49 ways of connecting among Figure 31 B along the paper left and right directions always, forms data select line WL0～WL15 and selection gate controls line SSL, GSL.And p type silicon area 23 preferably can pass through n type silicon area 22, applies voltage independently with p type silicon substrate 21, so that the load of booster circuit can reduce to wipe the time, and suppresses the electric power that consumed.Grid shape in the present embodiment, the sidewall of its p type silicon area 23 is being covered by dielectric film 24 lids, so this sidewall can't be owing to corrosion exposes to the open air before forming floating gate electrode 26, this can prevent that gate electrode 26 is formed on the position than p type silicon area 23 downsides.Therefore, be difficult to generate the parasitic transistor that the grid electric field is concentrated, threshold value is low on p type silicon area 23 and dielectric film 24 borders.Owing to the electric field that can not produce is concentrated writing threshold value decline phenomenon, reaching so-called bypass phenomenon, so can form the more transistor of high reliability of producing.

At place, the both sides of this gate electrode, also being formed with clamping, by thickness be the silicon nitride film of 5 millimicrons of (nm)～200 millimicron (nm) or n type diffusion layer 28 side wall insulating film 43, that constitute source electrode or drain electrode that silicon oxide layer constitutes.Utilize this diffusion layer 28, electric charge accumulation layer 26 and control gate 27, can form non-volatile electrically EPROM (Erasable Programmable Read Only Memory) (EEPROM) unit of M-ONO-S type, gate length is 0.5 micron (μ m) with down to more than 0.01 micron (μ m) in the electric charge accumulation layer 26.As the n type diffusion layer 28 that constitutes source electrode or drain electrode, can be 10 according to the surface concentration of its phosphorus, arsenic, antimony ¹⁷Centimetre ^-3(cm ^-3)～10 ²¹Centimetre ^-3(cm ^-3), the degree of depth is that the mode of 10 millimicrons of (nm)～500 millimicron (nm) forms.This n type diffusion layer 28 can be total each other by consecutive storage unit, thereby realize that NAND connects.Reference number 27SSL, 27GSL are respectively the gate electrodes that the piece selection wire suitable with SSL, GSL is connected in the drawings, and are formed on in one deck with control grid electrode in the described MONOS type EEPROM (Electrically Erasable Programmable Read Only Memo) (EEPROM).Gate electrode can be by by for example thickness being gate insulating film 25SSL, the 25GSL that the silicon nitride film of 3 millimicrons of (nm)～15 millimicron (nm) or oxynitride film constitute, and forms MOS type (MOS type) transistor relative with p type silicon area 23.Here, gate electrode length by making gate electrode 27SSL, 27GSL is longer than the gate electrode length of storage unit, such as be 1 micron (μ m) with down to the mode more than 0.02 micron (μ m), can guarantee that piece has bigger conducting, disconnection ratio when selecting with non-selections, read and miss and write so that prevent mistake.

By being formed on the one-sided n type diffusion layer 28d that constitutes source electrode or drain electrode of gate circuit 27SSL, can be connected with the data conveyer line 36 (BL) that for example constitutes by contact 31d by tungsten and tungsten silicide, titanium, titanium nitride or aluminium or the like.Here, the mode of data conveyer line 36 (BL) to be connected with the adjacent memory unit piece in Figure 31 B, is formed up to block boundary along the paper above-below direction always.On the other hand, by being formed on the one-sided n type diffusion layer 28S that constitutes source electrode or drain electrode of 27SSL, can be connected with the source electrode line that is labeled as SL by contact 31s.This source electrode line SL in 31B, always is formed up to block boundary along the paper left and right directions with adjacent memory unit piece ways of connecting.Certainly, be formed up to block boundary along the paper left and right directions always, also can form source electrode line by making n type diffusion layer 28S.Be labeled as here BL contact, be labeled as the contact of SL, for example can use conductive material, and these conductive materials are packed into contact hole and the electric conductor zone that constitutes at the polysilicon of n type or the coating of p type and tungsten, tungsten silicide, aluminium (Al), titanium nitride (TiN), titanium (Ti) or the like.And, between these contacts BL, contact SL and described transistor, also can use for example by silicon dioxide (SIO ₂) and the interlayer dielectric 28 that constitutes of silicon nitride (SiN) fill.And the place, top at contact BL is formed with by for example silicon dioxide (SIO ₂), the dielectric film protective seam 37 that constitutes of silicon nitride (SiN) or polysilicon or the like, and not shown, by the upper wiring of for example tungsten (W), aluminium (Al) and copper (Cu) or the like formation.

If employing present embodiment, except the advantage that floating grid type storage unit is had shown in Figure 32 A and Figure 32 B, owing to use MONOS type storage unit, so can also further make than floating grid type EEPROM (Electrically Erasable Programmable Read Only Memo) (EEPROM) and write voltage, erasing voltage lower voltage, even, also can keep needed resistance to pressure in order to make the element separation spacing narrow and make thick gate insulating film thinner.Therefore, can apply high voltage with the minimizing circuit area, thereby can further dwindle chip area.

And compare with floating grid type storage unit, owing to the thickness of electric charge accumulation layer 26 can be decreased to for example below 20 millimicrons (nm), so flat shape in the time of can further dwindling grid formation, improve the machining shape of gate electrode, and then can improve the amount of being embedded between interlayer dielectric 28 grid, further improve its resistance to pressure.And, owing to no longer need to form the operation that gate electrode uses and make the operation that narrow slit is used, so can further shorten production process.And electric charge accumulation layer 26 is insulators, can be with charge-trapping to one by one charge trap place, and institute is so that electric charge is difficult to come off with respect to radioactive ray, thereby can have stronger resistance to pressure.And, even make side wall insulating film 43 filmings of electric charge accumulation layer 26, the electric charge that is captured to electric charge accumulation layer 26 place is all escaped, so can have good charge-retention property.Because electric charge accumulation layer 26 is according to cooperate the mode of not having skew to form with p type silicon area 23, so can further make the electric capacity homogenising of electric charge accumulation layer 26 and p type silicon area 23.Adopt this form of the composition, can also reduce deviation between memory cell capacitor and the capacitance deviation between storage unit.

And the storage unit in the semiconductor storage of aforesaid first, second and the 3rd embodiment also can not be floating grid type storage unit, but adopts the MONOS type storage unit by the present embodiment explanation.

(the 5th embodiment)

Figure 34 A～Figure 34 D represents the storage unit structure of fifth embodiment of the invention.

Present embodiment adopts the AND memory cell block, replaces the NAND memory cell block 49 among first～the 4th embodiment.And with identical part among first～the 4th embodiment, and identical voltage relationship all is denoted by like references, and omitted detailed description.

Figure 34 A is the circuit diagram with 49 and 49 ' the corresponding AND memory cell block.The AND cell block 49 of the expression of 49 among Figure 34 A storage data, non-volatile memory cells M0～the M15 that constitutes with the MOS type with floating grid (MOS type) transistor is connected in parallel, and the one end is also by selecting transistor S1 to be connected with the data conveyer line that is labeled as BL.The other end is connected with the common source line that is labeled as SL by selecting transistor S2.Each transistor all is formed on same trap place.When getting n and be piece index (natural number), the control electrode among each storage unit M0～M15 is connected with the data select line that is labeled as WL0～WL15 respectively.For with can from a plurality of memory cell blocks, select a memory cell block and be connected along the data conveyer line with the data conveyer line, select the control electrode of transistor S1 also to be connected with piece selection wire SSL.Select to be connected with piece selection wire GSL, to form so-called AND memory cell block 49 (zone shown in the dotted line) with the control electrode of transistor S2.In the present embodiment, be illustrated in memory cell block 49 places and be connected with 16=2 ⁴The example of individual storage unit, the storage unit that is connected with data select line with the data conveyer line can be for a plurality of, yet see from the angle of geocoding and to be preferably 2 ⁿIndividual (n is a positive integer).

Figure 34 B is the planimetric map of AND cell block, and Figure 34 C is the sectional view along the line 34C-34C among Figure 34 B, and Figure 34 D is the sectional view along the line 34D-34D among Figure 34 B.Particularly in Figure 34 B,, only show the structure under the gate electrode 27 in order to understand the structure that makes storage unit easily.In Figure 34 C and Figure 34 D, can by for example thickness the silicon oxide layer of 3 millimicrons of (nm)～15 millimicron (nm), or the tunnel gate insulating film that constitutes of oxynitride film 25,25SSL, 25GSL, form thickness and be 10 millimicrons of (nm)～500 millimicron (nm), by being added with 10 ¹⁸Centimetre ^-3(cm ^-3)～10 ²¹Centimetre ^-3(cm ^-3) phosphorus or the electric charge accumulation layer 26 that constitutes of the polysilicon of arsenic.These can be formed self-aligned with p type silicon area 23 not forming on the element separation usefulness zone of dielectric film 24 that is made of silicon oxide layer.

On it, can also be formed with by thickness is the silicon oxide layer of 5 millimicrons of (nm)～30 millimicron (nm) or oxynitride film or the piece dielectric film 50 that is made of silicon oxide layer/silicon nitride film/silicon oxide layer.These are formed self-aligned with p type silicon area 23 for example in the location that does not form the element separating insulation film 24 that is made of silicon oxide layer.And, this can be after for example p type silicon area 23 places be deposited with oxynitride film 25 and electric charge accumulation layer 26 comprehensively, implement corrosion patternization arriving p type silicon area 23, and then embodiment such as the degree of depth be the corrosion of 0.05 micron (μ m)～0.5 micron (μ m), with being embedded into dielectric film 24 formation.Because the integral plane that oxynitride film 25 in this storage unit and electric charge accumulation layer 26 do not have step part forms, so can carry out the film forming that homogeneity is higher, characteristic is consistent.And, the interlayer dielectric 56 of storage unit portion and n type diffusion layer 28, can be before forming tunnel insulator film 25, form the mask material that constitutes by for example polysilicon or the like material at the part place that forms tunnel type dielectric film 25 in advance, and inject formation n type diffusion layer 28 by for example ion after, at the comprehensive deposit interlayer dielectric 56 of whole location, with CMP and corrosion back, the described mask material of selective removal and tunnel type dielectric film 25 considerable parts is formed self-aligned.

Can form by polysilicon, or the lit-par-lit structure of tungsten silicide (WSi) and polysilicon, or the thickness that the lit-par-lit structure of cobalt silicide (CoSi) and polysilicon constitutes is the control gate 27 of 10 millimicrons of (nm)～500 millimicron (nm).This control gate 27 ground connection that can link to each other with the consecutive storage unit piece among Figure 34 B is formed up to the block edge place along the paper left and right directions always, and forms data select line WL0～WL15, and data selection gate controls line SSL, GSL.P type silicon area 23 preferably can pass through n type silicon area 22, applies voltage independently with p type silicon substrate 21, so that the load of booster circuit can reduce to wipe the time, and suppresses the electric power that consumed.

Shown in Figure 34 D, in the D-D sectional view suitable with storage unit, also under these gate electrodes, being formed with clamping, by thickness be the silicon nitride film of 5 millimicrons of (nm)～200 millimicron (nm) or n type diffusion layer 28 interlayer dielectric 56, that constitute source electrode or drain electrode that silicon oxide layer constitutes.Utilize these diffusion layers 28, electric charge accumulation layer 26 and control gate 27, can form with the quantity of electric charge that is stored in electric charge accumulation layer place floating grid type EEPROM (Electrically Erasable Programmable Read Only Memo) (EEPROM) storage unit as quantity of information, the length of these grid can for 0.5 micron (μ m) with down to more than 0.01 micron (μ m).Shown in Figure 34 D, interlayer dielectric 56 is preferably covering the mode of the diffusion layer 28 that constitutes source electrode or drain electrode according to lid, is formed on the raceway groove, so that can prevent owing to the electric field in the source/drain end is concentrated writing unusually of causing.These n type diffusion layers 28 can be 10 according to the surface concentration of its phosphorus, arsenic, antimony ¹⁷Centimetre ^-3(cm ^-3)～10 ²¹Centimetre ^-3(cm ^-3), the degree of depth is that the mode of 10 millimicrons of (nm)～500 millimicron (nm) forms.And these n type diffusion layers 28 can be by being shared along data conveyer line BL direction adjacent memory unit, and realize that the AND type connects.

Reference number 27SSL, 27GSL are respectively the gate electrodes that the piece selection wire suitable with SSL, GSL is connected in the drawings, interlayer dielectric 50 in piece selection wire portion between 26 and 27 is stripped from, with EEPROM (Electrically Erasable Programmable Read Only Memo) (EEPROM) in control electrode WL0～WL15 form with one deck.Here, shown in Figure 34 B and Figure 34 C, piece is selected with transistor

S1 diffusion layer

28 and 28d as source/drain, 27SSL is formed mos field effect transistor (MOSFET) as gate electrode, and piece is selected with transistor

S2 diffusion layer

28 and 28s as source/drain 27GSL to be formed mos field effect transistor (MOSFET) as gate electrode.Here, the gate length of gate electrode 27SSL, 27GSL is longer than the gate electrode length of storage unit, for example be 1 micron (μ m) with down to more than 0.02 micron (μ m), can guarantee that piece has bigger conducting, disconnection ratio when selecting with non-selections, read and miss and write to prevent mistake.

Present embodiment adopts AND type storage unit shown in Figure 34 A～Figure 34 D, thus the series impedance of memory cell block can be decreased to a certain degree, thus also can keep the stable of threshold value for the occasion of many-valuedization.

Storage unit in the semiconductor storage of aforesaid first, second and the 3rd embodiment also can not adopt NAND type storage unit, but adopts the AND type storage unit by the present embodiment explanation.

(the 6th embodiment)

Figure 35 A～Figure 35 D represents the storage unit structure in the sixth embodiment of the invention.

Present embodiment replaces with the AND type cell block that adopts non-service monitor (MONOS) type storage unit with the AND type cell block 49 that the 5th embodiment illustrated, adopting the floating grid type.

Figure 35 A～Figure 35 D be respectively with circuit diagram, the planimetric map of Figure 34 A～corresponding AND cell block of Figure 34 D, with and piece select grid portion, storage unit portion sectional view.

Shown in Figure 35 A, the non-volatile memory cells M0～M15 that is made of MOS type (MOS type) transistor with electric charge accumulation layer electrode is connected in parallel, and the one end is selected to be connected with the data conveyer line that is labeled as BL with transistor S1 by piece.The other end is selected to be connected with the common source line that is labeled as SL with transistor S2 by piece.Each transistor all is formed on the same trap.When getting n and be piece index (natural number), the control electrode among each storage unit M0～M15 is connected with the data select line that is labeled as WL0～WL15 respectively.For from selecting a memory cell block and be connected with the data conveyer line along a plurality of memory cell blocks of data conveyer line, piece is selected also to be connected with piece selection wire SSL with the control electrode of transistor S1.And piece is selected to be connected with piece selection wire GSL with the control electrode of transistor S2, to form so-called AND type memory cell block 45 (zone shown in the dotted line).In the present embodiment, piece is selected the control wiring SSL and the GSL of grid, can use with storage unit to form with the wiring of layer with control wiring WL0～WL15.The piece selection wire preferably is at least one or more in memory cell block 49, and forms in the direction identical with data select line, to realize densification.In the present embodiment, be illustrated in memory cell block 49 places and be connected with 16=2 ⁴The example of individual storage unit can be considered to be preferably 2 from implementing geocoding for a plurality of with the storage unit that the data conveyer line is connected with data select line ⁿIndividual (n is a positive integer).

Figure 35 B is the planimetric map of AND type memory cell block 49, the sectional view of Figure 35 C for cutting open along the line C-C among Figure 35 B, the sectional view of Figure 35 D for cutting open along the line D-D among Figure 35 B.Particularly in Figure 35 B,, only show the structure under the gate electrode 27 in order to understand the structure of storage unit easily.Shown in Figure 35 C and Figure 35 D, can be the silicon oxide layer that 0.5 millimicron of (nm)～10 millimicron (nm) are formed by for example thickness, or the tunnel gate insulating film that constitutes of oxynitride film 25,25SSL, 25GSL, form thickness and be electric charge accumulation layer 26 4 millimicrons of (nm)～50 millimicron (nm), that constitute by for example silicon nitride film.On it, can also be by being the silicon oxide layer of 4 millimicrons of (nm)～50 millimicron (nm) or the piece dielectric film 50 that oxynitride film constitutes by thickness, being formed with thickness is the polysilicon layer 51 of 10 millimicrons of (nm)～500 millimicron (nm).And these can be formed self-aligned with p type silicon area 23 in the location that does not form the element separating insulation film 24 that is made of silicon oxide layer.This can be after the comprehensive deposit 25,26,40,41 in p type silicon area 23 places, implement corrosion patternization to arrive p type silicon area 23, and then enforcement such as the degree of depth is the corrosion of 0.05 micron (μ m)～0.5 micron (μ m), so that dielectric film 24 is implemented to be embedded into to form.Because 25,26 and 40 integral body form on the very little plane of step difference, so can carry out the system film that homogeneity is higher, characteristic is consistent.And, the interlayer dielectric 56 of storage unit portion and n type diffusion layer 28, can be before forming tunnel type dielectric film 25, form the mask material that constitutes by for example polysilicon or the like material at the part place that is pre-formed tunnel type dielectric film 25, and after forming n type diffusion layer 28 by for example ion injection mode or the like, at the comprehensive deposit interlayer dielectric 56 of whole location, by CMP and time corrosion or the like mode, select the described mask material at removal and tunnel type dielectric film 25 considerable part places, be formed self-aligned.

Can form by polysilicon, or the lit-par-lit structure of tungsten silicide (WSi) and polysilicon, or the thickness that the lit-par-lit structure of cobalt silicide (CoSi) and polysilicon constitutes is the control gate 27 of 10 millimicrons of (nm)～500 millimicron (nm).This control gate 27 ground connection that can link to each other with the consecutive storage unit piece among Figure 35 B is formed up to the block edge place along the paper left and right directions always, and forms data select line WL0～WL15, and piece selection gate controls line SSL, GSL.P type silicon area 23 applies voltage by n type silicon area 22 independently with p N-type semiconductor N substrate 21, so that the load of booster circuit can reduce to wipe the time, and suppresses the electric power that consumed.

Shown in Figure 35 D, in the D-D section suitable with storage unit, also under these gate electrodes, being formed with clamping, by thickness be the silicon nitride film of 5 millimicrons of (nm)～200 millimicron (nm) or n type diffusion layer 28 interlayer dielectric 56, that constitute source electrode or drain electrode that silicon oxide layer constitutes.Utilize these diffusion layers 28, electric charge accumulation layer 26 and control gate 27, can form with the quantity of electric charge that is stored in electric charge accumulation layer place non-service monitor (MONOS) type EEPROM (Electrically Erasable Programmable Read Only Memo) (EEPROM) as quantity of information, the length of these grid can for 0.5 micron (μ m) with down to more than 0.01 micron (μ m).Shown in Figure 35 D, interlayer dielectric 56 is preferably covering the mode of the diffusion layer 28 that constitutes source electrode or drain electrode according to lid, is formed on the raceway groove, so that can prevent owing to concentrating writing unusually of causing at the electric field at place, source/drain end.These n type diffusion layers 28 can be 10 according to the surface concentration of its phosphorus, arsenic, antimony ¹⁷Centimetre ^-3(cm ^-3)～10 ²¹Centimetre ^-3(cm ^-3), the degree of depth is that the mode of 10 millimicrons of (nm)～500 millimicron (nm) forms.And these n type diffusion layers 28 can be by shared along data conveyer line BL direction adjacent memory unit, and realize that the AND type connects.

Reference number 27SSL, 27GSL are respectively the gate electrodes that the piece selection wire suitable with SSL, GSL is connected in the drawings, and can be formed on in one deck with the online WL0～WL15 of control in the EEPROM (Electrically Erasable Programmable Read Only Memo) (EEPROM) of described MONOS type.Here shown in Figure 35 B and Figure 35 C, piece is selected with transistor

S1 diffusion layer

28 and 28s as source/drain, 27SSL is formed the mos field effect transistor (MOSFET) of MOS type (MOS type) type as gate electrode, and piece is selected with transistor

S2 diffusion layer

28 and 28d 27GSL to be formed the mos field effect transistor (MOSFET) of MOS type (MOS type) type as gate electrode as source/drain.Here, the gate length of gate electrode 27SSL, 27GSL is longer than the gate electrode length of storage unit, for example be 1 micron (μ m) with down to more than 0.02 micron (μ m), can guarantee when piece is selected with non-the selection conducting, disconnect than big, write to prevent that mistake from reading and missing.

Present embodiment has the advantage that the 5th embodiment is had, promptly owing to adopting the AND storage unit, thus the series impedance of memory cell block can be decreased to a certain degree, thus also can keep the stable of threshold value for the occasion of many-valuedization.In addition, owing to adopt MONOS type storage unit, so compare with the occasion that is adopting floating grid type EEPROM (Electrically Erasable Programmable Read Only Memo) (EEPROM) among the 5th embodiment, can further make and write voltage, erasing voltage lower voltage, even, also can keep withstand voltage in order to make the element separation spacing narrow and make the thick gate insulating film filming.Therefore, can make to apply high-tension circuit area minimizing, thereby can further dwindle chip area.

And compare with the 5th embodiment, owing to the thickness of electric charge accumulation layer 26 can be decreased to 20 millimicrons below (nm), so flat shape in the time of can further dwindling grid formation, improve the machining shape of gate electrode, and then can improve the amount of being embedded between the grid of interlayer dielectric, further improve its resistance to pressure.And, owing to do not need the operation of using for the formation floating gate electrode and make the operation that narrow slit is used, so can further shorten production process.And electric charge accumulation layer 26 insulate, can be with charge-trapping to one by one charge trap place, and institute is so that electric charge is difficult to come off with respect to radioactive ray, thereby can have stronger resistance to pressure.And, even make side wall insulating film 43 filmings of electric charge accumulation layer 26, the electric charge that is captured to electric charge accumulation layer 26 place is all escaped, so can keep good charge-retention property.Electric charge accumulation layer 26 can cooperate the mode of not having skew to form with p type silicon area 23, so can further make the electric capacity homogenising of electric charge accumulation layer 26 and p type groove 23.Adopt this form of the composition, can also reduce the capacitance deviation between memory cell capacitor deviation and storage unit.

And the storage unit in the semiconductor storage of the above first, second and the 3rd embodiment not only adopts the AND storage unit of having used floating grid type storage unit, and can adopt by the AND storage unit present embodiment explanation, that adopt MONOS type storage unit.

(the 7th embodiment)

Figure 36 A～Figure 36 D represents that the storage unit in the seventh embodiment of the invention constitutes.

The NAND cell block 49 that present embodiment will illustrate in first～the 4th embodiment replaces with the NOR cell block.

Figure 36 A is the circuit diagram of NOR cell block.

Shown in Figure 36 A, have non-volatile memory cells M0～M15 electric charge accumulation layer electrode, that constitute by MOS type (MOS type) transistor and be connected in parallel, and the one end is connected with the data conveyer line that is labeled as BL.The other end is connected with shared source electrode line SL.Can utilize a transistor to form memory cell block 49 at the NOR memory cell block.Each transistor all is formed on the same trap.Control electrode among each storage unit M0～M15 is connected with the data select line that is labeled as WL0～WL15 respectively.

Figure 36 B is the planimetric map of NOR cell block, and Figure 36 C is the sectional view along the line C-C among Figure 36 B, and Figure 36 D is the sectional view along the line D-D among Figure 36 B.Particularly in Figure 36 B,, only show the structure under the gate electrode 27 in order to understand the structure of storage unit easily.In Figure 36 C and Figure 36 D, can be the silicon oxide layer that 3 millimicrons of (nm)～15 millimicron (nm) constitute by for example thickness, or the tunnel gate insulating film that constitutes of oxynitride film 25, form thickness and be 10 millimicrons of (nm)～500 millimicron (nm), by being added with 10 ¹⁸Centimetre ^-3(cm ^-3)～10 ²¹Centimetre ^-3(cm ^-3) phosphorus or the electric charge accumulation layer 26 that constitutes of the polysilicon of arsenic.These can be formed self-aligned with p type silicon area 23 in the location that does not form the element separating insulation film 24 that is made of silicon oxide layer.

On it, can also be formed with by thickness is the silicon oxide layer of 5 millimicrons of (nm)～30 millimicron (nm) or the piece dielectric film 50 of oxynitride film or silicon oxide layer/silicon nitride film/silicon oxide layer formation.This dielectric film 50 can be formed self-aligned with p type silicon area 23 not being formed with the element separation that is made of the silicon oxide layer location of dielectric film 24.

Can form by polysilicon, or the lit-par-lit structure of tungsten silicide (WSi) and polysilicon, or the thickness that the lit-par-lit structure of cobalt silicide (CoSi) and polysilicon constitutes is the control gate 27 of 10 millimicrons of (nm)～500 millimicron (nm).This control gate 27 can be connected ground with the consecutive storage unit piece among Figure 36 B, is formed up to the block edge place along the paper left and right directions always, and forms data select line WL0～WL2.P type silicon area 23 preferably can pass through n type silicon area 22, applies voltage independently with p N-type semiconductor N substrate 21, so that the load of booster circuit can reduce to wipe the time, and suppresses the electric power that consumed.

Shown in Figure 36 D, in the D-D sectional view suitable with storage unit, also under these grid, being formed with clamping, by thickness be the silicon nitride film of 5 millimicrons of (nm)～200 millimicron (nm) or n type diffusion layer 28 interlayer dielectric 56, that constitute source electrode or drain electrode that silicon oxide layer constitutes.Utilize these diffusion layers 28, electric charge accumulation layer 26 and control gate 27, can form with the quantity of electric charge that is stored in electric charge accumulation layer place floating grid type EEPROM (Electrically Erasable Programmable Read Only Memo) (EEPROM) storage unit as quantity of information, the length of these grid can for 0.5 micron (μ m) with down to more than 0.01 micron (μ m).Shown in Figure 36 B, Figure 36 D, the corresponding n type of the n type diffusion layer 28d diffusion layer 28 with being connected with connecting line BL can constitute along the paper left and right directions of Figure 36 B source electrode line SL that extending, that be connected with consecutive storage unit.Even this NOR type storage unit and since clamping connecting line SL, form by dielectric film along data select line direction adjacent memory unit electric charge accumulation interlayer, so the capacitive coupling of electric charge accumulation interlayer can produce changes of threshold.Therefore, shown in the M0 of Figure 36 A and M1, clamping two consecutive storage units of source electrode, can be stored into a plurality of threshold values more than two values at a storage unit place, such as be stored into four value threshold values, with two bits that are stored together, implement writing of each bit for consecutive storage unit while implementing verification,, can also implement compensation the variation that produces owing to the consecutive storage unit capacitive coupling so adopt the method for the 3rd embodiment.

And, along between two adjacent storage unit of column direction also shown in Figure 36 A～Figure 36 D, be embedded into by dielectric film, so the capacitive coupling of electric charge accumulation interlayer can produce changes of threshold.Therefore, shown in the storage unit M1 and M1 ' of Figure 33 A, two storage unit adjacent to column direction, can be stored into a plurality of threshold values more than two values at a storage unit place, such as be stored into four value threshold values, with two bits that are stored together,, consecutive storage unit implements writing of each bit while being implemented verification, if, can also implement compensation to the variation that produces owing to the consecutive storage unit capacitive coupling so adopt the method for the 3rd embodiment.

If adopt the structure of first～the 7th embodiment as mentioned above,, can realize narrower threshold distribution even after the consecutive storage unit implementation data writes.Therefore, even adopt identical max-thresholds to distribute, also can make and the corresponding threshold distribution of data between the separation voltage amplitude bigger, even, also can reduce owing to the overlapping data corruption that produces between the different pieces of information threshold distribution so produce drift owing to charge-retention property deterioration and temperature variation make threshold value.

And formerly technology is lower for the ratio that the maximal value of storage unit threshold distribution can be set.Therefore, smaller by the electric field of assembling electric charge self generation, thus can keep good charge-retention property.Be in the NAND type memory cell block that is connected in series and forms in storage unit, for the storage unit that connects in the sense data units in series, must be created in the grid place and apply the voltage bigger, but can reduce the voltage that is applied becomes possibility than threshold distribution maximal value.Therefore, by repeating read operation, inject negative charge and the threshold value rising problem that produces to the electric charge accumulation layer, but can suppress this problem, the threshold value magnitude of separation in the time of particularly well guaranteeing threshold value when erase status is " 11 " and state for " 10 ".

And, for the occasion of implementing read operation, since can guarantee judgment threshold and with the bigger separation voltage amplitude of the corresponding threshold value of data, so can further reduce wrong read frequency, to read the grid driving voltage of judgement bigger thereby can guarantee to carry out data.Therefore, when high, the electric current of the storage unit of flowing through is kept necessarily with the corresponding threshold ratio judgment threshold of data substantially, with the corresponding threshold ratio judgment threshold of data when low, the electric current of the storage unit of flowing through is increased, thereby can make the reading speed high speed.

And, even even the electric capacity of electric charge accumulation interlayer is because change in size and voltage drift and change to some extent, because being carried out checking data, the consecutive storage unit that is subjected to the changes of threshold influence writes work again, so threshold drift is remained within certain threshold range lessly.

And, in formation of the present invention, owing to include the inscape of the Nonvolatile memory devices that the storage two-value data is used in the technology formerly, so can implement on the basis of the Nonvolatile memory devices function that the storage two-value data is used in not destroying technology formerly in the same old way.

And, for first embodiment and the 3rd embodiment,, can cut apart page or leaf and append and follow direction and constitute storage unit and the sensor amplifier that memory cell array is used with respect to memory cell array.For second embodiment, no longer need further to append storage unit than technology formerly.Therefore for whole embodiment, do not need to append storage unit, so can constitute the circuit that can not increase with increase along data select line direction area along the bearing of trend of data conveyer line.

And for the 3rd embodiment, also be formed with temporarily to writing a plurality of circuit that data enforcement keeps at each sensor amplifier place, so fashionablely compare to the occasion that sensor amplifier transmits data at any time by the external data impact damper with writing, can improve speed, shorten length of arrangement wire, thereby can reduce power consumption.

The present invention will be described with first～the 7th embodiment above, yet the present invention is not limited in these embodiment.For example represent and cut apart the corresponding example of page or leaf, cut apart page or leaf certainly and also can be one at the example of the above.And the embodiment of expression, yet also can implement the threshold value correction in the lump to both sides along column direction and line direction adjacent memory unit to following the direction adjacent memory unit and carrying out the threshold value correction independently along the column direction adjacent memory unit.

And, mainly use n type metal insulatioin semiconductor field effect transistor (MISFET) as on-off element in the above embodiments, yet these if make grid input counter-rotating, also can implement to replace to p transistor npn npn and n transistor npn npn.

And, constituting the nonvolatile semiconductor element with EEPROM (Electrically Erasable Programmable Read Only Memo) (EEPROM) in the above embodiments is that the present invention will be described for example, yet it is self-evident, formation of the present invention is by some data select lines and some the memory cell arrays that the data conveyer line constitutes, between the mutual adjacent memory unit in the information stores zone of storage unit, utilization is stored in the information at consecutive storage unit place, and the structure of being interfered with location information is effective.For example, even do not use the information that is stored in electric charge accumulation layer place but utilize amount of polarization or counter-rotating comes the strong electrolyte body storage unit of canned data, owing to produce electric field according to polarised direction at consecutive storage unit, so the present invention also is suitable for.And, promptly use the ferromagnetism body of direction of magnetization or intensity, because consecutive storage unit produces magnetic field according to polarised direction, the present invention also is suitable for.

And, the formation method of element isolation film and dielectric film itself is transformed into silicon the method for silicon oxide layer and silicon nitride film except using, for example for example can also adopt method from the silicon materials oxidation that makes deposit to the silicon of deposit that implement method that oxonium ion injects and or the like.And electric charge accumulation layer 26 can also adopt for example titania (TiO ₂) and alundum (Al (Al ₂O ₃) or tantalum oxide film, strontium titanates and barium titanate, zirconia titanate lead, and their stack membrane or the like.

And, as example, be envisioned for p type silicon substrate as Semiconductor substrate 21, but also can be silicon-on-insulator (SOI) silicon layer on n type silicon substrate and silicon-on-insulator (SOI) substrate, or SiGe (SiGe) mixed crystal, Germanium carbon (SiGeC) mixed crystal or the like include the single crystal semiconductor substrate of silicon.

And, the present invention describes for example form n type metal oxide semiconductor field effect transistor (MOSFET) on p type silicon area 23, yet the present invention can also be replaced as and form p type metal oxide semiconductor field effect transistor (MOSFET) on n type silicon area 23, for this occasion, n type in the foregoing description can be replaced with the p type, the p type replaces to the n type, but also can adopt for example indium (In), palladium (b) or the like to implementing to replace as the arsenic (As) that oozes miscellaneous material, phosphorus (p), antimony (Sb) among the described embodiment.

And, gate electrode 27 among the present invention can also adopt for example silicon (Si) semiconductor, SiGe (SiGe) mixed crystal, Germanium carbon (SiGeC) mixed crystal, Titanium silicide (TiSi), nickel silicide (NiSi), cobalt silicide (CoSi), tantalum silicide (TaSi), tungsten silicide (WSi), silicide of molybdenum silicide (MoSi) or the like and multi-crystal silicification thing, and titanium (Ti) for example, aluminium (Al), copper (Cu), titanium nitride (TiN), the metal of tungsten (W) or the like is made, and can adopt polycrystalline material to make, also can be the stromatolithic structure that these materials constitute.And, can also adopt for example amorphous silicon, amorphous silicon germanium (SiGe) mixed crystal, amorphous silicon germanium carbon (SiGeC) mixed crystal, also can be the laminated body structure that these materials constitute.And self-evident, even forming point-like, electric charge accumulation layer 26 do not mind yet, also can use this method.

And those of ordinary skill in the art can carry out all different distortion and implement under the prerequisite that does not break away from theme of the present invention and scope.

And aforesaid each embodiment can implement separately, also can make up enforcement.

And the above each embodiment comprises the invention in each stage, by the appropriate combination of the disclosed some inscapes of each embodiment, can also extract the invention in each stage.

With reference to top explanation, those of ordinary skill in the art can be known other advantage of the present invention and embodiment.Therefore, the scope of asking for protection of the present invention is not limited in the concrete form of the composition that is made of these embodiment.Those of ordinary skill in the art can carry out the change of various ways to each thin portion in not breaking away from theme of the present invention and scope, and theme of the present invention and scope are to be limited by the claim of attached friendship and their equivalent.

Claims

1. the method for writing data of a semiconductor storage, but described semiconductor storage has implementation data first memory cell block of write operation once more that includes one first storage unit at least, but and the implementation data that includes second storage unit adjacent at least second memory cell block of write operation once more with first storage unit, it is characterized in that this method for writing data comprises:

The described first storage unit implementation data is write;

After the described first storage unit implementation data is write, the described second storage unit implementation data is write;

After the described second storage unit implementation data is write, the described first storage unit implementation data is judged;

And when data no show that described data judged result is described first storage unit, the described first storage unit implementation data is write once more.

2. the method for writing data of semiconductor storage as claimed in claim 1, it is characterized in that described first, second storage unit has the electric charge accumulation layer of implementing the electric charge injection accordingly or emitting with the data that need to keep respectively, and the data more than the two-value are implemented storage as the quantity of electric charge.

3. the method for writing data of semiconductor storage as claimed in claim 1, the data that it is characterized in that described first, second storage unit has respectively and need to keep are implemented the electric charge accumulation layer that electric charge injects or emit usefulness accordingly, and two-value data is implemented to store as the quantity of electric charge;

And for the above data of three values that apply by the outside, respectively with described first, second storage unit in two-value data implement storage accordingly.

4. the method for writing data of a semiconductor storage, but described semiconductor storage has and includes two adjacent one another are, implementation data of being first storage unit that is connected in series or is connected in parallel and second storage unit memory cell block of write operation once more at least, it is characterized in that this method for writing data comprises:

The described first storage unit implementation data is write;

And when described data judged result is the described first memory cell data no show, the described first storage unit implementation data is write once more.

5. the method for writing data of semiconductor storage as claimed in claim 4, it is characterized in that described first, second storage unit has the electric charge accumulation layer of implementing the electric charge injection accordingly or emitting with the data that need to keep respectively, and the data more than the two-value are implemented storage as the quantity of electric charge.

6. the method for writing data of semiconductor storage as claimed in claim 4, it is characterized in that described first, second storage unit has the electric charge accumulation layer of implementing the electric charge injection accordingly or emitting with the data that need to keep respectively, and the data of two-value are implemented storage as the quantity of electric charge;

7. conductor integrated circuit device is characterized in that having:

But first memory cell block that implementation data writes once more, described first memory cell block has one first storage unit at least;

But second memory cell block that implementation data writes once more, described second memory cell block have second storage unit adjacent with described first storage unit at least;

The first data conveyer line, the described first data conveyer line directly is connected with described first memory cell block, or is electrically connected with described first memory cell block by the alternative pack that described first memory cell block is implemented to select;

The second data conveyer line, the described second data conveyer line directly is connected with described second memory cell block, or is electrically connected with described second memory cell block by the alternative pack that described second memory cell block is implemented to select;

Charging circuit, described charging circuit are used for any the enforcement charging to described first data conveyer line and the described second data conveyer line;

Charging and discharge circuit, described charging and discharge circuit are implemented charge or discharge according to the data that remain in described the 3rd data holding circuit to first voltage node;

First connecting circuit, described first connecting circuit are electrically connected arbitrary in described first voltage node and described first, second data conveyer line;

8. conductor integrated circuit device as claimed in claim 7 is characterized in that described conductor integrated circuit device also has:

Along with the configuration of the direction of described first, second data conveyer line quadrature and along many data input-output lines that extend with the direction of described first, second data conveyer line quadrature;

And the 3rd connecting circuit that each comprised in described data input-output line and a plurality of conductor integrated circuit devices that disposed the 4th data holding circuit is electrically connected.

9. conductor integrated circuit device as claimed in claim 7 is characterized in that described conductor integrated circuit device also has:

Along implementing many control lines of control usefulness with the configuration of the direction of described first, second data conveyer line quadrature and to each comprised in a plurality of conductor integrated circuit devices that disposed first, second, third, fourth data holding circuit and charging circuit and discharge circuit, and these control lines are shared by a plurality of conductor integrated circuit devices that disposed.

10. conductor integrated circuit device as claimed in claim 9 is characterized in that described first, second data conveyer line is respectively two.

11. conductor integrated circuit device as claimed in claim 9 is characterized in that described first, second data conveyer line is respectively four.

12. conductor integrated circuit device as claimed in claim 7 is characterized in that described first data holding circuit and described the 4th data holding circuit are respectively the reverse flip-flop circuit that is connected in parallel and constitutes of phase inverter.

13. conductor integrated circuit device as claimed in claim 7, it is characterized in that being included in the transistor size in described second data holding circuit, lack than the transistor size that is included in the transistor size in described first data holding circuit and be included in described the 4th data holding circuit.

14. conductor integrated circuit device as claimed in claim 7, it is characterized in that after the described first storage unit implementation data is write, the described second storage unit implementation data is write, not to described first, described second storage unit simultaneously implementation data write.

15. conductor integrated circuit device as claimed in claim 7 is characterized in that being electrically connected data input pin of described the 3rd data holding circuit with described first data holding circuit by the 4th connecting circuit;

And described first voltage node is electrically connected with described first data holding circuit by the 5th connecting circuit.

16. conductor integrated circuit device as claimed in claim 15 is characterized in that described the 3rd data holding circuit includes first switch block with control electrode and current path;

The control electrode of described first switch block is electrically connected with described first data holding circuit by described the 4th connecting circuit;

One end of the described first switch block current path is connected with described first voltage node, and the other end is connected with the tertiary voltage node that has two stationary values at least by the second switch parts.

17. conductor integrated circuit device as claimed in claim 15 is characterized in that described the 3rd data holding circuit includes first switch block with control electrode and current path;

One end of the described first switch block current path is connected with described first voltage node by the second switch parts, and the other end is connected with the tertiary voltage node that has two stationary values at least.

18. conductor integrated circuit device as claimed in claim 7 is characterized in that being electrically connected data input pin of described the 3rd data holding circuit with second voltage node by the 6th connecting circuit;

And described second voltage node is electrically connected with described first voltage node by the 7th connecting circuit, passes through the 8th connecting circuit simultaneously and is electrically connected with described first data holding circuit.

19. conductor integrated circuit device as claimed in claim 18 is characterized in that described the 3rd data holding circuit includes first switch block with control electrode and current path;

The control electrode of described first switch block is electrically connected with described second voltage node;

20. conductor integrated circuit device as claimed in claim 18 is characterized in that described the 3rd data holding circuit includes first switch block with control electrode and current path;

One end of the described first switch block current path is connected with described first voltage node by the second switch parts, and the other end is connected with the tertiary voltage node that keeps two stationary values at least.

21. conductor integrated circuit device as claimed in claim 7 is characterized in that described the 3rd data holding circuit includes first switch block with control electrode and current path;

The control electrode of described first switch block is electrically connected with described first data holding circuit;

One end of the described first switch block current path is connected with described first voltage node, and the other end is connected with the tertiary voltage node that keeps two stationary values at least by the second switch parts.

22. conductor integrated circuit device as claimed in claim 7 is characterized in that described the 3rd data holding circuit includes first switch block with control electrode and current path;

23. conductor integrated circuit device as claimed in claim 7 is characterized in that respectively that three values are the above data of first, second storage unit are as logical value enforcement storage.

24. conductor integrated circuit device as claimed in claim 7 is characterized in that first, second storage unit is respectively the field effect transistor with at least one electric charge accumulation layer and control gate.

25. conductor integrated circuit device as claimed in claim 24, it is characterized in that respectively that four values are the above numerical data of first, second storage unit implements storage as logical value and according to the size of the quantity of electric charge that is accumulated in described electric charge accumulation layer, implement the bit reversal of a bit between the occasion of ranking in proper order according to the described quantity of electric charge in numerical data, the every pair of consecutive number digital data for the quantity of electric charge.

26. conductor integrated circuit device as claimed in claim 24 is characterized in that described field effect transistor is respectively formed on the trap of identical conduction type.

27. conductor integrated circuit device as claimed in claim 26 is characterized in that described field effect transistor uses the FN tunnel current in write activity.

28. conductor integrated circuit device as claimed in claim 24 is characterized in that described electric charge accumulation layer includes silicon nitride.

29. conductor integrated circuit device as claimed in claim 28, it is characterized in that described first, second storage unit makes a plurality of source electrodes and drain electrode be connected in series respectively, and make below the twice of the described electric charge accumulation layer thickness of being spaced apart of adjacent electric charge accumulation layer within a plurality of storage unit respectively.

30. conductor integrated circuit device as claimed in claim 24 is characterized in that described electric charge accumulation layer is the floating gate electrode that includes polysilicon.

31. conductor integrated circuit device as claimed in claim 30, it is characterized in that described first, second storage unit makes a plurality of source electrodes and drain electrode be connected in series respectively, and make below the twice of the described electric charge accumulation layer thickness of being spaced apart of adjacent electric charge accumulation layer within a plurality of storage unit respectively.

32. conductor integrated circuit device as claimed in claim 30 is characterized in that only being formed with insulant between described first charge storing unit accumulating layer and the described second charge storing unit accumulating layer.

33. a conductor integrated circuit device is characterized in that having:

But implementation data is the memory cell block of write operation once more, described memory cell block have include at least two adjacent one another are, be first storage unit and second storage unit that are connected in series or are connected in parallel;

Charging and discharge circuit, described charging and discharge circuit are implemented charge or discharge according to the data that remain on described the 3rd data holding circuit to first voltage node;

34. conductor integrated circuit device as claimed in claim 33 is characterized in that described conductor integrated circuit device also has:

Along with the configuration of the direction of described data conveyer line quadrature and along a plurality of data input-output lines that extend with the direction of described data conveyer line quadrature;

And make each comprised in described data input-output line and a plurality of conductor integrated circuit devices that disposed the 4th data holding circuit implement the 3rd connecting circuit that is electrically connected.

35. conductor integrated circuit device as claimed in claim 33 is characterized in that described conductor integrated circuit device also has:

Along implementing a plurality of control lines of control usefulness with the configuration of the direction of described data conveyer line quadrature and to each comprised in a plurality of conductor integrated circuit devices that disposed first, second, third, fourth data holding circuit and charging circuit and discharge circuit, and these control lines are shared by a plurality of conductor integrated circuit devices that disposed.

36. conductor integrated circuit device as claimed in claim 35 is characterized in that described data conveyer line is two.

37. conductor integrated circuit device as claimed in claim 35 is characterized in that described data conveyer line is four.

38. conductor integrated circuit device as claimed in claim 33 is characterized in that described first data holding circuit and described the 4th data holding circuit are respectively the reverse flip-flop circuit that is being connected in parallel of phase inverter.

39. conductor integrated circuit device as claimed in claim 33, it is characterized in that being included in the transistor size in described second data holding circuit, lack than the transistor size that is included in the transistor size in described first data holding circuit and be included in described the 4th data holding circuit.

40. conductor integrated circuit device as claimed in claim 33, it is characterized in that after the described first storage unit implementation data is write, the described second storage unit implementation data is write, not to described first, described second storage unit simultaneously implementation data write.

41. conductor integrated circuit device as claimed in claim 33 is characterized in that data input pin in described the 3rd data holding circuit, is electrically connected with described first data holding circuit by the 4th connecting circuit;

42. conductor integrated circuit device as claimed in claim 41 is characterized in that described the 3rd data holding circuit includes first switch block with control electrode and current path;

43. conductor integrated circuit device as claimed in claim 41 is characterized in that described the 3rd data holding circuit includes first switch block with control electrode and current path;

44. conductor integrated circuit device as claimed in claim 33 is characterized in that being electrically connected data input pin of described the 3rd data holding circuit with second voltage node by the 6th connecting circuit;

45. conductor integrated circuit device as claimed in claim 44 is characterized in that described the 3rd data holding circuit includes first switch block with control electrode and current path;

The control electrode of described first switch block is connected with described second voltage node;

46. conductor integrated circuit device as claimed in claim 44 is characterized in that described the 3rd data holding circuit includes first switch block with control electrode and current path;

47. conductor integrated circuit device as claimed in claim 33 is characterized in that described the 3rd data holding circuit includes first switch block with control electrode and current path;

48. conductor integrated circuit device as claimed in claim 33 is characterized in that described the 3rd data holding circuit includes first switch block with control electrode and current path;

49. conductor integrated circuit device as claimed in claim 33 is characterized in that respectively that three values are the above data of described first, second storage unit are as logical value enforcement storage.

50. conductor integrated circuit device as claimed in claim 33 is characterized in that described first, second storage unit is respectively the field effect transistor with at least one electric charge accumulation layer and control gate.

51. conductor integrated circuit device as claimed in claim 50, it is characterized in that respectively that four values are the above numerical data of described first, second storage unit is as logical value and according to the size enforcement storage that is accumulated in the quantity of electric charge in the described electric charge accumulation layer, implement the bit reversal of a bit between the occasion of ranking in proper order according to the described quantity of electric charge in numerical data, the every pair of consecutive number digital data for the quantity of electric charge.

52. conductor integrated circuit device as claimed in claim 50, it is characterized in that described field effect transistor be respectively formed at identical conduction type trap on.

53. conductor integrated circuit device as claimed in claim 52 is characterized in that described field effect transistor uses the FN tunnel current in write activity.

54. conductor integrated circuit device as claimed in claim 50 is characterized in that described electric charge accumulation layer includes silicon nitride.

55. conductor integrated circuit device as claimed in claim 54, it is characterized in that described first, second storage unit makes a plurality of source electrodes and drain electrode be connected in series respectively, and make below the twice of the described electric charge accumulation layer thickness of being spaced apart of adjacent electric charge accumulation layer within a plurality of storage unit respectively.

56. conductor integrated circuit device as claimed in claim 50 is characterized in that described electric charge accumulation layer is the floating gate electrode that includes polysilicon.

57. conductor integrated circuit device as claimed in claim 56, it is characterized in that described first, second storage unit makes a plurality of source electrodes and drain electrode be connected in series respectively, and respectively below the twice that is spaced apart described electric charge accumulation layer thickness that makes within a plurality of storage unit between adjacent electric charge accumulation layer and the described second charge storing unit accumulating layer.

58. conductor integrated circuit device as claimed in claim 56 is characterized in that only being formed with insulant between described first charge storing unit accumulating layer and the described second charge storing unit accumulating layer.

59. a conductor integrated circuit device is characterized in that having:

First memory cell array, but described first memory cell array includes and has first, second memory cell block that writes once more along the implementation data with the configuration of the direction of data conveyer line quadrature and a plurality of storage unit of being connected in series or being connected in parallel, and along with the direction of described data conveyer line quadrature data select line that form, that described first, second memory cell block is connected in parallel, and the data that three values are above of the storage unit in described first memory cell array are implemented storage as logical value;

And second memory cell array, but described second memory cell array include have for described first memory cell array along with the implementation data of the direction configuration of described data conveyer line quadrature and a plurality of storage unit of being connected in series or being connected in parallel the 3rd, the 4th memory cell block of write operation once more, with the total data select line of the data select line of described first memory cell array, the storage unit of described second memory cell array is implemented storage with the data of two-value as logical value.

60. conductor integrated circuit device as claimed in claim 59, the number that it is characterized in that being included in storage unit in described second memory cell array, that be connected with a data select line is more than two, and described number lacks than the number that is included in storage unit in described first memory cell array, that be connected with a data select line.

61. a conductor integrated circuit device has:

But a plurality of first memory cell blocks that implementation data writes once more;

It is characterized in that from described a plurality of first memory cell blocks and described a plurality of second memory cell block erase data, described a plurality of first memory cell blocks are implemented write operation, make described a plurality of second memory cell block when keeping the erase status implementation data to read, the data of described a plurality of second memory cell blocks are consistent with the data in described a plurality of first memory cell blocks.