[go: up one dir, main page]
More Web Proxy on the site http://driver.im/

CN1237651A - 形成双重金属镶嵌结构的方法 - Google Patents

形成双重金属镶嵌结构的方法 Download PDF

Info

Publication number
CN1237651A
CN1237651A CN98116853A CN98116853A CN1237651A CN 1237651 A CN1237651 A CN 1237651A CN 98116853 A CN98116853 A CN 98116853A CN 98116853 A CN98116853 A CN 98116853A CN 1237651 A CN1237651 A CN 1237651A
Authority
CN
China
Prior art keywords
layer
silicon nitride
insulation layer
substrate
nitride layer
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
CN98116853A
Other languages
English (en)
Other versions
CN1194401C (zh
Inventor
罗吉进
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Worldwide Semiconductor Manufacturing Corp
Original Assignee
Worldwide Semiconductor Manufacturing Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Worldwide Semiconductor Manufacturing Corp filed Critical Worldwide Semiconductor Manufacturing Corp
Publication of CN1237651A publication Critical patent/CN1237651A/zh
Application granted granted Critical
Publication of CN1194401C publication Critical patent/CN1194401C/zh
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
    • H01L21/76804—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics by forming tapered via holes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
    • H01L21/76807—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics for dual damascene structures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2221/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof covered by H01L21/00
    • H01L2221/10—Applying interconnections to be used for carrying current between separate components within a device
    • H01L2221/1005—Formation and after-treatment of dielectrics
    • H01L2221/101—Forming openings in dielectrics
    • H01L2221/1015—Forming openings in dielectrics for dual damascene structures
    • H01L2221/1036—Dual damascene with different via-level and trench-level dielectrics

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

Abstract

一种在基底上形成双重金属镶嵌结构的方法，该结构包括一接触窗与一内连线，该方法包括：形成一绝缘层在基底上，接着形成一氧化硅层于该绝缘层上，形成一掩模氧化层于该氮化硅层上，然后以光刻与蚀刻步骤依序除去相对应于该接触窗位置上的绝缘层、该氮化硅层以及该掩模氧化层，再以光刻与蚀刻步骤依序去除相对应于该内连线位置上的该氮化硅层以及该掩模氧化层，然后进行一回流步骤。

Description

形成双重金属镶嵌 结构的方法
本发明涉及一种形成双重金属镶嵌(Dual Damascene)结构的方法，特别是涉及一种结合接触窗开口(Contact)与内连线(Interconnect)的双重金属镶嵌结构的制造方法。
金属镶嵌为一种内连线的制造过程，其在绝缘层中形成沟槽，然后填入金属而形成导线(内连线)。双重金属镶嵌为一种多重内连线制造过程，除了形成金属镶嵌沟槽外，还需形成导电接触窗(或介层窗)开口。在标准双重金属镶嵌制造过程中，在单一或复合的绝缘层(典型的为氧化层)上覆盖一层光致抗蚀剂，经由具有接触窗开口的影像图案的第一光掩模将光致抗蚀剂曝光，并蚀刻该绝缘层。第二光掩模图案则形成内连线图案，然后再蚀刻一次绝缘层。最后，沉积导电材料例如铝或铜，在绝缘层形成的沟槽以及接触窗开口内，此外，也需沉积钛和氮化钛作为阻挡层及粘着层。
但是随着集成电路的密度增加以及双重金属镶嵌结构的缩小，钛或氮化钛愈来愈难以均匀地沉积在深次微米尺寸的接触窗开口内，因此需要新的程序来形成具有接触窗开口与内连线的双重金属镶嵌结构。
本发明的目的在于提供一种双重金属镶嵌结构的方法，在基底上形成接触窗开口与内连线的方法。
本发明的目的是这样实现的，即提供一种形成双重金属镶嵌结构的方法，其包括下列步骤：首先在该基底上形成一绝缘层，然后形成一氮化硅层于绝缘层上，接着形成一掩模氧化层(Cap Oxide)在氮化硅层上，以光刻与蚀刻步骤依序除去对应于接触窗开口位置的掩模氧化层、氮化硅层以及绝缘层，再以光刻与蚀刻步骤依序除去对应于内连线位置的掩模氧化层以及氮化硅层，然后进行一最佳(Optimum)回流(Reflow)步骤。
本发明还提供一种在一基底上形成一接触窗开口与一内连线结构的方法，该方法包括下列步骤：形成一绝缘层于该基底上；形成一氮化硅层于该绝缘层上；形成一掩模氧化层于该氮化硅层上；进行光刻与蚀刻步骤，依序除去相对应于该接触窗开口位置上的部分该绝缘层、该氮化硅层以及该掩模氧化层，形成该接触窗开口；进行光刻与蚀刻步骤，依序除去相对应于该内连线位置上的部分该氮化硅层以及该掩模氧化层，形成该内连线开口；进行一回流程序，使该接触窗开口的边角变得较圆滑；以及填入一金属阻挡层及一导电材料至该内连线开口与该接触窗开口。
本发明方法的优点在于，其能使钛或氧化钛均匀地沉积在深次微米尺寸的接触窗开口内，形成较好的接触窗开口与内连线双重金属镶嵌结构。
为让本发明的上述和其他目的、特征和优点能更明显易懂，下文特举一较佳实施例，并配合附图作详细说明如下：
图1至图4是本发明一较佳实施例的一种双重金属镶嵌接触窗开口与内连线的形成流程剖视图。
见图1至图4，其绘示本发明一较佳实施例的一种形成双重金属镶嵌接触窗开口与内连线的方法流程剖视图。
请参照图1，提供一基底101，该基底例如是半导体晶片、形成在晶片中的主动与被动元件以及形成在晶片表面的薄膜。基底包括在晶片内以及覆盖在晶片上的薄膜所形成的元件，基底表面包括覆盖在晶片上所露出的最外层薄膜，例如基底硅表面、绝缘层以及金属线。
回到图1，在基底101上形成一衬底氧化层103，较佳的是，使用传统的化学气相沉积法沉积一二氧化硅层，沉积的厚度约500至2000埃。
接着，以传统的化学气相沉积法在衬底氧化层103上沉积第一绝缘层105，该绝缘层105例如是硼磷硅玻璃(BPSG)或是磷硅玻璃(PSG)所组成，较佳者为硼磷硅玻璃，沉积的厚度约为3000至8000埃。然后进行全面平坦化程序，例如以化学机械研磨法将第一绝缘层105磨平。
接着，在硼磷硅玻璃层105上沉积氮化硅层107，较佳的是，以传统的化学气相沉积法形成氮化硅层107，厚度大约为300至1000埃。氮化硅层107形成后，以化学气相沉积法在氮化硅层107上沉积第二绝缘层109(称为掩模氧化层)，较佳的是二氧化硅层，厚度约为3000至7000埃。仍参照图1，在第二绝缘层109上覆盖一层光致抗蚀剂111，经光掩模与显影后将所要形成接触窗开口的基底位置上的部分光致抗蚀剂除去，并暴露出第二绝缘层109，形成开口113。
请参照图2，以光致抗蚀剂111为掩模，使用蚀刻法例如反应性离子蚀刻法(RIE)，依序除去开口113底下的第二绝缘层109、氮化硅层107、第一绝缘层105以及衬底氧化层103，直到暴露出基底101，然后除去光致抗蚀剂111，形成接触窗开口102。在本较佳实施例中的接触窗开口102形状为圆柱状，但也可形成其它任何所需的形状。
接着，请参照图3，覆盖第二光致抗蚀剂115在第二绝缘层109上，再经光掩模、显影与蚀刻将所要形成的内连线图案转移到第二绝缘层109与氮化硅层107上，然后除去光致抗蚀剂115，形成双重金属镶嵌开口117(也称为接触窗与内连线开口)。
请参照图4，进行回流步骤，使接触窗开口102的边角变得较圆滑。此回流步骤例如可以使用快速热处理工艺(RTP)，在温度约950至1100℃热处理约10至30秒，或是以常压化学气相沉积(APCVD)灯管，在温度约800至900℃热处理约5至30分钟。此圆滑边角能使在沉积钛或氮化钛阻挡层时有较佳的阶梯覆盖能力，尤其是对于深次微米元件而言。
之后，填入导电材料到双重金属镶嵌开口117内，导电材料包括例如铜或铝。在本较佳实施例中形成阻挡层的制造过程包括沉积钛及氮化钛到双重金属镶嵌开口117内。
虽然以上结合一较佳实施例揭露了本发明，但是其并非限定本发明，本领域的技术人员在不脱离本发明的精神和范围内，可作出各种更动与润饰，因此本发明的保护范围应当由所附的权利要求所限定。

Claims (19)

1．一种形成双重金属镶嵌结构的方法，该结构包括在一基底上形成一接触窗开口与一内连线；其特征在于，该方法包括下列步骤：
形成一绝缘层于该基底上；
形成一氮化硅层于该绝缘层上；
形成一掩模氧化层于该氮化硅层上；
进行光刻与蚀刻步骤，依序除去相对应于该接触窗开口位置上的部分该绝缘层、该氮化硅层以及该掩模氧化层；
进行光刻与蚀刻步骤，依序除去相对应于该内连线位置上的部分该氮化硅层以及该掩模氧化层；以及
进行一回流程序。
2．如权利要求1所述的方法，其特征在于，还包括在该基底与该绝缘层之间形成一衬底氧化层的步骤。
3．如权利要求1所述的方法，其特征在于，还包括使用化学机械研磨法研磨该绝缘层的步骤。
4．如权利要求1所述的方法，其特征在于，该氮化硅层为Si3N4。
5．如权利要求1所述的方法，其特征在于，该绝缘层为硼磷硅玻璃。
6．如权利要求1所述的方法，其特征在于，该绝缘层为磷硅玻璃。
7．如权利要求1所述的方法，其特征在于，该掩模氧化层为二氧化硅。
8．如权利要求1所述的方法，其特征在于，还包括填入一金属阻挡层及一导电材料至该重金属镶嵌结构的步骤。
9．如权利要求1所述的方法，其特征在于，该回流步骤是使用快速热处理制造工艺法，操作温度约为950至1100℃，热处理时间约为10至30秒。
10．如权利要求1所述的方法，其特征在于，该回流步骤是以常压化学气相沉积法进行，操作温度约为800至900℃，热处理时间约为5至30分钟。
11．一种在一基底上形成一接触窗开口与一内连线结构的方法，其特征在于，该方法包括下列步骤：
形成一绝缘层于该基底上；
形成一氮化硅层于该绝缘层上；
形成一掩模氧化层于该氮化硅层上；
进行光刻与蚀刻步骤，依序除去相对应于该接触窗开口位置上的部分该绝缘层、该氮化硅层以及该掩模氧化层，形成该接触窗开口；
进行光刻与蚀刻步骤，依序除去相对应于该内连线位置上的部分该氮化硅层以及该掩模氧化层；形成该内连线开口；
进行一回流程序，使该接触窗开口的边角变得较圆滑；以及
填入一金属阻挡层及一导电材料至该内连线开口与该接触窗开口。
12．如权利要求11所述的方法，其特征在于，还包括在该基底与该绝缘层之间形成一衬底氧化层的步骤。
13．如权利要求11所述的方法，其特征在于，还包括使用化学机械研磨法研磨该绝缘层的步骤。
14．如权利要求11所述的方法，其特征在于，该氮化硅层为Si3N4。
15．如权利要求11所述的方法，其特征在于，该绝缘层为硼磷硅玻璃。
16．如权利要求11所述的方法，其特征在于，该绝缘层为磷硅玻璃。
17．如权利要求11所述的方法，其特征在于，该掩模氧化层为二氧化硅。
18．如权利要求11所述的方法，其特征在于，该回流步骤是使用快速热处理制造工艺法，操作温度约为950至1100℃，热处理时间约为10至30秒。
19．如权利要求11所述的方法，其特征在于，该回流步骤是以常压化学气相沉积法进行，操作温度约为800至900℃，热处理时间约为5至30分钟。
CNB981168531A 1998-06-03 1998-08-04 形成双重金属镶嵌结构的方法 Expired - Lifetime CN1194401C (zh)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US09/089,875 US6074942A (en) 1998-06-03 1998-06-03 Method for forming a dual damascene contact and interconnect
US089,875 1998-06-03
US089875 1998-06-03

Publications (2)

Publication Number Publication Date
CN1237651A true CN1237651A (zh) 1999-12-08
CN1194401C CN1194401C (zh) 2005-03-23

Family

ID=22220021

Family Applications (1)

Application Number Title Priority Date Filing Date
CNB981168531A Expired - Lifetime CN1194401C (zh) 1998-06-03 1998-08-04 形成双重金属镶嵌结构的方法

Country Status (3)

Country Link
US (1) US6074942A (zh)
CN (1) CN1194401C (zh)
TW (1) TW388106B (zh)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN105533950A (zh) * 2016-02-05 2016-05-04 深圳市金城银域珠宝首饰有限公司 贵金属的多圈纹加工工艺及多圈纹饰品

Families Citing this family (30)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP3657788B2 (ja) * 1998-10-14 2005-06-08 富士通株式会社 半導体装置及びその製造方法
US6200906B1 (en) * 1998-12-17 2001-03-13 Micron Technology, Inc. Stepped photoresist profile and opening formed using the profile
US6734564B1 (en) * 1999-01-04 2004-05-11 International Business Machines Corporation Specially shaped contact via and integrated circuit therewith
US6211071B1 (en) * 1999-04-22 2001-04-03 Advanced Micro Devices, Inc. Optimized trench/via profile for damascene filling
US6197681B1 (en) * 1999-12-31 2001-03-06 United Microelectronics Corp. Forming copper interconnects in dielectric materials with low constant dielectrics
TW584917B (en) * 2000-01-06 2004-04-21 Matsushita Electric Ind Co Ltd Method of forming interconnect
US6355556B1 (en) * 2000-09-29 2002-03-12 Vanguard International Semiconductor Corp. Method for fabricating transistor
US6271128B1 (en) * 2000-09-29 2001-08-07 Vanguard International Semiconductor Corp. Method for fabricating transistor
US6878615B2 (en) * 2001-05-24 2005-04-12 Taiwan Semiconductor Manufacturing Company, Ltd. Method to solve via poisoning for porous low-k dielectric
US8046832B2 (en) * 2002-06-26 2011-10-25 Microsoft Corporation Spam detector with challenges
US6689695B1 (en) 2002-06-28 2004-02-10 Taiwan Semiconductor Manufacturing Company Multi-purpose composite mask for dual damascene patterning
US7246227B2 (en) * 2003-02-10 2007-07-17 Symantec Corporation Efficient scanning of stream based data
US7249162B2 (en) * 2003-02-25 2007-07-24 Microsoft Corporation Adaptive junk message filtering system
US7543053B2 (en) * 2003-03-03 2009-06-02 Microsoft Corporation Intelligent quarantining for spam prevention
US7219148B2 (en) 2003-03-03 2007-05-15 Microsoft Corporation Feedback loop for spam prevention
US7483947B2 (en) * 2003-05-02 2009-01-27 Microsoft Corporation Message rendering for identification of content features
US7272853B2 (en) * 2003-06-04 2007-09-18 Microsoft Corporation Origination/destination features and lists for spam prevention
US7519668B2 (en) * 2003-06-20 2009-04-14 Microsoft Corporation Obfuscation of spam filter
US7711779B2 (en) * 2003-06-20 2010-05-04 Microsoft Corporation Prevention of outgoing spam
US8533270B2 (en) 2003-06-23 2013-09-10 Microsoft Corporation Advanced spam detection techniques
US8214438B2 (en) * 2004-03-01 2012-07-03 Microsoft Corporation (More) advanced spam detection features
US20050204006A1 (en) * 2004-03-12 2005-09-15 Purcell Sean E. Message junk rating interface
US20050204005A1 (en) * 2004-03-12 2005-09-15 Purcell Sean E. Selective treatment of messages based on junk rating
US7664819B2 (en) * 2004-06-29 2010-02-16 Microsoft Corporation Incremental anti-spam lookup and update service
US7904517B2 (en) * 2004-08-09 2011-03-08 Microsoft Corporation Challenge response systems
US7660865B2 (en) * 2004-08-12 2010-02-09 Microsoft Corporation Spam filtering with probabilistic secure hashes
KR100641553B1 (ko) * 2004-12-23 2006-11-01 동부일렉트로닉스 주식회사 반도체 소자에서 패턴 형성 방법
US7930353B2 (en) * 2005-07-29 2011-04-19 Microsoft Corporation Trees of classifiers for detecting email spam
US8772157B2 (en) * 2012-11-02 2014-07-08 Shanghai Huali Microelectronics Corporation Method of forming Cu interconnects
CN114032033B (zh) * 2021-11-26 2022-08-05 万华化学集团电子材料有限公司 一种高效、高精度硅片抛光组合物及其制备方法和应用

Family Cites Families (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5453403A (en) * 1994-10-24 1995-09-26 Chartered Semiconductor Manufacturing Pte, Ltd. Method of beveled contact opening formation
US5741626A (en) * 1996-04-15 1998-04-21 Motorola, Inc. Method for forming a dielectric tantalum nitride layer as an anti-reflective coating (ARC)
US5801094A (en) * 1997-02-28 1998-09-01 United Microelectronics Corporation Dual damascene process

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN105533950A (zh) * 2016-02-05 2016-05-04 深圳市金城银域珠宝首饰有限公司 贵金属的多圈纹加工工艺及多圈纹饰品

Also Published As

Publication number Publication date
CN1194401C (zh) 2005-03-23
TW388106B (en) 2000-04-21
US6074942A (en) 2000-06-13

Similar Documents

Publication Publication Date Title
CN1237651A (zh) 形成双重金属镶嵌结构的方法
US5801095A (en) Production worthy interconnect process for deep sub-half micrometer back-end-of-line technology
US5691238A (en) Subtractive dual damascene
US20050191851A1 (en) Barrier metal cap structure on copper lines and vias
US7803713B2 (en) Method for fabricating air gap for semiconductor device
US6734097B2 (en) Liner with poor step coverage to improve contact resistance in W contacts
US6495448B1 (en) Dual damascene process
US7163887B2 (en) Method for fabricating a semiconductor device
TW536806B (en) Semiconductor device and method of manufacturing thereof
US6248665B1 (en) Delamination improvement between Cu and dielectrics for damascene process
KR20040096322A (ko) 반도체 소자의 금속배선 형성방법
US6734101B1 (en) Solution to the problem of copper hillocks
JPH10284600A (ja) 半導体装置及びその製造方法
US5966632A (en) Method of forming borderless metal to contact structure
JPH11312734A (ja) 半導体ウエハの絶縁層バイア内の銅層への接点を形成する方法及び構造
JP4207113B2 (ja) 配線構造の形成方法
KR100443148B1 (ko) 반도체소자의 제조방법
US6340638B1 (en) Method for forming a passivation layer on copper conductive elements
KR100268515B1 (ko) 접촉구형성방법
JP2000323569A (ja) 半導体集積回路装置およびその製造方法
JP3745460B2 (ja) 半導体装置の配線形成方法
JP2002184858A (ja) 半導体素子の製造方法
KR100307985B1 (ko) 반도체 장치 및 그 제조방법
KR100450241B1 (ko) 플러그 형성 방법 및 이 플러그를 갖는 반도체 소자
TW413899B (en) Manufacturing process of unlanded via

Legal Events

Date Code Title Description
C06 Publication
PB01 Publication
C10 Entry into substantive examination
SE01 Entry into force of request for substantive examination
C53 Correction of patent of invention or patent application
CB02 Change of applicant information

Applicant after: Taiwan Semiconductor Manufacturing Co., Ltd.

Applicant before: Shida Integrated Circuit Co., Ltd.

COR Change of bibliographic data

Free format text: CORRECT: APPLICANT; FROM: SHIDA INTEGRATED CIRCUIT CO., LTD. TO: TAIWAN SEMICONDUCTOR MFG

C14 Grant of patent or utility model
GR01 Patent grant
CX01 Expiry of patent term
CX01 Expiry of patent term

Granted publication date: 20050323