CN1212452A

CN1212452A - Three-dimensional read-only memory

Info

Publication number: CN1212452A
Application number: CN98119572.5A
Authority: CN
Inventors: 张国飙
Original assignee: Individual
Current assignee: Zhang Guobiao; Chengdu Haicun IP Technology LLC; Hangzhou Haicun Information Technology Co Ltd
Priority date: 1998-09-24
Filing date: 1998-09-24
Publication date: 1999-03-31
Anticipated expiration: 2018-09-24
Also published as: AU5406199A; CN1099695C; WO2000019537A1

Abstract

The present invention provides a read-only memory whose storage elements are arranged in three-dimensional space. These storage elements are distributed on several storage layers respectively, and these storage layers are mutually overlapped, one layer is superposed on another layer, and on every storage layer there are several adress-selecting wires and storage elements. These storage elements maybe mask programmable of field programmable, and are arranged in the three-dimensional space, its storage density and storage capacity can be greatly raised. Said invented three-dimensional ROM is short in access time, can be made up by using standard semiconductor production process, and can be extensively used in several fields.

Description

Three-dimensional read-only memory

This application is a chinese patent application corresponding to U.S. patent application No. 08/732,902, filed 10/17/1996.

The present invention relates to the field of integrated circuits, and more particularly, to a read only memory in an integrated circuit and a method of manufacturing the same.

A read-only memory is a device that stores fixed information that is programmed at the time of manufacture or at the time of use by the user. Conventional read-only memories are arranged in a two-dimensional array on a semiconductor substrate. At each cross point of the array there is a memory element that provides a resistive, inductive, capacitive, diode type or coupling mechanism using active elements. Each cell represents a bit of digital information. Meanwhile, each memory cell is connected with the input and the output through an electric signal, so that extremely short access time can be ensured. Read-only memories are divided into two categories: one is mask-programmed read only memory (MPROM) and the other is field-programmed read only memory (EPROM). The MPROM information is controlled by a mask at the time of manufacture, and the EPROM information is written by a user.

U.S. patent 5,429,968 to Koyoma (7/4 of 1995) is an example of the existing MPROM technology. The method uses a field effect transistor as a storage element, and digital information in the storage element is changed by adjusting the threshold voltage of the field effect transistor. By adjusting the ion implantation amount, the field effect transistors at different positions become enhancement type or depletion type. At a suitable voltage, the enhancement mode fet is on and the depletion mode fet is on. By detecting the current on different bit lines, digital information at different locations can be read. Since these field effect transistors can be formed only on a semiconductor substrate, this MPROM can be arranged only in a two-dimensional structure.

EPROM, on the other hand, generally uses a resistive coupling mechanism to represent digital information. Representative resistive coupling mechanisms include fuses (fuses) and antifuses (antifuses). U.S. patent 4,899,205 to Hamdy et al (1990, 6/2) describes a two-dimensional EPROM that utilizes a silicon-silicon antifuse as the programming element. In this configuration, the source/drain of the antifuse and the access fet are integrated together to form a memory cell. Because the access fets must be grown on a semiconductor substrate, EPROMs using silicon-silicon antifuses can only be arranged in a two-dimensional array. With this structure, the amount of digital information per unit area on the chip is limited by the size of the access fet. U.S. Pat. No. 4,442,507 to Roesner et al (4.10.4 1984) describes another field-programmable read-only memory. It uses a schottky diode stack as the memory cell. One of the address select lines is formed of polysilicon and the other of the address select lines is formed of aluminum. Since the growth temperature of polysilicon requires at least 600 c, the maximum temperature that aluminum can withstand is 450 c. Polysilicon cannot grow on top of aluminum. Therefore, this memory can use only one layer of EPROM. That is, the storage density is limited.

As described above, since the memory cells of the read only memory in the related art are formed on the substrate made of a semiconductor material, that is, the related art can only arrange the memory cells in the integrated circuit in a two-dimensional space, the storage density of the read only memory is greatly limited. In addition, the word lines formed by polysilicon in the prior art have the defects of large resistivity and slow access speed.

In order to improve the storage density of a read-only memory in an integrated circuit, the inventor sets the storage elements in a three-dimensional form on the basis of changing the construction materials of the storage elements from the viewpoint of improving the setting dimension of the storage elements, thereby improving the storage density and the access speed. To generate memory cells in three dimensions means that the read-only memory has a plurality of stacked memory layers, each memory layer having a plurality of memory cells and corresponding word and bit lines. The stacking of multiple storage layers requires that the lower storage layer must provide a good foundation for the upper storage layer. With the advent of Chemical Mechanical Polishing (CMP) technology, this requirement can be easily met.

The first purpose of the invention is to provide a new type of read-only memory cell generated in three dimensions;

a second object of the present invention is to provide a three-dimensional read-only memory;

the third purpose of the invention is to provide a manufacturing method of the three-dimensional read-only memory.

In order to solve the above problems in the prior art, the present invention provides a three-dimensional read-only memory cell, a three-dimensional read-only memory having the same, and a method for manufacturing the same.

The read-only memory element of the invention comprises: a first electrode comprising a metallic material; a second electrode containing a metal material; and a quasi-conductive film sandwiched between the first and second electrodes.

The three-dimensional read-only memory of the present invention comprises: a semiconductor substrate and an address selector formed on the semiconductor substrate, characterized by further comprising: at least one read-only memory layer stacked on the substrate, each read-only memory layer comprising: a plurality of first and second address select lines comprising a metal material; a plurality of read-only memory cells, each memory cell including a first electrode connected to a first address select line and a second electrode connected to a second address select line; an interlayer insulating film between the adjacent two read-only memory layers; and a plurality of interlayer connection via holes and contact via holes formed between the read-only memory layer and the semiconductor substrate for providing connection between the read-only memory layer and the semiconductor substrate.

The manufacturing method of the three-dimensional read-only memory comprises the following steps: 1) forming an address selector and other transistor circuits on a semiconductor substrate; 2) forming an insulating dielectric film on the semiconductor substrate on which the address selector is formed; 3) forming a contact via hole and an interlayer connection via hole in the insulating dielectric film; 4) forming a first memory layer on the insulating dielectric film on which the contact via hole and the interlayer connection via hole are formed; 5) forming an insulating film on the first memory layer; 6) forming an interlayer connection channel port on the insulating film, and 7) forming a second memory; repeating steps 5) to 7) to form a plurality of memory layers.

Because both electrodes of the read-only memory cell are made of metal materials, the read-only memory cell not only does not occupy space on a semiconductor substrate and enables the manufacture of a three-dimensional read-only memory, but also has the advantages of small resistivity and higher storage speed compared with a memory cell with at least one electrode made of semiconductor materials.

The read-only memory of the invention arranges the memory element on the three-dimensional space, thus greatly improving the storage density and capacity of the memory, and because the three-dimensional read-only memory of the invention can be integrated with other semiconductor circuits, thus improving the data/instruction transmission rate between them and shortening the access time.

The manufacturing process of the three-dimensional read-only memory of the invention can be compatible with the conventional semiconductor manufacturing process. Thus, it can be manufactured using standard semiconductor manufacturing equipment and processes.

The three-dimensional read-only memory and the method for manufacturing the same according to the present invention will be described in detail with reference to the accompanying drawings. Wherein,

fig. 1 is a perspective view showing a 3D-ROM having two memory layers.

FIG. 2 is a circuit diagram showing a 3D-MPROM chip on a substrate. The circuit provides addressing and reading functions.

Figure 3 is a circuit diagram showing a 3D-EPROM chip substrate. The circuit provides addressing, programming and reading functions.

FIG. 4 is a sectional view showing a 3D-ROM cell.

Fig. 5A to 5C are cross-sectional views showing several MPROM films.

FIGS. 6A to 6E are cross-sectional views showing several 3D-MPROM cells.

FIG. 7 shows a 4X 4 memory cell array under a condition of the hardest read case, with O representing 0 and X representing 1.

FIG. 8 is a volt-ampere characteristic curve representing a logic "0" and a logic "1" of a 3D-MPROM film.

Fig. 9A is a cross-sectional view depicting a first EPROM film; fig. 9B is a cross-sectional view depicting a second EPROM film;

fig. 9C is a cross-sectional view depicting a third EPROM film.

FIG. 10A is a cross-sectional view showing a 3D-EPROM cell; figure 10B is a cross-sectional view showing another 3D-EPROM cell.

Fig. 11 shows the volt-ampere characteristic curves of the quasi-conducting film, antifuse film, and EPROM film.

FIG. 12A is a plan view showing a first wiring in a 3D-ROM storage layer;

FIG. 12B is a plan view showing a second wiring in a 3D-ROM storage layer;

FIG. 12C is a plan view showing a third wiring in a 3D-ROM storage layer.

FIG. 13 is a sectional view showing a first 3D-ROM memory structure.

FIG. 14 is a sectional view showing a second 3D-ROM memory structure.

FIGS. 15A to 15B are sectional views showing a third 3D-ROM memory structure.

FIG. 1 shows a 2X 23D-ROM. Here, the notation l × m × n3D-ROM refers to a 3D-ROM having l memory layers, m word lines, and n bit lines. This 3D-ROM is grown on a semiconductor substrate 10 which has two memory layers 100, 200. The substrate surface is set to be an XY plane, and each memory layer plane is parallel to the substrate surface. The storage layer 200 is stacked on top of the storage layer 100, i.e., stacked in the Z direction. Each memory layer is composed of a 2X 2 memory cell array, two address selection lines in the X direction, and two address selection lines in the Y direction. The address selection lines in the X direction are referred to as word lines, and they include word lines 101, 102 on the memory layer 100 and word lines 201, 202 on the memory layer 200. The address selection lines in the Y direction are referred to as bit lines, and include

bit lines

111 and 112 on the memory layer 100 and

bit lines

211 and 212 on the memory layer 200. Memory cells, such as 121-124, 221-224, are provided at the intersections of the word lines and bit lines. Each memory cell is capable of storing a bit of binary information and provides a coupling mechanism between the word line and the bit line. Such coupling mechanisms include resistive, inductive, capacitive, diode-type or coupling mechanisms using active elements. Each cell represents a bit of binary information by changing the size of the coupling mechanism. The address select lines provide a program/read path for selected memory cells.

Fig. 1 also shows the way in which the substrate 10 is connected to the address selection lines in the different memory layers. In the memory layer 100, the word lines 101, 102 are connected to the substrate 10 at contact points 131, 132 through contact via holes 101a, 102 a. On the other hand, the

bit lines

111, 112 are connected to the substrate 10 at

contacts

141, 142 via contact vias 111a, 112 a. Similarly, in the memory layer 200, the word lines 201, 202 are connected to the substrate 10 at contact points 231, 232 through contact via holes 201a, 202 a. On the other hand, the

bit lines

211, 212 are connected to the substrate 10 at

contacts

241, 242 through contact via holes 211a, 212 a. In order to connect the memory layer 200 and the substrate 10, the address selection lines need to be extended, for example, the bit lines 211 must extend beyond the contact via holes 111a until the contact via holes 211a, so that the bit lines 111 or the contact via holes 111a are not damaged.

Fig. 2 shows a circuit diagram of an address/read of a2 x 23D-MPROM. Because the addressing and reading functions are performed by transistors, the addressing/reading circuit needs to be built on a semiconductor substrate 10. It consists of a Z address decoder 190, two X address decoders 160, 260 and two Y address decoders 170, 270. The Z address decoder 190 has an X address input 191, a Y address input 192, and a Z address input 193. These inputs are connected to input pins of the semiconductor chip or to some other circuit.

To address/read the information stored in a memory cell (e.g., cell 121 of FIG. 1), X, Y and the Z address inputs 191, 192, 193 must be supplied with appropriate voltages so that the voltage applied to cell 121 is equal to the read voltage V_R. On the Z address input 193The added level signal can realize the connection of the following two electric signals: one between X address input 191 and X address input 1(161) and the other between Y address input 192 and Y address input 1 (171). Therefore, when the address signal on the X address input 191 and the address signal on the Y address input 192 are input to the X address decoders 1(160) and the Y address decoders 1(170), respectively, only the voltage of the address line on the memory layer 100 changes accordingly. At the same time, the level signal on the Z address input 193 enables a connection between the outputs 1(164) of the X address decoders 1(160) and the output 196 of the Z address decoder 190.

The address signal at X address decoder 1(160) raises the voltage at contact point 131 to read voltage V_RHalf of (A), V_R/2. At the same time, the address signal at Y address decoder 1(170) drops the voltage at contact 141 to the negative 1/2 read voltages, -V_R/2. The voltage on the word line 101 is thus also raised to V by contacting the via holes 101a and 111a_R/2, the voltage on bit line 111 falls to-V_R/2. Thus, a read voltage V_RAre added at both ends of the memory element 121. There is a different current on the word line 101 for different states of the memory element 121. The output signal passes from output 1(164) to output 196 and then to the output pin. Thus, the information stored in the storage element 121 can be read out.

Fig. 3 is a circuit diagram of an address/read/program showing a2 x 2 3D-EPROM. Similar to the circuit of fig. 2, this circuit is also formed on a semiconductor substrate 10. It includes a Z address decoder 190, two X address decoders 160, 260 and two Y address decoders 170, 270. In addition to X, Y, Z address inputs 191, 192, 193, the Z address decoder 190 includes an output 196, a program enable PGM195, one voltage that is one-half the program voltage (V)_PP/2) and a voltage that is one-half the negative programming voltage (-V)_PP/2) power source 198.

The read operation of the 3D-EPROM is similar to the read operation of the 3D-MPROM. Programming of the 3D-EPROM may be performed, for example, by inputting the Z address to program cell 224 of FIG. 1IN 193 shall be X address input 191, Y address input 192, V_PP/2 Power supply 197, -V_PPThe/2 power supply 198 and PGM195 are connected to their respective terminals at the X address decoder 2(260) and the Y address decoder 2 (270). The wordline 202 and bitline 212 are then selected by signals at X, Y on the address line through

contacts

232, 242. When PGM195 is selected, the voltage of word line 202 is raised to V_PP/2, the voltage on bit line 212 drops to-V_PPAnd/2, while the other address lines are grounded. Because the memory cell 224 is located at the intersection of the word line 202 and the bit line 212, the voltage applied thereto is a programming voltage V_PP. Thus, memory element 224 is programmed. On the other hand, the voltage applied to the other memory cells is only V_PPAnd/2, they continue in their unprogrammed state.

FIG. 4 shows a cross-sectional view of a 3D-ROM cell of the present invention. It has a top electrode 501, a ROM film 502, a bottom electrode 503, and a field region 504. The top electrode 501 is used as an address line, for example, as a bit line. It is composed of a metallic material. The metallic material is a metallic element, a metallic alloy or a metallic compound, such as aluminum or copper, having a thickness of 0.2 to 2 μm, preferably 0.5 μm. Between the top electrode 501 and the ROM film 502, there may also be a barrier metal film, such as TiW. This barrier film prevents a reaction between the top electrode 501 and the ROM film 502. The bottom electrode 503 may be used as another address line, such as a word line. It also comprises a metallic material, such as aluminum or copper, having a thickness of between 0.2 and 2 μm, preferably 0.5 μm. There may also be a barrier film, such as TiW, between the bottom electrode 503 and the ROM film 502. This barrier film prevents a reaction between the bottom electrode 503 and the ROM film 502.

ROM film 502 represents the digital information stored in this memory element. In MPROM the ROM film is called MPROM film. If the MPROM film is in a high resistance state at the read voltage, it represents "0" logic. Accordingly, the MPROM film of "0" logic is referred to as a blocking film. On the other hand, if the MPROM film is in a low resistance state at the read voltage, it represents "1" logic. Accordingly, the MPROM film of "1" logic is referred to as a quasi-conducting film. The reason for using the "quasi-conducting film" will be explained in more detail in fig. 7 and 8.

In EPROM, the ROM film is called EPROM film. The EPROM film contains a quasi-conducting film and an antifuse film. The quasi-conducting film has the same characteristics as those of the 3D-MPROM. The anti-fuse film is in a high resistance state before programming and it irreversibly converts to a low resistance state after programming. For a factory EPROM chip, the antifuse film is intact. Thus, the EPROM film is in a high resistance state and represents "0" logic, and the antifuse film becomes a low resistance state after programming, and accordingly, the EPROM film becomes a quasi-conductive film and represents "1" logic. The different memory cells are separated from each other by field regions 504. Field region 504 is composed of an insulating material (e.g., silicon oxide). The thickness is between 0.2 and 2 μm, preferably 0.5 μm.

Fig. 5A to 5C show several MPROM films.

Fig. 5A shows an MPROM film suitable as a "0" logical memory cell. The MPROM film comprises an insulating dielectric 502a which blocks the flow of current, such as silicon oxide formed by PECVD, and has a thickness of 0.02-2 μm, preferably 0.5 μm.

Fig. 5B to 5C show two MPROM films suitable as "1" logic. It contains a quasi-conducting film. The quasi-conductive film has a nonlinear resistance characteristic: a) it is in a low resistance state at the read voltage; b) its resistance increases significantly when subjected to a voltage that is less than or opposite in magnitude to the read voltage. This will be explained in detail in fig. 7 and 8.

Fig. 5B shows a quasi-conducting film 502B used as "1" logic. It contains amorphous silicon and has a thickness of 5-500 nm, preferably 100 nm. Amorphous silicon can be formed by, for example: sputtering, and luminous discharge. If the address line is made of a refractory metal, i.e. it can withstand a higher temperature thermal treatment, polysilicon can be used as the quasi-conducting film. The amorphous silicon film may be undoped or doped. Since amorphous silicon has an exponential volt-ampere characteristic, it can satisfy the requirements for aligning the volt-ampere characteristic of the conducting film as set forth in the above discussion, in general. On the other hand, protective ceramic materials, particularly protective oxides, also have exponential volt-ampere curves, and therefore, they can also be used as the quasi-conducting film 502 b. Protective ceramic material is understood here to mean a ceramic material having a Piiling-Bedworth ratio of more than 1 (J. Shackelford, "Introduction to Materials Science for Engineers", second edition, p. 609-610, 1988). Some examples of protective ceramic materials include oxides of Be, Cu, Al, Cr, Mn, Fe, Co, Pd, Pb, Ce, Sc, Zn, Zr, La, Y, Nb, Rh, and Pt. The protective ceramic material can be formed generally by: 1. and (4) a deposition method. Such as CVD, sputtering; 2. the method is shown in the specification. For example, thermal oxidation, plasma oxidation, anodic oxidation, and the like. The protective ceramic material has a thickness of 2-200 nm, preferably 10 nm. Other materials that may be used for the quasi-conductive film 502b include amorphous germanium, carbon, silicon carbide, and the like.

Fig. 5C shows another quasi-conducting film 502b as a "1" logic memory cell. It is made of an amorphous silicon p-n junction diode. If the address lines are refractory metals, polysilicon p-n junction diodes may be used. The p-layer 502bb and the n-layer 502ba have a thickness of 20 to 300nm, preferably 60 nm. The resistance difference between the positive direction and the negative direction of the p-n junction is extremely large, so that the p-n junction diode can meet the condition of a quasi-conducting film. Accordingly, it may serve as a "1" logical storage element. In addition to the p-n junction diode, a p-i-n junction may also be used as the quasi-conducting film 502 b. The benefits of using a p-n junction or a p-i-n junction will be discussed in more detail in fig. 7 and 8.

Fig. 6A to 6E show the structures of several 3D-MPROM memory cells. FIG. 6A is suitable for "0" logic, and FIGS. 6B-6E are suitable for "1" logic or "0" logic, preferably "1" logic.

Fig. 6A shows a cross-section of a memory cell. This memory cell is suitable for "0" logic, and accordingly, the MPROM film 502 is a barrier film 502 a. This blocking film may be an extension of field region 504. It may be formed of a thick insulating material. No current passes between the top electrode 501 and the bottom electrode 503 because of the barrier film. Therefore, a high resistance is exhibited between the top electrode 501 and the bottom electrode 503.

Fig. 6B to 6E show cross-sectional views of four other types of 3D-MPROM memory cells. They have a similar structure to metal-metal antifuse cells. A via hole 505 is formed in the field region 504, and then the MPROM film 502 is formed inside, below, or above the via hole 505. Depending on the logic state of this memory cell, the MPROM film may be a blocking film representing "0" logic or a quasi-conducting film of "1" logic.

FIG. 6B shows a cross-sectional view of a 3D-MPROM cell. Here, the MPROM film 502 is formed in the via hole 505. The process for manufacturing this memory cell is as follows: first, the bottom electrode 503 is formed, then the field region film 504 is deposited, and the field region film 504 is etched to form the via hole 505, after which the MPROM film 502 and the top electrode 501 are sequentially formed inside the via hole 505, and finally the top electrode 501 and the MPROM film 502 are etched to shape.

FIG. 6C shows a cross-sectional view of another 3D-MPROM cell. Here, the MPROM film 502 is formed over the via hole 505. The process for manufacturing this memory cell is as follows: first, a bottom electrode 503 is formed, a field region 504 is deposited, a via hole 505 is etched, then a hole plug 506 made of, for example, tungsten is filled in the via hole 505, and the tungsten and the material of the surrounding field region 504 are polished, and finally, an MPROM film 502 and a top electrode 501 are deposited and etched.

FIG. 6D shows a cross-sectional view of another 3D-MPROM cell. Here, the MPROM film 502 is formed under the via hole 505. The process for manufacturing this memory cell is as follows: the bottom electrode 503 and MPROM film 502 are first formed, then the field region film 504 is deposited and the via hole 505 is etched. After the via hole 505 is formed, a part of the upper surface of the MPROM film 502 is exposed. Finally a top electrode film is deposited and the top electrode 501 is etched away.

FIG. 6E shows a cross-sectional view of another 3D-MPROM cell. The difference between this cell and the cell in fig. 6D is that a top buffer film 508 is formed between the MPROM film 502 and the top electrode plate 501. The top buffer film 508 contains a conductor, such as tungsten, having a thickness of 50-500 nm, preferably 100 nm. The top buffer film serves to prevent the MPROM film 502 from being excessively etched when the channel hole 505 is opened.

FIG. 7 shows an n memory cell array in the most unreadable state. At this point, the memory cell to be read is 600aa, which is in a "0" logic state, and all other memory cells are in a "1" logic state. As an example, during a read, the voltage on word line 400a is raised to V_R/2, the voltage on bit line 500a drops to-V_RAnd/2, all other addressing lines are suspended. FIG. 8 shows the volt-ampere characteristics curves for a ROM in the "0" logic state and a ROM in the "1" logic state. For "0" logic and "1" logic memory cells, there is a non-linear relationship between current and voltage, with the reverse current being less than or approximately equal to the forward current. The benefits of this volt-ampere characteristic will be discussed in detail below.

When reading memory cell 600aa ("0" logic), the voltage on word line 400a is V_R/2, the voltage on bit line 500a is-V_R/2, therefore, the contribution of the current through memory cell 600aa to the current on word line 400a is

I_600aa=I_{Logic of "0}(V_R) There are other currents on the word line 400a, which come from other lines, such as 600ab → 600bb → 600 ba. If a single amorphous silicon film is used as the quasi-conducting film 502b, its reverse volt-ampere characteristic curve is similar to that of the forward volt-ampere characteristic curve. In this case, the voltage drop across each "1" logic cell, e.g., 600ab, 600bb, 600ba, is approximately 1/3 read voltages. Therefore, the leakage current through the wiring 600ab → 600bb → 600ba is about I_{Logic of "1}(V_R/3). Since there are n × n memory cells in the memory layer, there are n drain lines like 600ab → 600bb → 600ba in the most difficult case to read. Thus, in the most difficult case to read, the other current on word line 400a is approximately

I_Others≈I_{Logic of "1}(V_R/3)×n.

Overall, the current on word line 400a for the "0" logic case is

I_{"0" logic word line}≈I_600aa+I_Others=I_{Logic of "0}(V_R)+I_{Logic of "1}(V_R/3)×n.

In another most difficult case to read, the word line current of the "1" logic is

I_{"1" logic word line}=I_{Logic of "1}(V_R). This most difficult case means that the memory cell of interest is in a "1" logic state, while the remaining memory cells are in a "0" logic state. These memory cells in the "0" logic state contribute little to the word line current.

To distinguish between "0" logic and "1" logic, we wish to

I_{"1" logic word line}＞I_{"0" logic word line}

Namely, it is

I_{Logic of "1}(V_R)＞I_{Logic of "0}(V_R)+I_{Logic of "1}(V_R/3)×n.

In general I_{Logic of "0}(V_R)＜＜I_{Logic of "1}(V_R) And therefore, as an estimate,

since the storage capacity in one storage layer is n²Equation (1) provides an estimate of the storage capacity in a storage layer.

The magnitude of the storage capacity depends on the non-linear characteristic of the volt-ampere characteristic of the quasi-conducting film according to equation (1). If the quasi-conducting film has an exponential volt-ampere characteristic curve, the read-only memory can have a large capacity.

The quasi-conducting film has a higher resistance (fig. 8) if the voltage applied to the quasi-conducting film is in the opposite direction to the read voltage, for example, an amorphous silicon p-n junction diode. For "0" logic in the hardest state, the current will be smaller. This is because for a leakage circuit such as 600ab → 600bb → 600ba, the voltage experienced at 600bb is a reverse voltage, and therefore the leakage current is much smaller than I_{Logic of "1}(V_R/3). Accordingly, n may be much larger than the upper limit set by equation (1), that is, the storage capacity may be larger.

Fig. 9A to 11 are descriptions about the 3D-EPROM. The 3D-EPROM and the 3D-MPROM are different in that: all 3D-EPROM cells have the same structure, and they are initially in a "0" logic state, or unprogrammed state; the user can selectively program the address to transition to a "1" logic state. The EPROM film contains a quasi-conducting film and an antifuse film. And the quasi-conducting film and the 1 logic in the 3D-MPROM become low resistance after quasi-conducting. Some examples are given in fig. 9A to 9C.

Figure 9A shows EPROM film 502c of a 3D-EPROM cell. It contains a quasi-conducting film 502cb and an antifuse film 502 ca. This quasi-conducting film 502cb is similar to the quasi-conducting film used in 3D-MPROM, such as the quasi-conducting film shown in fig. 5B. The antifuse film 502ca is made of amorphous silicon or a protective ceramic, for example, chromium oxide having a thickness of 3 to 100nm, preferably 10 nm. Fig. 11 shows the volt-ampere characteristic curves of the quasi-conducting film 502cb, the antifuse film 502ca, and the unprogrammed EPROM film 502 c. Antifuse film 502ca at a suitable programming voltage V_PPAnd a programming current I_PIs programmed. Selecting an appropriate V_PPAnd I_PIn order to avoid damage to the quasi-conducting film 502 cb. The antifuse film 502ca is converted to a low resistance state after programming, and accordingly, the volt-ampere curve of the EPROM film is similar to that of the quasi-conducting film 502 cb. Thus, the memory element enters a "1" logic state.

Figure 9B shows another EPROM film 502c of a 3D-EPROM. Here EPROM film 502c includes a p-n junction diode 502cb and antifuse film 502 ca. This p-n junction diode 502cb (i.e., the quasi-conducting film) is similar to the p-n junction diode shown in fig. 5C. It consists of a p-doped silicon region 502cbb and an n-doped silicon region 502cba, with a thickness of between 50-500 nm, preferably 60 nm. The antifuse film 502ca may be formed under or over the quasi-conductive film. This 3D-EPROM operates like the 3D-EPROM in FIG. 9A, except that the p-n junction diode has a more desirable turn-on characteristic.

Figure 9C shows another EPROM film 502C of a 3D-EPROM. Here, an intermediate buffer film 502cc is embedded between the quasi-conducting film 502cb and the antifuse film 502 ca. It is made of a refractory metal, for example tungsten, with a thickness of between 10nm and 2 μm. During the programming of the antifuse film 502ca, local joule heat is generated. This Joule heat raises the temperature of antifuse film 502 ca. After the intermediate buffer film 502cc is added, it is prevented from generating thermal damage to the alignment via film 502 cb. The programming and reading operations of this cell are similar to the cell in fig. 9A and 9B.

The structure of fig. 6A to 6E can be used for the 3D-EPROM memory cell, except that the quasi-conducting film 502b in fig. 6A to 6E is replaced with the EPROM film 502 c. For the EPROM film in fig. 9C, fig. 10A and 10B show some other corresponding EPROM cell structures. The positions of the quasi-via film 502cb and the antifuse film 502ca in fig. 10A and 10B may be interchanged, as will be apparent to those skilled in the art.

Fig. 10A shows a memory cell of a 3D-EPROM. It has a bottom electrode 503, a quasi-conducting film 502cb, an intermediate buffer film 502cc, an antifuse film 502ca, and a top electrode 501. The manufacturing steps comprise: depositing and etching a bottom electrode 503 and a quasi-conductive film 502 cb; depositing an insulating dielectric film 504; etching the insulating dielectric film 504 to form a window 505 to expose a portion of the quasi-conductive film 502 cb; the middle of the window 505 is filled with an intermediate transition film 502cc, and finally an antifuse film 502ca and a top electrode 501 are formed. Figure 10B shows another 3D-EPROM cell. The manufacturing steps of the memory element are as follows: depositing a bottom electrode 503, a quasi-conductive film 502cb and an intermediate buffer film 502 cc; etching the intermediate buffer film 502cc and the quasi-conductive film 502 cb; etching the bottom electrode 503; depositing a field region dielectric film 504; etching the field region dielectric film 504 to form a via hole 505 to expose a portion of the intermediate buffer film 502 cc; finally, the antifuse film 502ca and the top electrode 501 are deposited and etched.

FIGS. 12A-12C show top views of several layouts in a 3D-ROM storage layer. In these layouts, word lines 450 a-450 d are in the X direction and bit lines 470 a-470 c are in the Y direction. Contact via holes 460 a-460 d provide connections between word lines and transistors on the substrate.

FIG. 12A shows a first layout where all contact via holes 460 a-460 d fall on a straight line. FIG. 12B shows a second layout, where the contact via holes are divided into two groups: group a 460a and 460 c; group B460B and 460 d. The group B of contact via holes are spaced a distance from the group A of contact via holes so that all of the contact via holes 460 a-460 d fall on two straight lines. The design of the decoder can be made simpler as the contact via holes become more sparse relative to each other. FIG. 12C shows a third layout, in which the contact via holes are also divided into two groups: c groups 460a and 460C; d groups 460b and 460D. The contact channel holes of the C group and the D group are arranged at two ends of the word line, so that the design of the address selector becomes simpler.

FIG. 13 shows a cross-sectional view of a 3D-ROM memory. Here, a 3D-MPROM structure is taken as an example. The process of manufacturing this memory includes: a transistor is first formed on a semiconductor substrate 10. Those skilled in the art will appreciate that these transistors can be fabricated by standard semiconductor process flows. These transistors provide the address/read function. An insulating dielectric film 20 is formed on the substrate 10 on which the transistor is formed. This insulating dielectric film 20 may be silicon oxide or some other more advanced dielectric system. These more advanced media systems can fill the voids more successfully. The insulating dielectric film 20 may be planarized using a method such as CMP. After that, the contact via hole 101a and the interlayer connection via 201a3 are formed by RIE or the like. A conductor is formed on this planarized surface, and then the first word line 101 is formed by pattern conversion, and a pedestal 201a2 is also formed. The word line 101 may contain a highly conductive metal such as aluminum or copper. Another insulating film 30 is formed on the word line 101 and planarized. At this time, digital information is transferred onto the insulating film 30 by pattern transfer, and if "0" logic and "1" logic are to be generated at

addresses

123 and 121, respectively, the reticle patterns at 123 and 121 should be opaque and transparent, respectively. So that only the resist film on 121 is removed after exposure. A via hole is formed by RIE and a portion of the word line 101 is exposed. The quasi-conductive film 121 and the

bit lines

111 and 112 are formed next. After that, another insulating film 40 is formed on the

bit lines

111 and 112, which can be planarized by a method such as CMP and provides a flat basis for the second memory layer 200.

The second memory layer 200 can be formed in a similar manner, but requires an additional step to form the interlayer connection via 201a 1. 201a1 provides a connection between the wordlines 201 on the storage layer 200 and the pedestals 201a2 on the storage layer 100. Accordingly, the second memory layer 200 is electrically connected to the substrate 10 through the contact via hole 201 a. After the second memory layer is formed, the CMP polishing technique continues to be used to planarize the wafer surface. Repeating the above steps to manufacture a multi-layer 3D-ROM.

The above description is given by way of example for the memory cell of fig. 6A and 6B, and it will be appreciated by those skilled in the art that the above process steps and structures can be used for the memory cells of fig. 6C-6E as well.

FIG. 14 shows a cross-sectional view of another 3D-ROM memory. Taking a 3D-MPROM as an example, it can be seen from fig. 2 that the X, Y addressor occupies a certain area. Accordingly, the distance between the contact points 131 and 231 must exceed a certain value. In order to maintain the storage capacity of the 3D-ROM, at least one wiring layer 109b may be added between the substrate 10 and the first storage layer 100. This wiring layer 109b removes the contact point 131 on the storage layer 100 from the contact point 231 of the storage layer 200. Thus saving more chip area. Accordingly, the storage capacity can also be increased.

FIGS. 15A to 15B are sectional views showing another 3D-ROM memory. Here, by connecting the address selection lines on different layers together in series, the number of contact points between the address lines and the substrate 10 can be reduced. As the number of contacts decreases, the complexity of the addressor decreases accordingly. Accordingly, the manufacturability of the 3D-ROM is also improved. Using the method in FIGS. 13 and 14, a l × m × n3D-ROM has l × (m + n) contact points. But for a memory of l x m x n, the minimum number of contacts can beFor example, a 4 × 3 × 3D-ROM may use only 6 word line contacts and 6 bit line contacts.

Fig. 15A shows a cross-sectional view of the 3D-ROM memory perpendicular to bit lines 482a to 482D. In this 3D-ROM there are four storage layers 500 a-500D. The word lines 480a to 480d are divided into two groups: group a 480a and 480 b;

b groups

480c and 480 d. The word lines in each group are connected together in series and share a common contact via to the substrate 10. For example, word lines 480b and 480a are connected together by metal plugs 490b and then to substrate 10 by contact via holes 490 a. Similarly,

word lines

480d and 480c are connected together by metal plugs 490d and then to substrate 10 by contact via holes 490 c. FIG. 15B shows a cross-sectional view of the 3D-ROM memory perpendicular to the word lines 480 a-480D. Bit lines 482a 482d are divided into two groups: c groups 482a and 482C; d groups 482b and 482D. The bitlines in each group are connected together in series and share a common contact via to the substrate 10. For example,

bit lines

482c and 482a are connected together by metal plugs 492c and then to substrate 10 by contact via holes 492 a. Similarly,

bit lines

482d and 482b are connected together by metal plug 492d and then connected to substrate 10 by contact via hole 492 b. Overall, the number of bit line and word line contacts to the substrate 10 can be halved using this method.

FIGS. 13-15B illustrate the structure of a 3D-MPROM by way of example for a 3D-MPROM. These structures are also applicable to 3D-EPROM. The only difference is that for all memory cells of the 3D-EPROM, a window is etched and an EPROM film is formed; the EPROM film contains a quasi-conducting film and an antifuse film instead of only the quasi-conducting film as in the 3D-MPROM. In addition, all manufacturing process steps are applicable.

The 3D-ROM memory has extremely large storage capacity, so that the 3D-ROM memory can be applied to many fields. For example, today computers use most of their hard disk space to store software, which is rarely changed, and thus much of the hard disk resources are wasted. The use of CD-ROMs can partially alleviate this problem, but the read time of CD-ROMs is very long. The 3D-ROM memory has a large storage capacity and a fast read time and is therefore an ideal device for storing software. A computer using 3D-ROM to store software may relax the requirements on the capacity of the hard disk. When a 3D-ROM memory is used as a storage element of computer software, a separate 3D-ROM memory chip may be used or the 3D-ROM may be integrated on a Central Processing Unit (CPU). Another application of 3D-ROM memory is the sensitive card, also called security card. Sensitive cards can store a large amount of personal information and can replace identification cards, telephone cards, credit cards, and the like in the near future. Some information in sensitive cards needs to be permanently retained and other information needs to be replaced at any time, so the MPROM0, EPROM and other non-volatile memories, such as E, of the present invention can be used²PROM, integrated on a single 3D-ROM chip, and using it as a sensitive card. For example, E²The PROM and the addressor of the present invention can be formed on a semiconductor substrate, and then the MPROM and EPROM of the present invention can be formed thereon. Because the MPROM and EPROM of the invention have low cost and high integration level, the invention can reduce the cost of the MPROM and the EPROM²PROM, MPROM and EPROM are the markets in the near future where sensitive cards integrated together in three-dimensional form may find themselves.

Although the foregoing description specifically describes certain examples of the present invention, it will be understood by those skilled in the art that changes in form and detail may be made therein without departing from the spirit and scope of the invention, for example, the above description of the embodiments is based on positive logic and those skilled in the art will appreciate that the present invention may also be used with negative logic if the "0" logic and "1" logic are interchanged. The invention, therefore, is not to be restricted except in the spirit of the appended claims.

Claims

1. A read-only memory cell in an integrated circuit, comprising: a first electrode (501) comprising a metal material; a second electrode (503) comprising a metal material; and a quasi-conductive film (502) sandwiched between the first and second electrodes.

2. The read-only memory cell of claim 1, wherein: the quasi-conductive film (502) is formed of a semiconductor material.

3. The read-only memory cell of claim 2, wherein: the semiconductor material is carbon, silicon, germanium, tin and gallium arsenide.

4. The read-only memory cell of claim 2, wherein: the semiconductor material is doped.

5. The read-only memory cell of claim 1, wherein: the quasi-conducting film (502) has a higher resistance when the direction of the voltage on the memory cell is opposite to the direction of the read voltage.

6. The read-only memory cell of claim 5, wherein: the quasi-conducting film (502b) is composed of a first semiconductor film (502ba) and a second semiconductor film (502bb), wherein the first semiconductor film (502ba) and the second semiconductor film (502bb) are counter-doped.

7. The read-only memory cell of claim 1, wherein: the quasi-conductive film (502) has a non-single crystal structure.

8. The read-only memory cell of claim 1, further comprising: an antifuse film (502ca) formed between the first electrode (501) and the second electrode (503).

9. The read-only memory cell of claim 8, further comprising: and a buffer film (502cc) formed between the antifuse film (502ca) and the quasi-conductive film (502cb), the buffer film (502cc) containing a metal material.

10. The read-only memory cell of claim 8, wherein: the antifuse film (502ca) contains non-single-crystal silicon.

11. The read-only memory cell of claim 8, wherein: the antifuse film (502ca) comprises a protective ceramic material.

12. A three-dimensional read-only memory comprising a semiconductor substrate (10) and an addressor formed on the semiconductor substrate, characterized by further comprising: at least one read-only memory layer (100, 200, … …) stacked on said substrate (10), each read-only memory layer comprising: a plurality of read-only memory cells (121, 122, 123, 124 … …), each memory cell including a first electrode (501) connected to a first address select line (111, 112 … …) and a second electrode (503) connected to a second address select line (101, 102 … …); an interlayer insulating film (40) between the adjacent two read-only memory layers; and a plurality of contact via holes and interlayer connection via openings (101a, 102a, 111a, 112a, 201a, 202a … …) formed between the read-only memory layer (100, 200, 300) and the semiconductor substrate (10) for providing connection between the read-only memory layer (100, 200, 300) and the semiconductor substrate (10).

13. The three-dimensional read-only memory of claim 12, wherein: a quasi-conducting film (502) is arranged between a first electrode (501) and a second electrode (503) of at least one memory cell.

14. The three-dimensional read-only memory according to claim 12, further comprising: an antifuse film (502ca) formed between a first electrode (501) and a second electrode (503) of the memory cell.

15. The three-dimensional read-only memory of claim 12, wherein: the read-only memory layer further includes a plurality of word lines (450a, 450b … …) and first contact via holes (460a, 460b … …) and the like, the word lines being coupled to the semiconductor substrate 10 through the first contact via holes; the semiconductor substrate having a plurality of first contact points at which the first contact via holes are in contact with the semiconductor substrate; the first contact points fall on at least one straight line.

16. The three-dimensional read-only memory of claim 12, wherein: the read-only memory layer further has a plurality of bit lines (470a, 470b … …) and second contact via holes, the bit lines being connected to the semiconductor substrate (10) through the second contact via holes; the semiconductor substrate has a plurality of second contact points at which the second contact via holes are in contact with the semiconductor substrate; the plurality of second contact points fall on at least one straight line.

17. The three-dimensional read-only memory of claim 12, wherein: the total number of read-only storage layers is greater than 2 and includes: a first read-only memory layer (100) and a second read-only memory layer (200), the first read-only memory layer having first word lines and first bit lines and being coupled to a first addressor on the substrate (10); the second read-only memory layer contains second word lines and second bit lines and is coupled to a second addressor on the substrate (10).

18. The three-dimensional read-only memory according to claim 17, further comprising: at least one wiring layer coupled to address select lines on the first read-only memory layer (100) and coupled to a first addressor on the substrate (10); the wiring layer is coupled to address select lines on the second read-only memory layer (200) and to a second addressor on the substrate (10).

19. The three-dimensional read-only memory of claim 17, wherein: the first word line and the second word line are connected together in series.

20. The three-dimensional read-only memory of claim 17, wherein: the first bit line and the second bit line are connected together in series.

21. The three-dimensional read-only memory of claim 12, wherein: the interlayer insulating film (40) is planarized.

22. A method for manufacturing a three-dimensional read-only memory comprises the following steps:

1) forming an address selector and other transistor circuits on a semiconductor substrate (10);

2) forming an insulating dielectric film (20) on a semiconductor substrate (10) on which an address selector is formed;

3) forming contact via holes (101a, … …) and interlayer connection via holes (201a3, … …) in the insulating dielectric film (20);

4) forming a first memory layer (100) on the insulating dielectric film on which the contact via hole and the interlayer connection via hole are formed;

5) forming an insulating film (40) on the first memory layer (100);

6) forming interlayer connection via holes (201a1, … …) in the insulating film (40), and

7) forming a second storage layer (200);

repeating steps 5) to 7) to form a plurality of memory layers.

23. The method of claim 22, further comprising the steps of:

2') planarizing the insulating dielectric film (20) after forming the same; and

5') planarizing the insulating film (40) after forming the insulating film.