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CN1298046C - Wafer processing method by forming combination viscosity on grain surface - Google Patents

Wafer processing method by forming combination viscosity on grain surface Download PDF

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Publication number
CN1298046C
CN1298046C CNB021304971A CN02130497A CN1298046C CN 1298046 C CN1298046 C CN 1298046C CN B021304971 A CNB021304971 A CN B021304971A CN 02130497 A CN02130497 A CN 02130497A CN 1298046 C CN1298046 C CN 1298046C
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CN
China
Prior art keywords
wafer
tool
colloid
processing method
grain
Prior art date
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Expired - Fee Related
Application number
CNB021304971A
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Chinese (zh)
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CN1477696A (en
Inventor
林俊宏
黄国樑
陈光辉
周世文
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
BERMUDA CHIPMOS TECHNOLOGIES Co Ltd
Chipmos Technologies Inc
Original Assignee
BERMUDA CHIPMOS TECHNOLOGIES Co Ltd
Chipmos Technologies Inc
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Application filed by BERMUDA CHIPMOS TECHNOLOGIES Co Ltd, Chipmos Technologies Inc filed Critical BERMUDA CHIPMOS TECHNOLOGIES Co Ltd
Priority to CNB021304971A priority Critical patent/CN1298046C/en
Publication of CN1477696A publication Critical patent/CN1477696A/en
Application granted granted Critical
Publication of CN1298046C publication Critical patent/CN1298046C/en
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/27—Manufacturing methods
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    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/3201—Structure
    • H01L2224/32012—Structure relative to the bonding area, e.g. bond pad
    • H01L2224/32014—Structure relative to the bonding area, e.g. bond pad the layer connector being smaller than the bonding area, e.g. bond pad
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    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
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    • H01L2224/321—Disposition
    • H01L2224/32135—Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/32145—Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
    • H—ELECTRICITY
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    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
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    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
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    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
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    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/4824—Connecting between the body and an opposite side of the item with respect to the body
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    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
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    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/4826—Connecting between the body and an opposite side of the item with respect to the body
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    • H01L2224/732—Location after the connecting process
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    • H01L2224/73215—Layer and wire connectors
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    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73265—Layer and wire connectors
    • H—ELECTRICITY
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    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/8319—Arrangement of the layer connectors prior to mounting
    • H01L2224/83191—Arrangement of the layer connectors prior to mounting wherein the layer connectors are disposed only on the semiconductor or solid-state body
    • H—ELECTRICITY
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    • H01L2224/91—Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L2224/80 - H01L2224/90
    • H01L2224/92—Specific sequence of method steps
    • H01L2224/921—Connecting a surface with connectors of different types
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    • H01L2224/92147—Sequential connecting processes the first connecting process involving a layer connector the second connecting process involving a wire connector
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    • H01L2224/91—Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L2224/80 - H01L2224/90
    • H01L2224/92—Specific sequence of method steps
    • H01L2224/922—Connecting different surfaces of the semiconductor or solid-state body with connectors of different types
    • H01L2224/9222—Sequential connecting processes
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    • H01L2224/92247—Sequential connecting processes the first connecting process involving a layer connector the second connecting process involving a wire connector
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    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/14—Integrated circuits
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    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA

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  • Engineering & Computer Science (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Application Of Or Painting With Fluid Materials (AREA)
  • Container, Conveyance, Adherence, Positioning, Of Wafer (AREA)

Abstract

The present invention relates to a wafer processing method by forming combination viscosity on grain surfaces. After one surface of a wafer is printed with one layer of colloid with two-stage property, the wafer is pre-baked, the colloid with two-stage property is solidified at ordinary temperature and has no flowability and viscosity for being turned over or being adsorbed by a grain-sticking machine, after the wafer is cut into grains, the grain surface has thermal bonding viscosity for being stuck on a base plate, and the base plate can be another grain, or a printed circuit board, or a ceramic circuit board, or a conductor wire frame. The present invention is wide used for sticking base plates during stacking wafers or various packages because of the low cost and the high efficiency.

Description

Form the wafer processing method of combination viscosity at grain surface
Technical field
The present invention relates to the treatment technology of wafer after finishing integrated circuit, particularly about a kind of wafer processing method that forms combination viscosity at grain surface.
Background technology
Finish integrated circuit and cut into crystal grain [die] at semiconductor crystal wafer, difference according to the encapsulation kenel is pasted on substrate miscellaneous, as be pasted on another crystal grain to form polycrystalline sheet stacked body, be pasted on printed circuit board (PCB) lead frame or in pasting with the encapsulation of carrying out sphere grid array [Ball Grid Array] the crystalline substance pad or in draw finger and encapsulate [Thin Small Outline Package] or quad flat package [Quad Flat Package] approach little outward appearance, the crystal grain sticker of commonly using is the liquid thermosetting elargol (sliver Paste) or the solid-state adhesive tape of pi [polyimide].
A kind of assemble method of polycrystalline sheet module is described in No. 2001/005935 patent of United States Patent (USP), it will be attached at a substrate with sticking brilliant machine than wafer earlier, again a less wafer is fixed in this than on the wafer, and be a kind of liquid thermosetting viscose glue or solid-state adhesive tape than the sticker of wafer and less wafer in order to cementation, yet fail to disclose sticker and be to be coated with earlier and impose on less wafer or than the order of wafer and sticking brilliant and routing, in fact, when sticker is selected a kind of liquid thermosetting viscose glue for use, because the liquid thermosetting viscose glue still has flowability when pasting, impose on less wafer [going up wafer] and the easy weld pad that pollutes than wafer [lower wafer] so can't be coated with in advance, simultaneously if must carry out before routing when desiring on printing liquid thermosetting viscose glue than wafer, because the bonding wire that routing forms can't be placed half tone again, make that the processing restriction of polycrystalline sheet encapsulation is quite a lot of, if sticker is selected a kind of solid-state adhesive tape for use, not only cost is higher, when the polycrystalline sheet encapsulates, solid-state adhesive tape has biadhesive, in case be pasted on the lower surface of less wafer, promptly make less wafer have viscosity, overturn as wafer, move or the shaping and the location of adhesive tape, the viscosity that is not suitable for wafer scale is handled, in order on each wafer, to adhere to an adhesive tape devices needed and a spended time, all be not inconsistent cost simultaneously.
Summary of the invention
Main purpose of the present invention is to provide a kind of wafer processing method that forms combination viscosity at grain surface, utilization large tracts of land on wafer is coated with the viscose glue of a tool two stage property, and the viscose glue of roasting in advance this tool two stage property, it is become in room temperature reach solid-state B stage (B-stage) glued membrane that does not have flowability and viscosity, this wafer that overturns makes this B stage glued membrane contact to a location adhesive tape, after cutting, can obtain a large amount of a plurality of crystal grain, to reduce sticking brilliant cost with viscosity.
Of the present invention time a purpose is to provide a kind of wafer processing method that forms combination viscosity at grain surface, the viscose glue that forms a tool two stage property is printed in utilization on wafer, and the viscose glue of roasting in advance this tool two stage property, it is become in room temperature reach solid-state B stage (B-stage) glued membrane that does not have flowability and viscosity, after cutting, can obtain having the crystal grain of thermal viscosity, it has good machinability, for the semiconductor packages manufacturing of various kenels.
It is a kind of at the wafer processing method of grain surface formation in conjunction with stickiness that a purpose more of the present invention is to provide, its step includes: a wafer is provided, this wafer has an active surface, wherein is formed with a plurality of weld pads on this active surface, and this wafer has a plurality of Cutting Roads with definition crystal grain; At the colloid of the local printing of this active surface last layer tool two stage property of this wafer, this two stage colloid be appear described weld pad and when printing cording flowability is arranged; Pre-roasting this wafer becomes a mobile B stage glued membrane with viscosity of tool not at room temperature up to the colloid of this tool two stage property on this wafer; And cut this wafer along described Cutting Road, have crystal grain with formation in conjunction with stickiness.
To achieve the above object, according to the wafer processing method that forms combination viscosity at grain surface of the present invention, one semiconductor crystal wafer of finishing integrated circuit at first is provided, this wafer has a surface, it can be active surface or non-active surface, evenly be coated with the colloid of one deck tool two stage property on this surface of this wafer, as with screen painting (screen printing), steel version printing (stencil Printing) or centrifugal coating (spin coating) make the colloid part of these tool two stages or coat this surface of this wafer fully, in a preferred embodiment, the colloid of this tool two stage property is this surface that this wafer is coated in the part, with Cutting Road or the weld pad that does not cover wafer, roasting in advance afterwards this wafer, the colloid of this tool two stage property is become in room temperature reach solid-state B stage (B-stage) glued membrane of not having flowability and viscosity, typical temperature carried out roasting 1 hour in advance for about 125 ℃, at this moment, the colloid of this tool two stage property is fully hot curing reaction and have the viscosity of thermal yet, processing for upset or sticking brilliant machine absorption, after cutting into crystal grain, obtain the crystal grain that the surface is formed with thermal viscosity, to affix to a substrate, this substrate can be another crystal grain, printed circuit board (PCB), ceramic circuit board or lead frame, the stickup of substrate when extensively applying to wafer stacking or various encapsulation with low-cost high-efficiency ground.
Description of drawings
Fig. 1: the flow chart that forms the brilliant figure processing method of combination viscosity at grain surface of the present invention;
Fig. 2: according to the wafer processing method at grain surface formation combination viscosity of the present invention, the front view of the wafer that provides;
Fig. 3 A to 3F: according to first specific embodiment of the present invention, the schematic cross-section of flow process in the wafer processing method of grain surface formation combination viscosity;
Fig. 4 A to 4F: according to second specific embodiment of the present invention, the schematic cross-section of flow process in the wafer processing method of grain surface formation combination viscosity;
Fig. 5: according to the 3rd specific embodiment of the present invention, the sticking schematic cross-section of being located at locating adhesive tape for cutting of the non-active surface of wafer in the wafer processing method of grain surface formation combination viscosity;
Fig. 6:, form the sticking schematic cross-section of establishing a lead frame of the crystal grain that has cut in the wafer processing method of combination viscosity at grain surface according to the 3rd specific embodiment of the present invention; And
Fig. 7:, form the schematic cross-section that the crystal grain that has cut in the wafer processing method of combination viscosity is applied to an encapsulating structure at grain surface according to the 3rd specific embodiment of the present invention.
Embodiment
See also appended graphicly, the present invention will enumerate following embodiment explanation:
As shown in Figure 1, the key step that comprises at the wafer processing method of grain surface formation combination viscosity of the present invention has: " wafer is provided " 11, " colloid of applying implenent two stage property " 12, " roasting in advance wafer " 13, " upset wafer " 14 reach " cutting crystal wafer ", and details are as follows for it:
Shown in Fig. 2 and 3A, one wafer 110 at first is provided in the step of " wafer is provided " 11, this wafer 110 has an active surface 112 (activesurface) that is formed with integrated circuit and weld pad 115, the non-active surface 111 of one correspondence (inactive surface) and a plurality of crystal grain 113 that also is one that do not separate, wherein weld pad 115 is positioned at the periphery of crystal grain 113, around crystal grain 113 is straight Cutting Road 114, demand according to encapsulation procedure, the surface that wafer 110 desires form viscosity can be active surface 112 or non-active surface 111, in the present embodiment, form viscosity if be predefined in the non-active surface 111 of wafer 110, then this non-active surface 111 up, then, carry out the step of " colloid of applying implenent two stage property " 12, shown in Fig. 3 B, with screen painting (screen printing), the colloid 130 that the steel version is printed (stencil Printing) or centrifugal coating (spin coating) method is local or coating forms a kind of tool two stage property fully, it places a half tone 121 at the non-active surface 111 of wafer 110 earlier, colloid 130 with scraper 122 that this tool is mobile again and the tool two stage property prints to this non-active surface 111, in the present embodiment, half tone 121 covers the Cutting Road 114 of wafer 110, make colloid 130 parts of this tool two stage property be printed in this non-active surface 111 of this wafer 110 and not cover Cutting Road 114, in first embodiment the crystal grain of the local combination viscosity of the tool that forms be for wafer stacking, so in the present embodiment, the thickness of the colloid 130 of this tool two stage property is about 5-6mil during printing, the colloid 130 of tool two stage property presents different qualities at different conditions, it includes thermosetting polymer, as pi [Polyimide], poly quinoline [Polyquinolin] or benzocyclobutene [benzocyclobutene], and can include the solvent that can dissolve above-mentioned thermosetting resin, as the mixed solvent or 1 of fourth lactones [butyrolactone] with cyclopentanone [cyclopentanone], 3,5-trimethylbenzene [mesitylene] etc., because this two stage colloid 130 has the characteristic of A stage [A-stage] when spreading, it is in a liquid state and has adequate liquidity, in order to printed and formed.
Then, carry out the step of " roasting in advance wafer " 13, shown in Fig. 3 C, wafer 110 is positioned over a baking box, be heated to a proper temperature, 90-150 ℃ Celsius according to appointment about one hour, desolvate to remove, this is the colloid 130 at the tool two stage property that contains epoxy compounds, different thermosetting polymers should be adjusted its suitable pre-roasting temperature and condition, make the colloid 130 of the tool two stage property on the non-active surface 111 of wafer 110 form a kind of dry film of not having a flowability, preferably, when comprising solvent, can carry out in the colloid 130 of two stage of tool row vacuumize heating in addition, to remove solvent fully, at this moment, colloid 130 at the tool two stage property of wafer 110 has the characteristic of B stage (B-stage), promptly at room temperature do not have mobile and sticking glued membrane, in the present embodiment, Tg 〉=40 of the colloid 130 of tool two stage property ℃, Tg is glass transition temperature (glass transition temperature), Stackable is carried or is stored, and helps the processing of follow-up encapsulation, yet still has the viscosity of thermal [thermalbonding].
Then, carry out the step of " upset wafer " 14, shown in Fig. 3 D, with wafer 110 upsets, make non-active surface 111 down and conform to one the location adhesive tape 140, this locating adhesive tape 140 is a kind of crystal grain locating adhesive tape commonly used when cutting crystal wafer, as polyvinyl chloride film [polyvinyl chloridemembrane], its upper surface has viscosity and is bonded to a framework, at this moment, colloid 130 these locating adhesive tapes 140 of contact and the viscosity of tool two stage property are provided by this locating adhesive tape 140, behind fixing wafer 110, carry out the step of " cutting crystal wafer " 15, utilization is cut the cutting tool 150 of brilliant machine along Cutting Road 114 cutting crystal wafers 110, to constitute a plurality of crystal grain 113 with thermal viscosity, not only can low cost provide fast also and can use for various encapsulation, for example: shown in Fig. 3 E, earlier another crystal grain 160 is adhered to a substrate 170, and routing electrically connects the weld pad 161 of crystal grain 160 to substrate 170 with bonding wire 162, this crystal grain 113 with thermal viscosity got up with sticking brilliant machine [die bonder] absorption and adhere to another crystal grain 160 with the colloid 130 of this tool two stage property, usually its hot pressing temperature is about 120 to 170 ℃, only need the time of several seconds, even can finish a wafer stacking body [shown in Fig. 3 F] less than one second, the colloid 130 of this tool two stage property hot curing reaction fully yet after bonding, then, routing electrically connects the weld pad 115 of crystal grain 113 to substrate 170 with bonding wire 180, of the present invention at wafer processing method that grain surface forms combination viscosity except can be for the wafer stacking bonding, also can be for the sticking brilliant combination of general encapsulation, step at " colloid of applying implenent two stage property " 12, be coated with the colloid of formation one deck tool two stage property fully in the non-active surface of wafer with centrifugal coating or comprehensive printing process, and through pre-roasting, upset is with behind the cutting step, obtain a plurality of crystal grain that have thermal viscosity at non-active surface, for being bonded to a substrate, because the colloid of tool two stage property does not flow if having height as the elargol of commonly using after pre-baking.Therefore, the connection gasket of substrate and the interval of intergranule can be shortened, and make the size of substrate further dwindle, to be applicable to wafer size encapsulation [Chip Scale Package].
Understand the print surface that the present invention does not limit to wafer for making, in second specific embodiment, shown in Fig. 4 A, one wafer 210 at first is provided, this wafer 210 has one and is formed with weld pad 215[or projection] active surface 211, the non-active surface 212 of one correspondence and a plurality of crystal grain 213, wherein weld pad 215 is at the middle position of corresponding crystal grain 213, this active surface 211 up, afterwards, shown in Fig. 4 B, form a kind of colloid 230 of tool two stage property in active surface 211 with screen painting or the printing process of steel version, it places a half tone 221 at the active surface 211 of wafer 210 earlier, colloid 230 with scraper 222 that this tool is mobile again and the tool two stage property prints to this active surface 212, in the present embodiment, half tone 221 covers the weld pad 215 of wafers 210, makes colloid 230 parts of this tool two stage property be printed in this active surface 212 of this wafer 210, and in the present embodiment its thickness of colloid 230 that prints this tool two stage property about 1-2mil.
Then, shown in Fig. 4 C, pre-roasting this wafer 210, make the colloid 230 of the tool two stage property on the active surface 211 of wafer 210 form a kind of dry film of not having a flowability, promptly at room temperature become and do not have mobile and viscosity the glued membrane of (Tg 〉=40 ℃), Stackable is carried or is stored, but still has the viscosity of thermal [thermal bonding].Then, shown in Fig. 4 D, with wafer 210 upsets, make active surface 211 down and conform to one the location adhesive tape 240, behind fixing wafer 210, utilize cutting tool 250 along Cutting Road 214 cutting crystal wafers 210, to constitute a plurality of crystal grain 213 that have thermal viscosity at active surface 211, not only can low cost provide fast also and can use for various encapsulation, for example: shown in Fig. 4 E, this crystal grain 213 with thermal viscosity is adhered to substrate just like printed circuit board (PCB) 260 or ceramic circuit board with sticking brilliant machine absorption and with the colloid 230 of this tool two stage property, about 120 to 175 ℃ of its hot pressing temperature only needs time of several seconds, i.e. quick-binding to a substrate, and through routing bonding wire 262, pressing mold adhesive body 263 and in conjunction with behind the soldered ball 261, be construed as a sphere grid array [BGA] encapsulating structure (shown in Fig. 4 F].
In addition, in the 3rd specific embodiment of the present invention, its leading portion step is as Fig. 4 A to 4C of second specific embodiment, afterwards, as shown in Figure 5, behind pre-roasting this wafer 210, directly the non-active surface 212 with wafer 210 affixes to a location adhesive tape 240, the active surface 211 of its wafer 210 up, after cutting into other crystal grain 213, as shown in Figure 6, absorption crystal grain 213 to one microscope carriers 272, again with a LOC[Lead-On-Chip] lead frame in draw and refer to that 271 down paste the colloid 230 of this tool two stage property, with in conjunction with wafer 213 and lead frame with pin 270, form bonding wire 274 at routing, pressing mold forms adhesive body 273 and lead frame is pruned after the shaping, and prepare the encapsulating structure of a kind of thin little outward appearance encapsulation (Thin SmallOutline Package) or quad flat package [Quad Flat Package], as shown in Figure 7, therefore, of the present invention form the wafer processing method of combination viscosity at grain surface can be in a large number and make at low cost and have the encapsulation procedure of the crystal grain of thermal viscosity for back segment.
Though the present invention discloses as above with preferred embodiment; right its is not in order to qualification the present invention, any those who are familiar with this art, without departing from the spirit and scope of the invention; when can doing a little change and retouching, so the present invention's protection range is as the criterion when looking claims scope person of defining.

Claims (17)

1, a kind of wafer processing method at grain surface formation combination viscosity, it is characterized in that: its step includes:
One wafer is provided, and this wafer has a surface;
At this surface coated one deck tool flowability of this wafer and the colloid of tool two stage property;
Pre-roasting this wafer makes the colloid of this tool two stage property on this wafer become a mobile B stage glued membrane with viscosity of tool not at room temperature;
This wafer that overturns makes the contact of this B stage glued membrane to a location adhesive tape; And
Cut this wafer, have the crystal grain of combination viscosity with formation.
2, the wafer processing method at grain surface formation combination viscosity as claimed in claim 1 is characterized in that: the colloid that forms this tool two stage property with screen painting, the printing of steel version or centrifugal coating process.
3, the wafer processing method at grain surface formation combination viscosity as claimed in claim 1, it is characterized in that: this surface of this wafer is an active surface.
4, the wafer processing method at grain surface formation combination viscosity as claimed in claim 1, it is characterized in that: this surface of this wafer is a non-active surface.
5, the wafer processing method at grain surface formation combination viscosity as claimed in claim 4, it is characterized in that: in the step of " being coated with the colloid of a tool two stage property ", the colloid of this tool two stage property is completed into this surface in this wafer.
6, the wafer processing method that forms combination viscosity at grain surface as claimed in claim 3, it is characterized in that: wherein in the step of " being coated with the colloid of a tool two stage property ", the colloid of this tool two stage property is Cutting Road or the weld pad that does not cover this wafer.
7, the wafer processing method at grain surface formation combination viscosity as claimed in claim 1, it is characterized in that: in the step of " being coated with the colloid of a tool two stage property ", the colloid of this tool two stage property is this surface that the part is formed at this wafer.
8, the wafer processing method at grain surface formation combination viscosity as claimed in claim 1, it is characterized in that: after the step of " cutting this wafer ", the step that other comprises has: adsorb this crystal grain and adhere to a substrate with this B stage glued membrane.
9, as claimed in claim 8 it is characterized in that: this substrate is a crystal grain at the wafer processing method of grain surface formation in conjunction with stickiness, to constitute the chip stack body.
10, as claimed in claim 8 at the wafer processing method of grain surface formation in conjunction with stickiness, it is characterized in that: this substrate is printed circuit board (PCB) or the ceramic substrate with circuit pattern.
11, as claimed in claim 8 at the wafer processing method of grain surface formation in conjunction with stickiness, it is characterized in that: this substrate is a lead frame.
12, a kind of at the wafer processing method of grain surface formation in conjunction with stickiness, its step includes:
One wafer is provided, and this wafer has an active surface, wherein is formed with a plurality of weld pads on this active surface, and this wafer has a plurality of Cutting Roads with definition crystal grain;
At the colloid of the local printing of this active surface last layer tool two stage property of this wafer, this two stage colloid be appear described weld pad and when printing cording flowability is arranged;
Pre-roasting this wafer becomes a mobile B stage glued membrane with viscosity of tool not at room temperature up to the colloid of this tool two stage property on this wafer; And
Cut this wafer along described Cutting Road, have crystal grain in conjunction with stickiness with formation.
13, as claimed in claim 12 at the wafer processing method of grain surface formation in conjunction with stickiness, it is characterized in that: be the colloid that forms this tool two stage property with screen painting or the printing process of steel version.
14, as claimed in claim 12ly form wafer processing method, it is characterized in that in conjunction with stickiness at grain surface: in the step of " printing the colloid of a tool two stage property ", the colloid of this tool two stage property is the Cutting Road that does not cover this wafer.
15, as claimed in claim 12 at the wafer processing method of grain surface formation in conjunction with stickiness, it is characterized in that: in the step of " wafer is provided ", described weld pad is the central authorities that are positioned at each crystal grain.
16, as claimed in claim 12 at the wafer processing method of grain surface formation in conjunction with stickiness, it is characterized in that: in the step of " wafer is provided ", described weld pad is the periphery that is positioned at each crystal grain.
17, as claimed in claim 12 at the wafer processing method of grain surface formation in conjunction with stickiness, it is characterized in that: in the step of " wafer is provided ", each crystal grain has a plurality of projections on this active surface of this wafer.
CNB021304971A 2002-08-21 2002-08-21 Wafer processing method by forming combination viscosity on grain surface Expired - Fee Related CN1298046C (en)

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US20050249945A1 (en) * 2004-05-10 2005-11-10 Wen Kun Yang Manufacturing tool for wafer level package and method of placing dies
CN112542423A (en) * 2021-01-07 2021-03-23 扬州杰利半导体有限公司 Semiconductor crystal grain separation processing technology

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JPS58196031A (en) * 1982-05-11 1983-11-15 Nec Home Electronics Ltd Manufacture of semiconductor device
JPH06302629A (en) * 1993-04-19 1994-10-28 Toshiba Chem Corp Mounting method of semiconductor device
US5635010A (en) * 1995-04-14 1997-06-03 Pepe; Angel A. Dry adhesive joining of layers of electronic devices
US6017776A (en) * 1997-04-29 2000-01-25 Micron Technology, Inc. Method of attaching a leadframe to singulated semiconductor dice
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