CN1249534A - Method and system for testing IC in wafer stage - Google Patents

Abstract

Disclosed is a method and system for testing IC in wafer stage by using passive electric network. Based on the invention, a plurality of ICs are formed on the semiconductor wafer during making process. The conduct trace, conduct belt and test welding point are deposited on the empty area in the wafer during making IC on the wafer. The empty area includes an area around the wafer and a cut area for dividing the adjacent ICs. Conduct traces are formed to the conduct network in the cut area range between adjacent ICs. Using the conduct belt is to interconnect the conduct traces on the key position and connect the traces with input/output joint on the ICs.

Description

Method and system for testing integrated circuits at the wafer stage

The present invention relates to a method and system for providing passive electrical test structures for testing integrated circuits at the wafer level. More particularly, the present invention relates to a method and system for interconnecting integrated circuits which enable on-wafer testing of device functionality in an efficient and cost-effective manner. More particularly, the present invention relates to a method and system in which multiple integrated circuits are connected using the unoccupied area of the wafer separating adjacent rows and columns of integrated circuits as an intermediate staging area With the interconnection, this non-occupied area of the wafer is hereinafter referred to as the "kerf" area. Still more particularly, the present invention relates to a method and system for testing integrated circuits at the wafer level, wherein an orthogonal grid of conductive traces is formed in the notch area of the wafer, thereby providing a method and system for testing integrated circuits without reducing the size of the finished device. Reliable and efficient test structures for large wafer surface areas.

Mechanical probing of each integrated circuit (hereinafter "device") on a semiconductor wafer (hereinafter "wafer") for electrical testing is expensive and time consuming. Extremely precise X, Y, and spatial positioning is required, and the extremely small geometry of device input/output peripheral or zone array probe pads makes reliable electrical contact very difficult, requiring very fine precision probes . This difficult and time-consuming probing process constitutes a major part of the device manufacturing test cost. Poor contact of test probes will cause non-defective devices to be rejected during testing, thereby reducing wafer yield. Furthermore, as the number of input/output connection terminals of the device increases, that is, it is generally said that the input/output "count" of the device increases, due to the increase in the operating frequency of the device and the increase in power consumption, the physical and mechanical characteristics of the mechanical probe measurement Limitations limit the possible number of device input/output counts, test frequency, and maximum device power.

To address these problems, increasing emphasis has been placed on the design of integrated circuits to provide device testing methods that reduce the number of input/output pads that must be mechanically contacted while maintaining test integration. performance. R.W. Basset and others proposed such a test structure, called boundary-scan test design (boundary-scan testdesign), the paper titled "Effective LSSD ASIC test boundary-scan design principle", the full text was originally published in IBM J. Res.Develop.Vol.34, No.2/3, March/May 1990, which is hereby incorporated by reference in its entirety. Boundary-scan testing utilizes a design in which multiple shift registers (SRLs) are connected in cascade. In test mode, data can be sequentially scanned into and out of SRLs around the input/output of the device under test. The test process is simplified to input a known data sequence from the cascaded SRLs into the functional circuit, store the result, and then move the stored value out of the SRLs.

A problem with boundary-scan testing is that while it can confirm the functionality of the internal device circuitry, it is not possible to fully test the entire external I/O pad structure. The invention of Walther, Dasgupta and Srikishnan addresses this problem. Its patent number is U.S. Pat., No. 5,787,098, titled "Testing Complete Chip I/O by Low Contact Test Method Using Enhanced Boundary Scan Method", published on July 28, 1998. This invention describes a method of evaluating the integrity of solder ball input/output joints and is hereby incorporated by reference in its entirety.

From the foregoing it can be appreciated that there is a need for a method and system in which electrical interconnections in integrated circuits on a wafer are utilized to reduce or eliminate the need for mechanical probe measurements for wafer level integrated circuit testing. Such a method and system would be advantageous by simultaneously making electrical contact to the input/output contacts of multiple integrated circuits in such a way that multiple integrated circuits can be controlled at the wafer level with greater efficiency and effectiveness. carry out testing.

The object of the present invention is to provide a passive electrical test structure for the testing of integrated circuits at the wafer level.

It is another object of the present invention to provide a method and system for interconnecting integrated circuits, which enables functional testing of devices across an entire wafer in an efficient and cost-effective manner.

It is yet another object of the present invention to provide methods and systems for utilizing the kerf area of a wafer as an intermediate staging area from which to electrically contact and interconnect input/output contacts of a plurality of integrated circuits.

Yet another object of the present invention is to provide a method and system for testing integrated circuits at the wafer level, wherein an orthogonal grid of conductive traces is formed in the wafer kerf area, thereby providing a reliable and efficient test structure without Reduces wafer surface area for finished devices.

The above and other objects of the present invention are achieved as described above. The invention discloses a method and a system for testing an integrated circuit at the wafer stage by using a passive electrical network. According to the present invention, a plurality of integrated circuits are formed on a semiconductor wafer during a manufacturing process. During, and part of, the fabrication of integrated circuits on a wafer, conductive traces, conductive straps, and test pads are deposited on unoccupied areas of the wafer. This unoccupied area includes the area around the wafer perimeter and the kerf area that separates adjacent integrated circuits. The conductive traces form a conductive network within the kerf area between adjacent integrated circuits. Conductive straps are utilized to interconnect conductive traces at critical locations and to connect the traces to input/output contacts on the integrated circuit. Test pads are formed on unoccupied peripheral areas of the wafer and are electrically connected to the conductive trace network. In this manner, wafer electrical test structures are formed whereby integrated circuits can be tested before they are diced from the wafer.

The novel features characteristic of the invention are set forth in the appended claims. However, a better understanding of the invention itself and its preferred mode of use, further objects and advantages, may be better understood by reference to the following detailed description of the embodiments and the following accompanying drawings:

Figure 1 depicts the conceptual layout of the wafer and how large size test pads are positioned to feed to or be fed by overall integrated circuits or subsystems (columns or rows) in accordance with a preferred embodiment of the present invention;

Figure 2 illustrates a 2x2 array of integrated circuits in an mxn array of integrated circuits within a wafer in accordance with a preferred embodiment of the present invention;

Figure 3A depicts a layout diagram of a typical wafer stage in accordance with a preferred embodiment of the present invention;

Figure 3B illustrates some details of the cutout area next to the integrated circuit;

Figure 4 depicts an enlarged area of a wafer according to a preferred embodiment of the present invention of the wafer stage test configuration;

Figure 5 illustrates an enlarged portion of the wafer kerf area where conductive traces have been formed in accordance with a preferred embodiment of the present invention;

Figure 6 is a diagrammatic representation of a typical integrated circuit input/output contact location; and

FIG. 7 illustrates an interconnection network of integrated circuits near the periphery of a wafer in accordance with a preferred embodiment of the present invention.

Detailed Description of Preferred Embodiments

In a preferred embodiment, the present invention is applied in conjunction with boundary scan "pin reduction" testing techniques and enhancements described in the above-mentioned U.S. Pat. In order to reduce pin testing at the wafer level and create a structure that requires neither complex test fixtures nor step-and-repeat procedures in which probes are moved from device to device during wafer level testing. This improvement lowers the cost of wafer-level testing by reducing test time and test fixture complexity. The fixed and larger geometry of the joints also eliminates the uncertainty of good contact between the probes and the pads associated with known wafer steppers and probers, thus eliminating the possibility of contact due to electrical contact. False yield loss due to poor quality.

Wafer-level integrated circuit test structures and methods of forming and utilizing test structures for wafer-level integrated circuits are now described. This or a similar structure can be used for comprehensive testing of integrated circuits at the wafer level. Figures 1 and 2 respectively depict the conceptual layout of a wafer and how common test pads are positioned to feed to or be fed by an entire integrated circuit or subsystem (column or row). Figure 3A illustrates a typical wafer stage layout. Note that the separation between the IC locations, as shown by the lines in Figure 3A, actually constitutes the kerf area, typically between 0.3 and 0.9 mm in width, most of which disappears when the IC is diced from the wafer. Note also that the shaded, incomplete, unusable integrated circuit locations 124 around the perimeter of the wafer leave room for large geometry test pads. Figures 4 to 7 illustrate one of the methods for implementing the present invention in which a network of conductive traces is formed in the kerf and perimeter regions of the wafer with all connections required to implement the test structures of the present disclosure.

A method and system for comprehensively testing integrated circuits using a test structure is first described, followed by a description of its composition and how it is formed. FIG. 1 is a schematic top view illustrating the configuration of the usable surface area of a semiconductor wafer 10 (hereinafter referred to as wafer 10). Most of the surface area of wafer 10 is occupied by finished device region 12 filled with multiple integrated circuits including integrated circuits 24 and 26 . Narrow unoccupied channels such as cutout area 14 are located between integrated circuits, ie, the cutout area is located between adjacent integrated circuits 24 and 26 . The remaining surface area of wafer 10 is located on the peripheral area of wafer 10 , ie outside finished device area 12 . As shown in FIG. 1 , the peripheral area of wafer 10 can be used as a convenient location for power pad 16 , ground pad 20 , and test I/O pads 18 and 22 .

Referring to Figure 2, a test control structure 30 is depicted for a 2x2 array of integrated circuits 32, 34, 36 and 38 in an mxn array of integrated circuits on a wafer. FIG. 2 also depicts examples of common control types, such as test mode select lines 40 and 42 (TMS1 and TMS2 ), that may be used to test a device. These controls are connected to test pads at the wafer stage (such as test pads 300 in FIG. 7 ), which are fixed and do not need to be moved stepwise from device to device. Assuming the test pads 300 are spaced from each other around the wafer perimeter and are not densely packed around the fixture on a single device, this naturally reduces the complexity of the tester probe mechanism and electronics for providing a noiseless, reliable high frequency signal sex. Power lines 46 and 48 and ground lines 60 and 62 provide power to all devices through a common grid per row or column. In one embodiment of the present invention, the test mode select lines 40 and 42 (TMS1 and TMS2) and the test clock line 44 (TCK) comply with the IEEE 1149.1 standard for boundary scan testing and can be used to test the devices described below.

Level Sensitive Scan Design (LSSD) Clock and Control 50 is an input device that provides internal scan registers to provide scan, built-in self-test (BIST), or other tests that supplement or replace those required by the IEEE 1149.1 standard LSSD control. Two of the m row select lines 52 and 54 (X1 and X2) select a single row of devices if desired. Likewise, two row select lines 56 and 58 (Y1 and Y2) of the total n column select lines can select single column devices if desired. When testing integrated circuits according to the IEEE 1149.1 standard, the Y-control may not be required if the TMS line is available for column selection. Test data inputs 64 and 66 (TDI1 and TDI2 of m rows of such inputs) respectively feed scan inputs to all devices of a particular row of the wafer. Likewise, row-wise test data outputs 68 and 70 (TD01 and TD02 in m-rows of such outputs) are fed by all scan outputs for a given row.

The test control network is implemented according to Figure 2, and the testing of integrated circuits at the wafer level can be accomplished in several ways. To test all devices in a single column simultaneously, activate all X-controls and select only one of the Y-controls, or use TMS (Test Mode Line) to activate one device in each row to be tested. Test data inputs 64 and 66 then feed test data to the selected devices in each row. Likewise, test data outputs 68 and 70 scan test results from selected devices in each row. This control program can measure m devices (one in each row) at the same time, so that the test throughput is increased by m times. By ordering all TMS/Y-controls, all columns of devices can be tested in a total of n steps. For diagnostic purposes, a single row select line 52 or 54, and a single column select line 56 or 58 are simultaneously activated to select a single device which is then analyzed in a more careful manner than in conventional manufacturing testing.

After the wafer stage test is completed, the integrated circuit is cut from the wafer, and the test control lines located in the kerf area are destroyed. Segments of the test control lines that still remain connected to each integrated circuit are no longer connected to the test pads, creating a source of possible interference with device performance. To prevent these "loose ends" from interfering with the functionality of the device, the test network is ingeniously designed such that the control lines are connected to normal device input/output contacts, which are ultimately connected to, or controlled by, power or ground so as not to introduce noise or do not interfere with the normal logic function of the design. On the other hand, the circuits that feed or are fed by the pads under test can be designed so that these nets do not interfere with normal device operation.

A passive electrical test structure configuration and a set of methods of forming a passive electrical test structure configuration will now be described with reference to FIGS. 3A to 7 . The process steps described herein were selected to minimize deviation from conventional wafer processing procedures. As described in the next paragraph, the above-mentioned test structure utilizes a network approach in which the input/output contacts of multiple integrated circuits are interconnected using conductive traces formed in the kerf area of the wafer. This network approach allows simultaneous testing of multiple integrated circuits at the wafer stage while preserving maximum wafer surface area for finished devices.

FIG. 3A shows a wafer layout in which square blocks represent integrated circuits 120 (eg, DRAMs), each of which adjoins a cutout region 122 . For ease of reference, an x-y coordinate is attached to the wafer 100 in FIG. 3A. Integrated circuit 120 is oriented with its sides parallel to the x and y directions. Wafer notch 130 points in the y direction.

The current generation of an integrated circuit utilizes multiple layers of wiring to connect the internal device circuitry to terminals (terminal vias or pads) on the surface of the device. The internal device interconnection has wiring layers typically composed of Al-Cu separated by an insulator film. In some technologies, copper wires can be used instead of Al-Cu wires. The wiring patterns and pathways on the insulator are determined by projection lithography (eg 5X) using a step-and-repeat machine and reticles. Typically, each device is exposed individually, one at a time.

Device fabrication ends with the formation of device terminations, typically using a 1X masked photolithography process. The advantage of 1X lithography is the reduced cost of exposing the entire wafer in one step. Device terminations are designed for connection to printed circuit (PC) boards using wire bonding or IBM's Controlled Collapse Chip Ball Attachment method (C4). The die layout of most semiconductor integrated circuit products such as microprocessors or application specific circuits (ASICs) is similar to the layout shown in FIG. 3A except for the block size.

Figure 3B depicts some details of the reticle pattern 142 in the cutout area, which is exposed with the product at each step. As previously mentioned, kerf regions are generally defined as narrow scribe lines separating adjacent integrated circuit sites that are destroyed when the devices are finally diced from the wafer. The kerf area often contains several functional areas, including test structures, photolithography, and scribe marks. FIG. 3B shows functional cutout regions along both edges of each device site 144, including photolithographic marks such as alignment aids, critical dimension sites (CDs), and the like. Along the other edge of device location 144 is a square test area 150 which includes test structures for production and parametric measurements.

4 and 5 depict enlarged views of the portion of the wafer (not shown) where integrated circuits 162, 164, 166, and 168 are located. Horizontal conductive traces 160 and vertical conductive traces 180 are aligned in the x and y directions shown outside the alignment areas located in test area 150 or notch areas 145 and 155 , respectively. Conductive traces 160 and 180 are exaggerated relative to test and alignment areas 140 and 150 in FIGS. 4 and 5 . In practice, each set of conductive traces may occupy a narrower footprint than test and alignment areas 140 and 150 . Thus, although conductive traces 160 and 180 are depicted as being located outside test and alignment areas 140 and 150 , they are easily located adjacent to each integrated circuit 162 , 164 , 166 and 168 location.

The conductive traces 180 for transmitting input/output signals can be designed with a width of 5 μm and a pitch of 10 μm, so that 5 traces can be arranged in a space of approximately 50 μm. Thus, a space of less than 0.1 mm (100 μm) can be used to place 5 traces on both sides of each device, and can easily fit into a kerf area with a typical width of 0.3-0.9 mm. Conductive trace 160 is used to provide power and ground to the device under test and may be designed with a wider conductor than conductive trace 180 for signal transmission. For example, a wiring track consisting of four conductive traces occupying less than 0.1 mm in width, each trace 10 μm wide with a 5 μm pitch, separated between two edges. The conductive traces 160 can be widened to carry large currents, if desired. However, given their relatively short duty cycle, they can often be designed to carry much higher currents than similarly sized conductive traces used in finished devices.

For the purposes of the following explanations, it is assumed that the integrated circuit has a terminal metal layer which connects the device to a printed circuit board or other suitable substrate, and assuming that below the terminal metal, the wiring layer is referred to as the "final metal". For devices without terminal metal, the last two metallization layers (or wiring steps) will be used for test structure purposes.

Referring again to FIGS. 4 and 5, the conductive traces 160 and 180 are formed at the same time as defining the final metal layer, and use the same metal material (eg, Al-Cu or Cu) as the metal layer. Conductive traces 160 and 180 are contained within the exposed area of the stepper, as depicted in the enlarged view of cutout areas 145 and 155 . The pattern of conductive traces 160 and 180 is intentionally outside the active device area and completely within the kerf area, most of the traces will be destroyed when the device is diced from the master wafer. If any portion of conductive trace 160 or 180 remains, the exposed Al or Cu trace material is separated from the cutout area without affecting the reliability of the metallization of the integrated circuit. Dashed line 190 shows an imaginary boundary of midpoint values between adjacent device/cutout regions. Each trace terminates a few microns (5 to 50 [mu]m) before penetrating the adjacent device/kerf area.

The patterning of conductive traces 160 and 180 is formed in the same process used to pattern the wiring of the finished device, ie, a wet or dry etching process, or a damascene chemical/mechanical polishing process. If for certain types of products, the wiring pattern at this stage is formed through a 1X mask, and then the conductive traces 160 and 180 are formed using the 1X mask.

After the final metal patterning process that forms the conductive traces 160 and 180 and the integrated circuit wiring pattern, the entire conductor pattern is enclosed with an insulator (not shown in FIGS. 4 and 5 ), which is usually plasma-deposited Silicon, and in some cases organic insulators such as polyimide. The insulator provides an anti-scratch coating and provides insulation protection against possible moisture corrosion.

Next an insulating layer is deposited, and two sets of vias 200 and 210 are opened in the insulating layer. In the embodiment shown in FIG. 5, vias 200 are opened near the ends of segmented conductive traces 160 and 180 so that short conductive strips 220 can be used to form continuous but separate conductive paths. In this manner, all contiguous segments of conductive trace 160 and all contiguous segments of conductive trace 180 are conductively connected. Thus, conductive traces 160 and 180 form an orthogonal conductive network with continuous conductive paths in the illustrated x and y directions. FIG. 4 depicts another embodiment of the invention in which conductive traces 180 are deposited as conductive paths in the y direction. Thus, vias 200 and conductive strips 220 are only used to connect adjoining segments of conductive trace 160 that flow in the x-direction. As depicted in FIGS. 4 and 5, vias 210 provide contact points for conductively connecting conductive traces 160 and 180 to integrated circuits 162, 164, 166 and 168 with conductive straps 240 at appropriate input/output contact locations.

Both vias 200 and 210 are designed according to the same rules, and both are fully landed and wet and dry etched to provide specific slope wall characteristics. In one embodiment of the invention, the conductive straps 220 and 240 are formed of a metallic material that can remain exposed on the device without concern for corrosion, preferably the same material used to form the wire bonds or solder terminations, Such as Cr-Cu-Cr, Ti/Pd/Au or Cr-Ni-Au layers. These bands are defined by a 1X mask, usually the same mask used to make the termination pattern. If the termination process cannot be advantageously used to define the bands at the same time, then an additional 1X mask process can be used to define the bands. Although the conductive strap 240 is described as being above the final metal layer, those skilled in the art will understand that the connections between the conductive traces 160 and 180 and the input/output contacts 235 may also be deposited under the final metal layer. The wiring layer is completed, and the connection is made with the via between the layers.

FIG. 6 is a schematic diagram of a typical integrated circuit, illustrating how conductive strips 240 connect to input/output contacts 235 . In one embodiment of the invention, a set of dummy pads 245 are added on the device 250 . As can be seen from the lower region of device 250, each dummy pad 245 is connected to each input/output contact 235. In a variation of the invention, the conductive strip 240 meets the dummy pad 245, thus keeping the surface of the device I/O contact 235 clear for other terminal connections.

FIG. 7 shows details of a test structure near the periphery of the semiconductor wafer 100 according to an embodiment of the present invention. In this embodiment, if the wafer 100 has 64 devices in an 8x8 array, if each device requires 10 signal traces and 4 power/ground traces, then a total of 80 conductive traces are formed in the y direction 180 to provide test signals, a total of 32 conductive traces 160 are formed in the x direction for power and ground. Conductive traces 180 are connected to test pads 300 near the periphery of wafer 100 with conductive tape 280 . Those skilled in the art will appreciate that although not shown in the drawings, test devices may be connected to test pads 300 to provide input test signals for wafer-level integrated circuit testing. It will also be understood by those skilled in the art that receiver devices cut from the wafer may be connected to test pads 300 to receive output test results.

The conductive traces 180 can be split such that, if desired, one half of the trace terminates at one end of the wafer and the other end terminates at the opposite end. Although not depicted in FIG. 7 , test pads similar to test pad 300 are placed on the left and right halves of wafer 100 and connected to conductive traces 160 with conductive straps similar to conductive strap 280 . Using the same mask as strips 220 and 240, the patterns of conductive strip 280 and test pad 300 can be formed simultaneously.

At the periphery of the semiconductor wafer 100, the test pads 300 provide the ability to transmit dedicated signals and/or power to a group of devices in a column (y-direction), or provide the ability to transmit dedicated signals and/or power to a group of devices in a row (x-direction). and/or the capability of the power supply. In this way, specific devices located at the intersection of selected rows and columns can be tested, entire columns and entire rows can be tested simultaneously, and if desired, all devices can be tested simultaneously.

Although the present invention has been particularly described with reference to preferred embodiments, those skilled in the art will understand that various changes in form and details may be made therein without departing from the spirit and scope of the invention. Accordingly, such modifications are contemplated without departing from the spirit and scope of the invention as defined in the appended claims.

Claims (16)

1. A method of conductively connecting and interconnecting a plurality of integrated circuits at the wafer stage for the purpose of wafer stage testing on the integrated circuits, characterized in that said method comprises the steps of: Form multiple integrated circuits on a semiconductor wafer using a manufacturing process; depositing one or more conductive traces in the kerf area of the semiconductor wafer during the manufacturing process, thereby forming a conductive network; depositing a conductive strip connecting one or more input/output contacts of said integrated circuit with one or more of said conductive traces within said conductive network during said fabrication process; forming test pads in unused peripheral regions of the semiconductor wafer during the manufacturing process; and Conductive strips are deposited during the fabrication process to connect each conductive trace to one or more of the test pads so that the plurality of integrated circuits can be tested. 2. The method of claim 1, wherein said conductive network forms an orthogonal grid of conductive traces in the middle of said integrated circuits in a cutout area around the perimeter of each of said integrated circuits. 3. The method according to claim 1, further comprising the steps of: At least one test device is conductively connected to the test pads to provide input test signals and power to the input/output contacts of the integrated circuit. 4. The method according to claim 1, further comprising the steps of: At least one off-wafer receiver device is conductively connected to the test pads for receiving and recording output signals from the input/output contacts of the integrated circuit. 5. The method according to claim 1, further comprising the steps of: Subsystems of the integrated circuit, including rows and columns of the integrated circuit, are selectively connected using mode select lines. 6. The method of claim 1, wherein: All of said conductive traces forming a conductive network are deposited on the same metallization layer during said fabrication process. 7. The method of claim 1, wherein: All of the conductive strips are deposited on the same metallization layer during the fabrication process. 8. A system for conductively connecting and interconnecting a plurality of integrated circuits at wafer stage for the purpose of wafer stage testing on integrated circuits, characterized in that said system comprises: Devices that utilize fabrication processes to form multiple integrated circuits on a semiconductor wafer; means of depositing one or more conductive traces in the kerf area of said wafer during said manufacturing process, thereby forming a conductive network; means for depositing, during said fabrication process, a conductive strip connecting one or more input/output contacts of said integrated circuit with one or more of said conductive traces within said conductive network; means for forming test pads in unused peripheral regions of the wafer during the fabrication process; and means for depositing, during said fabrication process, a conductive strip connecting each conductive trace to one or more of said test pads so that said plurality of integrated circuits can be tested. 9. A system for testing a plurality of integrated circuits prior to dicing the integrated circuits from a semiconductor wafer, said system comprising: semiconductor wafers; a plurality of integrated circuits having input/output contacts formed on said semiconductor wafer; one or more conductive traces formed on unoccupied kerf areas of the semiconductor wafer; means for conductively connecting said conductive trace with said input/output contact of said integrated circuit; test pads located on unused perimeter kerf areas of the semiconductor wafer; and Means for conductively connecting the conductive traces with the test pads for testing a plurality of integrated circuits. 10. The system of claim 8, wherein the conductive traces include mode select lines selectively connecting subsystems of the integrated circuit, wherein the subsystems include rows and columns of integrated circuits. 11. The system of claim 8, further comprising: one or more test devices for providing input test signals and power to said input/output contacts of said integrated circuit; and means for conductively connecting said test device to said test pad. 12. The system of claim 10, further comprising: an off-wafer receiving device that receives output signals from said input/output contacts of said integrated circuit; and means for conductively connecting the off-wafer receiving device with the test pads. 13. The system of claim 10, wherein the testing device utilizes a boundary-scan testing technique. 14. The system of claim 8, wherein said conductive traces form an orthogonal grid between said integrated circuits, said conductive traces being all formed on a metallization layer. 15. A method of testing an integrated circuit having input/output signal, power and ground pads before the integrated circuit is diced from a semiconductor wafer, said method comprising the steps of: forming a plurality of integrated circuits on a semiconductor wafer having input/output signal, power and ground pads; channels in between, thereby forming a conductive network comprising columns of vertical traces continuous across the wafer and rows of horizontal traces that are broken at points so as not to intersect said vertical traces; combining the deposition of said vertical and horizontal traces into a single integrated circuit fabrication process, such as a metallization layer process, such that no additional integrated circuit fabrication process is required to deposit said vertical and horizontal traces; conductively connecting the disconnected paths in the horizontal traces with a conductive tape, thereby forming a continuous conductive path in the horizontal direction, while remaining electrically isolated from the vertical traces; conductively connecting said input/output signal contacts of one or more integrated circuits with said vertical traces; conductively connecting said power, ground pads and said horizontal traces of one or more integrated circuits; and The horizontal and vertical traces are conductively connected to test pads located on the peripheral region of the semiconductor wafer. 16. A system for testing an integrated circuit having input/output signal, power and ground pads prior to cutting said integrated circuit from a semiconductor wafer, said system comprising: Multiple integrated circuits with input/output signal, power and ground pads formed on a semiconductor wafer; A plurality of conductive traces formed on an unoccupied area of the semiconductor wafer, the conductive traces including vias between the integrated circuits, thereby forming an orthogonal grid comprising continuous spans across the columns of vertical traces of the wafer and rows of horizontal traces that are broken at points so as not to intersect said vertical traces; a conductive strip conductively connecting disconnected paths in said horizontal traces, thereby forming a continuous conductive path in the horizontal direction, while remaining electrically isolated from said vertical traces; means for conductively connecting said input/output signal contacts of said one or more integrated circuits with said vertical traces; means for conductively connecting said power, ground pads and said horizontal traces of said one or more integrated circuits; and means for conductively connecting said horizontal and vertical traces to test pads located on a peripheral region of said semiconductor wafer.

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