CN1246962C - Method for outputting clock pulse on data path and relative circuit - Google Patents

Abstract

The present invention provides a clock generation method, relevant application thereof and a circuit. The present invention uses at least one trigger and one logic module to provide an output clock pulse according to a reference clock, wherein each trigger is provided with a clock terminal and an output port for outputting signals, and the reference clock can be received by the clock terminal of each trigger so as to change the electrical level of signals output by the output ports of the triggers according to the triggering of the signal rising edge or falling edge in the reference clock. The logic module is used for carrying out logical operation on the signals output by the output port of each trigger so as to generate an output clock pulse in synchronization with the reference clock, and the output clock pulse can be output by a data path formed by the logic module, and can also carry out logical operation together with other signals.

Description

The method and the interlock circuit of output clock pulse on data path

Technical field

The invention provides a kind of method and related application and circuit of clock generating, refer in particular to a kind of method, related application and circuit that produces a synchronous output clock pulse with pulse reference clock triggering trigger, with data path by each trigger.

Background technology

Development along with information-intensive society, information miscellaneous, data, video-audio data can both be handled quickly and efficiently, propagate, store with the form of digital electronic signal, and be used to handle the various digital signal circuits of digital electronic signal, also just become one of most basic part of present information construction.

As is known to the person skilled in the art, general digital signal circuit all triggers sequence numeral Signal Processing, transmission with clock pulse, and coordinates the sequential of each element, functional unit work in the digital signal circuit.Along with the function of digital signal circuit is increasingly sophisticated, various, when the design digital signal circuit, the factor that needs to consider also gets more and more.Please refer to Figure 1A and 1B.Figure 1A, 1B are respectively the functional unit schematic diagram of a Typical Digital signal circuit 10 under different circuit design are considered.Shown in Figure 1A, realize the function of general digital circuit, be provided with a logic array 12, a plurality of trigger 14A, 14B and a clock control circuit 16 in the signal circuit 10.Clock control circuit 16 is used for producing a reference clock 18B according to a source clock 18A; Source clock 18A then can be produced by signal circuit 10 oscillators own, or is received by the support circuit beyond the signal circuit 10.Trigger 14A, 14B all have the clock end 15 of an input port 13A, an output port 13B and a correspondence; Input port 13A is used for receiving inputted signal (as received two different position input data respectively by two inputs), clock end 15 is used to receive the triggering of a clock pulse, and the function of each trigger is exactly under the triggering of its clock end 15 receive clock pulses, changes the signal (as changing two position dateouts of two inputs respectively) of its output port 13B output according to the signal of its input port 13A input.Wherein trigger 14A triggers the data transaction (transition) of its output port 13B output signal according to the rising edge of its clock end 15 receive clocks, and trigger 14B then is the data transaction that triggers its output port 13B output signal according to the trailing edge of its clock end 15 receive clocks.Then be provided with a plurality of different types of logic gates in the logic array 12, as in Figure 1A, illustrate with door 19A and or the door 19B.Suitably each logic gates in each trigger 14A, 14B I/O port and the logic array 12 is coupled together, just can make up, realize different digital circuitry functions, as various adders, counter and state machine (statemachine) or the like.In addition, also be provided with a plurality of output solder joints 22 on the signal circuit 10; For instance, signal circuit 10 can be to encapsulate chip completely, is the outer pin of encapsulation and respectively export solder joint 22.So, logic array 12 each logic gates or the signal of each trigger output port output can be output in outside the signal circuit 10 by a plurality of output solder joints (output pad) of signal circuit 10.And the output of each logic gates in each trigger output port and the logic array 12 promptly can be considered the data path (data path) of signal circuit 10 dateouts; Each exports the transport interface that solder joint also just becomes signal circuit 10 outside data paths.

With respect to data path, be connected to the clock transfer approach of each trigger clock end by clock control circuit 16, then can be described as the clock pulse path.As previously mentioned, in order to coordinate the sequential of each trigger 14A, 14B work, each trigger 14A, 14B should unify to be triggered by reference clock 18B.In other words, with regard to the consideration of logic function, the clock end 15 of each trigger 14A, 14B all should be directly connected to clock control circuit 16, just shown in Figure 1A purely.Under unified triggering of reference clock 18B, data transaction also will take place in the signal of each trigger output port simultaneously.Since in the logic function aspect, the reference clock on signal on the data path and the clock pulse path is synchronous, and both also just can carry out logical operation, so that the signal on the data path can further be changed according to reference clock 18B.Just as the illustrated embodiment among Figure 1A, a signal 20 can with reference clock 18B with one or the door 19B carry out exclusive disjunction; And or the signal of door 19B output on data path will be relevant with reference clock 18B.

But, behind the non-ideal factor of considering the digital circuit real work, signal circuit 10 should be as shown in Figure 1B, before clock 18B is transferred to each trigger, suitably add buffer 24, make the clock signal that is transferred to each trigger 14A, 14B clock end 15 trigger each trigger with simultaneous rising edge or trailing edge veritably.When digital circuit during in real work, each trigger 14A, 14B also just equivalence become the capacity load of clock control circuit 16; With regard to the 26A to 26C of branch that is marked on the clock pulse path with Figure 1B, being connected with on the 26A of branch has four triggers on three triggers, the 26B of branch, two triggers are then only arranged on the 26C of branch.Be equivalent to the capacity load maximum on the 26B of branch, the capacity load minimum on the 26C of branch.If drive trigger in these two branches with the clock of identical driving force, actual transmissions will lag behind clock on the 26C of branch to the clock on the 26B of branch, and (this phenomenon is called the distortion of clock, skew), because bigger capacity load has also increased in this branch and has discharged and recharged the required time on the 26B of branch.Therefore, shown in Figure 1B, should contact on the 26B of the branch buffer 24 of more a plurality of (or driving force is bigger), increase the driving force of clock, go up the non-ideal factor that big capacity load is introduced to overcome the 26B of branch, make that the clock that trigger received in the different branches can trigger each trigger veritably simultaneously.

When considering the non-ideal factor of digital signal circuit real work,, also to consider the time response of each trigger under clock pulse triggers except regulating reference clock 18B on the clock pulse path the driving force to each trigger clock end.About this situation, please refer to Fig. 2.Fig. 2 is that a typical rising edge triggers trigger 14 under the triggering of reference clock 18B, and the sequential schematic diagram of signal is gone in relevant output; Trigger 14 receives a signal 28A by an input (being denoted as D among Fig. 2) of its input port, and exports a signal 28B by an output (being denoted as Q among Fig. 2) of its output port under the triggering of reference clock 18B.And promptly show the time dependent waveform of signal level of signal 28A, 28B and reference clock 18B among Fig. 2; The transverse axis of each waveform is the time, and the longitudinal axis of each waveform is represented the size of wave level.As shown in Figure 2, along with reference clock 18B triggers at the rising edge of time point tp0, tp1, tp2 and tp3, trigger 14 meeting sampling input signal 28A are at the wave level of these time points, and change the wave level of output signal 28B accordingly, make the wave level of output signal 28B when the signal level of time point tp0, tp1, tp2 and tp3 is equivalent to input signal 28A respectively at these time points.With regard to the example among Fig. 2, be respectively H, H, H, L (please refer to the sign among Fig. 2) corresponding to input signal 28A at the level of time point tp0, tp1, tp2 and tp 3, the signal level of output signal 28B will become level H, H, H, L respectively.But, when trigger 14 real work, be sampled to the part of waveform level equalization among the input signal 28A in order to ensure trigger 14 can trigger according to the rising edge of reference clock 18B, the time that input signal 28A data transaction takes place must be as far back as the time that reference clock 18B rising edge takes place.For instance, as shown in Figure 2, make trigger 14 can be sampled to the input signal 28A of level H at time point tp0, input signal 28A will carry out data transaction at time point tpA in advance, is elevated to level H by level L.In other words, the time that the data transaction of input signal 28A and clock 18B rising edge take place must need certain time difference, and this time difference is time (set-uptime).

On the other hand, after the rising edge of reference clock 18B took place, input signal 28A will keep a period of time with signal level at least, and trigger 14 can correctly be taken a sample; And must keeping the time of level behind rising edge, input signal 28A is hold time (hold time).For instance, in Fig. 2, trigger 14 is after time point tp2 sampling, and input signal 28A will wait until that at least conversion of signals could take place time point t pB, so that allow trigger 14 signal level of input signal 28A at time point tp2 of stably taking a sample.In summary, when modelled signal circuit 10, except will as Figure 1A, considering with regard to the logic function aspect whether signal circuit 10 can realize the logical operation function of presetting, also will add the real work of Figure 1B considers, the suitable clock driving force of each branch on the fine setting clock pulse path, and between the time that the time and the rising edge clock (or trailing edge) of trigger input signal generation data transaction takes place, introduce the suitable time difference (these time differences can be finely tuned by the time of delay that buffer is introduced).In digital circuitry functions increasingly sophisticated today, consider that as the design of Figure 1A, 1B many having used a computer carry out tool software and carry out Aided Design.Logical design among Figure 1A can use VHDL supervisor language to be described and simulate; Clock among Figure 1B considers to use the tool software of clock trees synthetic (clock tree synthesize) to carry out computer-aided design.

As previously mentioned, when using signal circuit 10, have and reference clock 18B and general data-signal 20 need be carried out logical operation with the logic gates in the logic array 12 so that the data of logic array 12 on data path can and reference clock 18B directly related; Just as what illustrate among Figure 1A, the 1B, directly carry out logical operation at logic gates 19B with a signal 20 by reference clock 18B.Yet just as in the previous paragraph, under the situation of considering the digital circuit real work, the time of each data-signal generation conversion of signals should have reasonable time poor with the time that rising edge (trailing edge) among the reference clock 18B takes place on the data path.This moment is if directly carry out logical operation with reference clock 18B on the clock pulse path and the data-signal on the data path, in time difference between both data transaction, the result of logical operation will not be inconsistent expection, causes interference and confusion to logic operation result.In addition, when the Aided Design of carrying out with the synthetic tool software of clock trees signal circuit 10, tool software can be ignored reference clock 18B in the required driving force adjustment of this branch of logic gates 19B because reference clock 18B is directly inputted into logic gates 19B.Because the synthetic tool software of clock trees can be identified as clock pulse with the signal that is connected to each trigger clock end, automatically adjust its driving force and delay, but tool software can't be identified as clock pulse with the signal that is directly inputted into logic gates 19B automatically, so can't automatically carry out the adjustment of driving force and delay to the reference clock 18B that is directly inputted into logic gates 19B; And this can cause the clock of this branch of logic gates 19B and the clock of last each the trigger clock end input of the 26A to 26C of branch that rising edge and trailing edge can't take place veritably simultaneously.

In addition, as is known to the person skilled in the art, for whether the logical design of wanting validation signal circuit 10 conforms with the set goal, the designer of signal circuit 10 can carry out computer simulation to the logic function of signal circuit 10, with the logic function of the logical design validation signal circuit 10 among Figure 1A.But, when carrying out the computer simulation of logic function, the clock of each trigger clock end all by virtual be synchronous, no matter how many capacity loads in the branch of trigger place has, the computer simulation meeting supposes that rising edge and trailing edge take place the clock of each trigger clock end all at one time; This is because the main purpose of computer simulation this moment is the simulation of logic function.Yet, if directly reference clock 18B and signal 20 are carried out logical operation with logic gates 19B, computer simulation can not be identified as the clock of each trigger clock end with the reference clock 18B that inputs to logic gates 19B, and the reference clock 18B that inputs to logic gates 19B can be identified as the output signal of clock pulse control circuit 16.So, computer simulator can think that the clock of the reference clock 18B that inputs to logic gates 19B and each trigger clock end rising edge and trailing edge can not take place simultaneously, cause computer simulation correctly to carry out, increase the difficulty of signal circuit 10 logic functions checking.

In short, in signal circuit 10, often have and reference clock and other signals directly need be carried out logical operation, make the sequential of result after the logical operation and reference clock directly related; Even in some special circuit (as field programmable gate array, Field Programmable Gate Array), clock can't can only be exported clock by the data path in logic array, the trigger directly by the output of output solder joint.But, just as discussed earlier, in routine techniques,, can cause all difficulties in circuit design, the work, also make circuit designers be difficult to grasp the result of clock after logical operation if directly the clock on the clock pulse path is carried out logical operation.

On the other hand, in the digital circuit in modern times, also often will be between the circuit of different frequency switching signal.Please refer to Fig. 3 A.Fig. 3 A is in the signal circuit 30, the schematic diagram of each coherent signal when transmitting a signal 36 between neither with circuit module 32A, the 32B of clock.In signal circuit 30, circuit module 32A works in clock 34A, and circuit module 32B then works in the clock 34B of frequency multiplication.In routine techniques, when circuit module 32A will be transferred to circuit module 32B with a signal 36, circuit module 32B can earlier handle signal 36 to form another signal 38, produces signal 40 at last, so as to allow circuit module 32A in can identification signal 36 with information.And also show the waveform sequential chart of these coherent signals among Fig. 3 A, and the transverse axis of each waveform is the time, the longitudinal axis is the size of signal level.In the example of Fig. 3 A, because the clock 34B frequency multiplication of circuit module 32B work is in the clock 34A of circuit module 32A work, so the cycle of clock 34A also is the twice in clock 34B cycle.Just as shown in Fig. 3 A, the one-period of clock 34A between time point tp4 to tp6 just is equivalent to clock 34B two cycles between time point tp4, tp5 and tp5, tp6 respectively.Along with the triggering of clock pulse in each circuit module, respectively organize data just corresponding to each cycle of this circuit module clock in each circuit module in the signal.With Fig. 3 A is example, and in circuit module 32A, signal 36 (corresponding to clock 34A one-period) between time point tp4, tp6 maintains level H, just can be considered the data of set of number " 1 "; In like manner, signal 36 maintains level L (corresponding to another cycle of clock 34A) between time point tp6, tp8, promptly can be considered the data of set of number " 0 ".

When circuit module 32A will be transferred to the circuit module 32B of frequency doubling clock work with signal 36, because the clock difference of two circuit module work, signal 36 must be carried out suitable processing and conversion, could allow circuit module 32B correctly separate data in the read signal 36.If without processing, the circuit module 32B of frequency doubling clock work can with in the signal 36 corresponding to the data of the set of number " 1 " of clock 34A, be read as data, and the data in the erroneous judgement signal 36 corresponding to two groups of numerals " 1 " of clock 34B.In order to want respectively to organize data in the switching signal 36, the practice of routine techniques can be described below.In routine techniques, circuit module 32B is after received signal 36, and the trigger that can use a rising edge to trigger under the triggering of clock 34B, produces signal 38 according to signal 36, and signal 38 was postponed in the cycle of 36 1 clock 34B of signal.Signal 36 can carry out and computing with signal 38 anti-phase results then, produces signal 40.So, just only between corresponding to clock 34B time point tp4, the tp5 of one-period, can maintain level H in the signal 40, and circuit module 32B just can be read as this data of set of number " 1 ".In other words, in the signal 36 that cooperates clock 34A, the data of set of number " 1 " are arranged, and signal 36 after being converted to signal 40, also can be had only the data of set of number " 1 " via above-mentioned processing corresponding to the signal 40 of clock 34B.So, the signal 36 of circuit module 32A just can correctly be understood by the circuit module 32B of frequency multiplication work after being converted into signal 40.

But, above-mentioned routine techniques also has shortcoming, and that is exactly the array data that above-mentioned routine techniques can't be used for handling continuously (burst) transmission.About this situation, please refer to Fig. 3 B.Fig. 3 B is for two circuit module 32A of digital circuit 30 among Fig. 3 A, when 32B transmits a signal 42, the schematic diagram of each coherent signal waveform sequential; The transverse axis of each waveform is similarly the time, and the longitudinal axis is the size of each waveform.Shown in Fig. 3 B, the signal 42 among the circuit module 32A (corresponding to two cycles of clock 34A) between time point tp9 to tp11 maintains level H continuously, is equivalent to two groups of continuous numerals " 1 " data.If but according to the practice of aforementioned routine techniques, the trigger that utilizes clock 34B to trigger produces signal 46, anti-phase and signal 42 with signal 46 carries out and computing again, still only has one group in its signal that draws 48 corresponding to the clock 34B numeral of one-period " 1 " data.In other words, with the practice of routine techniques, the data that are transferred to circuit module 32B by circuit module 32A can not be continuously (burst) data, and this also makes the efficient of transfer of data between two circuit modules reduce.

Summary of the invention

Therefore, main purpose of the present invention, be on data path, to provide a signal that changes with clock synchronization, and export the related application that clock pulse is carried out data processing etc., directly carry out the variety of problems that logical operation is derived with clock to overcome in the routine techniques with this as the output clock pulse.

In the present invention, triggered by a pulse reference clock and the output signal that changes is carried out logical operation, on the data path that trigger and logic gates are formed, produce one and export clock pulse trigger.This output clock pulse and reference clock are synchronous, can be applied in again on the data path, directly and other data-signals on the data path carry out logical operation.Because being the output with trigger, the output clock pulse among the present invention produces, so when the logic function checking of computer simulation, can obtain correct analog result, and carrying out clock trees when synthetic, implementing procedure also can be adjusted the driving force of each clock as usually, makes the digital circuit that is synthesized can be normally according to default sequential working.

In addition, the output clock pulse among the present invention can correctly be carried out logical operation with other signals on data path, so the present invention can be applicable on the Synchronous Processing of data, clock.As will be when neither transmitting with the processing signals between the circuit module of clock work, just can use output clock pulse that the present invention generates directly and the signal of transmission carries out logical operation, make between the circuit module of different clocks and can correctly transmit, understand signal with continuous (burst) data.

According to an aspect of the present invention, provide a kind of according to a reference clock with on data path, provide one output clock pulse method, it includes:

With the trigger impulse of pulse reference clock while as first, second trigger;

As first signal, homophase output is as the input signal of this trigger with the anti-phase output of first trigger;

With the anti-phase output of second trigger as secondary signal, with the input signal of first signal as this trigger,

Wherein, first trigger adopts the mode of rising edge to trigger, and second trigger adopts the mode of trailing edge to trigger;

First signal and secondary signal are carried out xor operation obtain clock signal.

According to a further aspect in the invention, provide a kind of clock circuit, comprised first, second trigger and an XOR circuit, wherein:

The input end of clock of first, second trigger receives pulse reference clock simultaneously as triggering clock;

The signal of first trigger reversed-phase output output is as first signal, and the signal of in-phase output end output is as the input signal of this zone of departure;

The signal of second trigger in-phase output end output is as secondary signal, and this trigger receives first signal as input signal;

First trigger is the rising edge trigger, and second trigger is the trailing edge trigger;

XOR circuit is carried out XOR to first, second signal, and it is exported as clock signal.

Description of drawings

Figure 1A, 1B are the schematic diagram of normal signal circuit functional unit when different circuit design stages.

Fig. 2 is the schematic diagram that the signal waveform sequential is gone in typical trigger output under clock pulse triggers among Figure 1A, the 1B.

Fig. 3 A, 3B are the schematic diagram of the waveform sequential of coherent signal when processing signals is transmitted between neither with the clock operating circuit in the routine techniques.

Fig. 4 is for producing the functional unit schematic diagram of output clock pulse on data path in the signal circuit of the present invention.

Fig. 5 is the schematic diagram of coherent signal waveform sequential when signal circuit is worked among Fig. 4.

Fig. 6 is the schematic diagram of another embodiment functional unit of clock module among Fig. 4.

Fig. 7 A carries out the functional unit schematic diagram of conversion of signals at two pilot channel intermodules of a signal circuit for the present invention.

Fig. 7 B is the schematic diagram of coherent signal waveform sequential when signal circuit is worked among Fig. 7 A.

Fig. 8 A carries out the functional unit schematic diagram of conversion of signals at two pilot channel intermodules of another signal circuit for the present invention.

Fig. 8 B is the schematic diagram of coherent signal waveform sequential when signal circuit is worked among Fig. 8 A.

Fig. 9 A carries out the functional unit schematic diagram of conversion of signals at two pilot channel intermodules of another signal circuit for the present invention.

Fig. 9 B is the schematic diagram of coherent signal waveform sequential when signal circuit is worked among Fig. 9 A.

The reference numeral explanation

10,30,50,80,100,120 signal circuits

12,52 logic array

13A, 53A input port

13B, 53B output port

14,14A-14B, 54,64A-64D, 140 triggers

15,55,142 clock end

16,56 clock control circuits

18A, 58A source clock 1

8B, 58B reference clock

19A, 96 and the door

19B, 59A or door

20,28A-28B, 36,38,40,42,46,48,66A-66C signal

22,62 output solder joints

24 buffers

26A-26C branch

The 59B XOR gate

32A-32B, 82A-82B, 102A-102B, 122A-122B circuit module

34A-34B, 84A-84B, 104A-104B, 124A-124B clock

58C, 84C, 104C, 124C export clock pulse

70,86,106,126 clock modules

129 reference signals

88A-88B, 108A-108D, 128A-128B control signal

90A-90B, 110A-110D, 130A-130B data-signal

92A-92B, 94A-94B, 112A-112D, 114A-114D, 116A-116D, 132A-132B, 134A-134B data

T1-T3 cycle S, R, D input

Q, Q ' output H, L level

Tp0-tp12, t0-t7, ta0-ta4, tb0-tb12, tc0-tc6 time point

Embodiment

Please refer to Fig. 4.Fig. 4 is the functional unit schematic diagram of digital signal circuit 50 of the present invention.Be similar to typical digital signal circuit, signal circuit 50 among the present invention also is provided with a clock control circuit 56, a plurality of trigger 54,64A and 64B, and a plurality of logic gates in logic array 52 (as shown in Figure 4 or door 59A, XOR gate 59B or the like).Clock control circuit 56 is used for producing a reference clock 58B according to a source clock 58A; And the signal waveform of may command reference clock 58B.For instance, when signal circuit 50 will be operated in battery saving mode, clock control circuit 56 can reduce the frequency of reference clock 58B, or even reference clock 58B is fixed on a fixing level, change no longer in time.And the basic structure of each trigger 54 is identical, has a clock end 55, with under the triggering of the rising edge of clock end 55 receive clocks or trailing edge, according to the signal of its output of signal change 53B output of its input 53A input.The clock end of each trigger is then unified to be triggered by reference clock 58B, to coordinate the sequential of each flip-flop operation.Similarly, each trigger output port is exported the data path that just constitutes signal circuit 50 into end together with logic array 52 each logic gates, and reference clock 58B then controls the sequential of each flip-flop operation by the clock pulse path that is connected to each trigger clock end.Each logic gates that suitably connects each trigger and logic array 52 just can realize the function of various digital signal circuits, and with a plurality of output solder joints 62 outputs of coherent signal by signal circuit 50.

In order to realize one of purpose of the present invention, the data-signal that generation one and reference clock 58B change synchronously on data path is also realized the function of a clock module 70 as an output clock pulse with two trigger 64A, 64B and an XOR gate 59B among the present invention.As shown in Figure 4, in this clock module 70 as a clock circuit, the clock end of trigger 64A, 64B all is subjected to the triggering of reference clock 58B by the clock pulse path; The input port of trigger 64A, 64B has an input (being denoted as S among Fig. 4) respectively, and the output port of each trigger then has two anti-phase each other outputs (being denoted as Q, Q ' among Fig. 4 respectively).Trigger 64A is the trigger that rising edge triggers, if its input S is sampled to the data of numeral " 1 ", the data of its output Q, Q ' output numeral respectively " 1 ", " 0 " when the rising edge of clock 58B takes place; If be sampled to the data of digital " 0 ", then its output Q, Q ' can export the data of digital " 0 ", " 1 " respectively.The trigger that trigger 64B then triggers for trailing edge, if its input S is sampled to the data of numeral " 1 " when the trailing edge of clock 58B takes place, the data of its output Q, Q ' output numeral respectively " 1 ", " 0 ", by that analogy.In clock module 70, the output signal 66C of trigger 64A output Q ' directly feedback is connected to its input S, and its output Q then produces a signal 66A.Signal 66A can be transferred to the input S of trigger 64B, produces a signal 66B at the output Q of trigger 64B under triggering with the trailing edge at reference clock 58B.As a logic module signal 66A, 66B are inputed to XOR gate 59B with after carrying out XOR with XOR gate 59B, just can be on the data path of signal circuit 50, produce a signal that changes synchronously with reference clock 58B, just export clock pulse 58C.

About clock module 70 work principle, please further with reference to figure 5 (and in the lump with reference to figure 4).When Fig. 5 is clock module 70 work among Fig. 4, the schematic diagram of each coherent signal waveform sequential.The transverse axis of each waveform is the time, and the longitudinal axis is the size of wave level.From top to bottom, promptly be respectively signal 66C, the reference clock 58B of trigger 64A output Q ', signal 66A, the 66B of trigger 64A, 64B output among Fig. 5, and the waveform of output clock pulse 58C.The cycle of reference clock 58B is T, and its waveform has a rising edge and a trailing edge in one-period.As shown in Figure 5, suppose before time point t0 that the signal level of output Q, the Q ' of trigger 64A is respectively level L, the H that represents digital " 0 ", " 1 "; At time point t0, the rising edge of reference clock 58B is sampled to numeral " 1 " data of signal 66C level H, makes trigger 64A also make the signal 66A of its output Q output be increased to level H; The signal 66C of output Q ' then is reduced to level L.Arrived the rising edge of reference clock 58B at time point t2, it is level L that trigger 64A is sampled to signal 66C again, makes trigger 64A transfer the signal 66A of its output Q to level L, transfers the signal 66C of output Q ' to level H, by that analogy.So, each rising edge of reference clock 58B (as the rising edge at time point t0, t2, t4 and t6) all can triggering signal 66A, 66C exchange once between level H, L.According to similar reason, be that the trigger 64B of input signal then can change level once at the trailing edge triggering signal 66B of time point t1, t3, t5 and t7 at clock 58B with signal 66A.After XOR gate 59B carried out XOR with signal 66A, 66B, the output clock pulse 58C of its gained just as shown in Figure 5.As seen from Figure 5, output clock pulse 58C can and reference clock 58B synchronously change, in other words, it is clock on data path that output clock pulse 58C just can equivalent be used as.

Cross as previously discussed, digital signal circuit often has and the data-signal on clock and the data path need be carried out logical operation, but if picture directly carries out logical operation with clock on the clock pulse path and the data-signal on the data path in routine techniques, all difficulties in the time of can causing digital signal circuit on circuit design, to reach real work.In the present invention, then available clock module 70 (just at the output port of trigger and output of logic array logic gates) on data path produces a data-signal that changes synchronously with reference clock 58B, just exports clock pulse 58C.In the time other data-signals on clock and the data path need being carried out logical operation, just can use output clock pulse 58C on the data path to be used as to be other data-signals on clock and the data path to carry out logical operation.Because output clock pulse 58C produces on data path, when the logic function checking of signal circuit 50 being carried out computer simulation, reference clock 58B can directly not carry out logical operation in logic gates and other signals, can the situation generation of the clock pulse in clock pulse path being sneaked into data path not arranged, the logic function checking can normally successfully be carried out as routine techniques.In like manner, carrying out clock trees when synthetic, because reference clock 58B can not be directly connected to logic gates as routine techniques, but normally being connected to the clock end of trigger 64A, 64B, the synthetic tool software of clock trees just can normally be that trigger 64A, 64B finely tune clock driving force and the time of delay in its branch.

Please refer to Fig. 6.Fig. 6 is the functional unit schematic diagram of clock module 70 another embodiment among Fig. 4.Clock module 70 among Fig. 6 constitutes with trigger 64C, 64D and an XOR gate 59B, and according to the triggering of reference clock 58B to trigger, and on data path, produce a data-signal that changes synchronously with reference clock 58B, as an output clock pulse 58C.Be similar to the embodiment among Fig. 4, trigger 64C, 64D also are respectively the trigger of rising edge and trailing edge triggering; Different relatively is that trigger 64C is the signal that receives its output port feedback with its input R.When trigger 64C worked, if when the rising edge of reference clock 58B takes place, trigger 64C can export the data of digital " 0 ", " 1 " respectively by its output Q, Q ' by the data that its input R is sampled to numeral " 1 "; Otherwise, if input R is sampled to the data of digital " 0 ", the signal of its output Q, Q ' output numeral respectively " 1 ", " 0 ".Clock module 70 work principle among Fig. 6 are identical with the clock module 70 among Fig. 4, and those skilled in the art should analogize and get; Not influencing under the disclosed situation of the technology of the present invention, repeat no more.

Utilize clock module 70 of the present invention after generation on the data path is equivalent to the data-signal (just exporting clock pulse 58C) of clock, it has multiple possible application.The most direct application is that output clock pulse 58C is directly exported by the output solder joint 62 of signal circuit 50.As previously mentioned, in some special circuit (as field programmable gate array), clock on the clock pulse path can't be directly by the output of output solder joint, just can produce the data-signal that is equivalent to clock with spirit of the present invention this moment in these special circuits, again solder joint is being exported in this data-signal output, being used as is the output of clock.For instance, in microprocessor system, if will realize the controller of a memory (as static RAM) with field programmable gate array, just realize clock module of the present invention in the programmable gate array at the scene, allow controller be able to the signal of output equivalent in clock, with as a clock circuit, the sequential of control storage data access.

In addition since the output clock pulse that generates of clock module of the present invention can be directly and other signals on the data path carry out logical operation, so export the foundation that clock pulse also can be used for being used as signal processing.For instance, when having two circuit modules that work in different clocks to want transmission signals in the signal circuit, the output clock pulse that just can use the present invention to produce is handled the signal that will transmit.About this situation, please refer to Fig. 7 A.Fig. 7 A is in the digital signal circuit 80, and two circuit module 82A, the 82B that are operated in different clocks 84A, 84B carry out the functional unit schematic diagram of signal processing with clock module of the present invention.In signal circuit 80, circuit module 82A works in clock 84A, and circuit module 82B then works in the clock 84B of frequency multiplication.Make circuit module 82B can correctly understand the data that send by circuit module 82A, can use spirit of the present invention in circuit module 82A, to realize a clock module 86 (as with the clock module among Fig. 4 or Fig. 6 70), with produce on data path according to clock 84A one with the data-signal of clock 84A equivalence, just export clock pulse 84C.To then can define the time of its valid data continuity by the data-signal 90A that circuit module 82A is transferred to circuit module 82B by the control signal 88A of a correspondence.Two realize logic modules with 96 at door, respectively data-signal 90A, control signal 88A and output clock pulse 84C are carried out and computing, can produce data-signal 90B, control signal 88B respectively.Cooperate control signal 88B, circuit module 82B gets final product the data among the correct unscrambling data signal 90B.

About the further situation of circuit working among Fig. 7 A, please continue with reference to figure 7B (and in the lump with reference to figure 7A).When Fig. 7 B is signal circuit 80 work among Fig. 7 A, the schematic diagram of each coherent signal waveform sequential; The transverse axis of Fig. 7 B is the time, and the longitudinal axis of each waveform is the level size of signal waveform.Shown in Fig. 7 B, circuits for triggering module 82A is according to the clock 84A of sequential working, and its cycle is T1; Circuit module 82B then works in the frequency doubling clock 84B of period T 2, so period T 2 is equivalent to period T 1 half.According to clock 84A, the clock module of realizing with spirit of the present invention 86 can produce the output clock pulse 84C of an equivalence on data path.Cooperate the triggering of clock 84A, suppose that the data-signal 90A among the circuit module 82A has each continuous two groups of data 92A, 94A corresponding to one-period T1 will be transferred to circuit module 82B between time point ta0 to ta4; Cooperate two groups of data among the data-signal 90A, circuit module 82A can be between time point ta0 to ta4, control signal 88A is maintained the level H (all the other times then are the level L of representative digital " 0 ") that represents numeral " 1 ", the time of designation data 92A, 94A continuity.Respectively with one with door 96 with data-signal 90A, control signal 88A and output clock pulse 84C carry out with computing after, just can form data-signal 90B, control signal 88B.Wherein, two of data-signal 90A groups of data 92A, 94A with computing after become data 92B, 94B among the data-signal 90B respectively.By finding out among Fig. 7 B, because the cycle of output clock pulse 84C can be the level L of digital " 0 " between time point ta1 to ta2, time point ta3 to ta4, output clock pulse 84C with data-signal 90A carry out with computing after, originally respectively continue data 92A, the 94A of one-period T1, just become data 92B, the 94B that only continues half period T1 among the data-signal 90B respectively, can be considered the subdata of data 92A, 94A, just in time corresponding to the one-period T2 of clock 84B.And between time point ta1 to ta2, ta3 to ta4, among the data-signal 90B originally corresponding to during data 92A, the 94A will with computing after become the subdata of digital " 0 ".In like manner, also can during data 92B, 94B continuity, maintain level H with control data 88B after the computing, with valid data among the designation data signal 90B (just data 92B, 94B) continued during.Because the time of data 92B, 94B among data-signal 90B continuity is just corresponding to the one-period T2 of clock 84B, the former circuit module 82B that works in clock 84B just can be following assisting of control data 88B, correctly will continue at data 92B, the 94B of time point ta0 to ta1, ta2 to ta 3 to be judged as one group of data respectively.In other words, in signal circuit 80, output clock pulse 84C can be used for directly and data-signal 90A, control signal 88A carry out logical operation because spirit of the present invention generates, just can be used between two circuit modules that work in different clocks, carrying out the processing and the conversion of signal format, allow the signal of transmission between the two correctly be understood.Note that in the example of Fig. 7 B,, all belong to (burst) data continuously no matter be the signal of between time point ta0 to ta4, keeping two period T 1 among two groups of data 92A, 94A among the data-signal 90A or the control signal 88A continuously; In other words, are continuous datas even circuit module 82A will be transferred to the data of circuit module 82B, still can suitably be changed with the data processing method of the present invention in Fig. 7 A, 7B.In comparison, the routine techniques of discussing among Fig. 3 A, the 3B just can't have been handled continuous data.

Please refer to Fig. 8 A, 8B.Fig. 8 A for the present invention in another signal circuit 100, between circuit module 102A, the 102B of two alien frequencies clocks, carry out the functional unit schematic diagram of signal processing; Fig. 8 B then is the schematic diagram of coherent signal waveform sequential among Fig. 8 A; The transverse axis of Fig. 8 B is the time, and the longitudinal axis of each waveform is the size of signal level.In Fig. 8 A, signal circuit 100 also has two the circuit module 102A, the 102B that work in clock 104A, 104B respectively, and the frequency of clock 104B then is four times of clock 104A.Under the difference of two circuit module quadruple work clocks, the data-signal 110A that makes circuit module 102A be transferred to circuit module 102B can correctly be understood by the latter, still can use spirit of the present invention, earlier according to clock 104A, on data path, produce the output clock pulse 104C of an equivalence with clock module 106, control signal 108A with a data-signal 110A and a correspondence carries out and computing with door 96 one with output clock pulse 104C respectively again, to produce data-signal 110B and control signal 108B respectively.After circuit module 102B receives data-signal 110B and control signal 108B, can be according to the triggering of clock 104B, produce data-signal 110C and control signal 108C with trigger 140 (its input is denoted as D, output is denoted as Q, and has clock end 142) respectively.Data-signal 110B and 110C, control signal 108B and 108C respectively one with the door 96 carry out with computing after, data-signal 110D that it generated and control signal 108D just include the correct information corresponding to data-signal 110A, can be understood by the circuit module 102B of quadruple smoothly.

Shown in Fig. 8 B, be used for the clock 104A of circuits for triggering module 102A according to sequential working, the cycle of its clock is T1; And the quadruple clock 104B of circuits for triggering module 102B work, its cycle then is T4; In other words, four period T 4 are arranged among the one-period T1.Utilize clock module 106 disclosed by the invention, circuit module 102A can produce an output clock pulse 104C who changes synchronously according to the triggering of clock 104A on data path.Suppose that in circuit module 102A having respectively among the data-signal 110A, continuous three groups of data 112A, 114A and the 116A of corresponding one-period T1 will be transferred to circuit module 102A; And circuit module 102A just can be between time point tb0 to tb12 in time period of continuous three period T 1, control signal 110A is maintained the level H of numeral " 1 ", with among the designation data signal 110A by time point tb0 to tb12 three groups of continuous data 112A, 114A and 116A.Respectively data-signal 110A, control signal 108A and output clock pulse 104C are carried out with computing after, just become data-signal 110B and 108B respectively.Shown in Fig. 8 B, originally in data-signal 110A, continue data 112A, 114A and the 116A of one-period T1 respectively, in data-signal 110B, just become data 112B, 114B and the 116B of continuity half period T1 respectively, can be considered the subdata of continuity half period T1.In like manner, also only can between time point tb0 to tb2, tb4 to tb6, tb8 to tb10, maintain the level H of numeral " 1 " among the control signal 108B.

In circuit module 102B, control signal 108B, data-signal 110B handle and formation control signal 108C, data-signal 110C through the triggering of a trigger 140 respectively.As shown in Fig. 8 A, three groups of data 112B, 114B among the data-signal 110B and 116B just postpone the time of one-period T4 respectively through after the processing of trigger 140, become data 112C, 114C and 116C among the data-signal 110C.In like manner, control signal 108B maintains the part of level H between time point tb0 to tb2, tb4 to tb6, tb8 to tb10, the time that also postpones one-period T4, become the part that between time point tb1 to tb3, tb5 to tb7 and tb9 to tb11, maintains level H among the control signal 108C.Data-signal 110B and 110C, control signal 108B and 108C are carried out respectively with computing after, just become data-signal 110D and control signal 108D.Can find out by Fig. 8 B, three groups of data 112B, 114B among the data-signal 110B and 116B with data-signal 110C in three groups of data 112C, 114C and 116C and computing after, just become among the data-signal 110D three groups of data 112D, 114D and 116D respectively; These three groups of data just all maintain one-period T4 during.In like manner, also only during one-period T4, maintaining level H between time point tb1 to tb2, tb5 to tb6 and the tb9 to tb10 respectively among the control signal 108D.So, work in the circuit module 102B of quadruple clock 104B, just can correctly the data 112D among the data-signal 110D, 114D and 116D be read as one group of data respectively according to control signal 108D.

Please refer to Fig. 9 A, 9B.Fig. 9 A for the present invention in another signal circuit 120, carry out between circuit module 122A, the 122B of two alien frequencies clock works that data format is handled, the functional unit schematic diagram of conversion; Fig. 9 B then is the schematic diagram of each coherent signal waveform sequential among Fig. 9 A, and the transverse axis of Fig. 9 B is the time, and the longitudinal axis of each waveform is represented the size of wave level.In Fig. 9 A, circuit module 122A works in clock 124A, and circuit module 122B then works in the clock 124B of a frequency tripling.When circuit module 122A will be transferred to circuit module 122B with a data-signal 130A, also can one clock module 126 be set spirit according to the present invention among the circuit module 122A, on data path, to produce the output clock pulse 124C of an equivalence according to clock 124A.As previously mentioned, the output clock pulse that generates via clock module 126 of the present invention can be used to carry out logical operation, is 1/3 reference signal 129 so just can use a logic module 127 to produce a work period (duty cycle) according to clock 124C in circuit module 122A in addition; Promptly show clock 124A (just exporting clock pulse 126C) the waveform sequential of reference signal 129 therewith among Fig. 9 B.With the control signal 128A of a data-signal 130A and a correspondence respectively one with door 96 therewith reference signal 129 carry out with computing after the data-signal 130B and the control signal 128B that are produced, can allow the circuit module 122B that works in frequency tripling correctly understand the data that originally in data-signal 130A, carry.It should be noted that logic module 127 can utilize combinational circuit to construct, any those skilled in the art are when being made up according to its actual demand.In addition, logic module 127 also can be incorporated in the clock module 126, and those skilled in the art are when being changed according to actual demand.

Shown in Fig. 9 B, clock 124A, 124B are respectively applied for circuits for triggering module 122A according to sequential working, and its cycle is respectively T1 and T3; Because the frequency of clock 124B is three times in clock 124A, so contained three period T 3 among the one-period T1.Via clock module 126, can produce output clock pulse 124C according to clock 124A.And logic module 127 just can produce the reference signal synchronous with it 129 according to output clock pulse 124C.Suppose in the data-signal 130A of circuit module 122A, there are two groups will be transferred among the circuit module 122B corresponding to data 132A, the 134A of one-period T1 respectively, circuit module 122A just can be between time point tc0 to tc6, control signal 128A is maintained the level H of numeral " 1 ", the time that valid data are kept among the designation data signal 130A.With control signal 128A, data-signal 130A respectively with reference data 129 carry out with computing after can controlled signal 128B, data-signal 130B.As shown in Fig. 9 B, continue two groups of data 132A, 134A of one-period T1 among the data-signal 130A respectively, having arrived just becomes two groups of subdata 132B, 134B that continue one-period T3 respectively among the data-signal 130B; In like manner, in 1 part that is maintained level H of two period T, also just become among the control signal 128B among the control signal 128A, between time point tc0 to tc1, tc3 to tc4, maintain the part of level H respectively.Since be equal to the one-period T3 of clock 124B during data 132B, the 134B continuity, circuit module 122B just can be according to the indication of control signal 128B, correctly the data among the unscrambling data signal 130B.

In routine techniques, only with the clock on the clock pulse path directly and the signal on the data path carry out logical operation, will cause the multiple difficulty in circuit design, simulation, the realization; In some special circuit, the clock road also can't directly be exported by the output solder joint through last clock, causes the difficulty of using.Owing to should not directly carry out logical operation with the data on the data path at the clock on the clock pulse path in the routine techniques, so also be difficult to the signal processing of utilizing clock to be correlated with in the routine techniques, as between the circuit of two alien frequencies work, carrying out the conversion of signal data; So the method for routine data conversion also can't be handled continuous data.In comparison, the present invention at first discloses the technology that produces clock on data path in the relevant discussion of Fig. 4 to Fig. 6, so that trigger trigger with clock pulse, the data-signal (just exporting clock pulse) of generation one and clock synchronization on data path.Because the present invention can produce the output clock pulse on data path, significantly reduced all difficulties in circuit design, simulation, the realization; Even can't directly export the special circuit of clock pulse, also can utilize spirit of the present invention, equivalent signal that changes with clock synchronization of generation/output on data path at output solder joint (pad).In addition, the present invention has also discussed the output clock pulse of how utilizing on the data path and carried out the processing and the conversion of data-signal between the circuit module of alien frequencies work in Fig. 7 A, 7B, Fig. 8 A, 8B and Fig. 9 A, 9B, so that the information in the data-signal can correctly be understood.And above-mentioned data-signal is handled, the method for conversion all can be used for handling (burst) data continuously, increases the efficient of signal transmission.

The above only is preferred embodiment of the present invention, and all equivalences of carrying out according to claim of the present invention change and revise, and all should belong to covering scope of the present invention.

Claims (10)

1. One kind according to a reference clock with on data path, provide one output clock pulse method, it includes:

   With the trigger impulse of pulse reference clock while as first, second trigger;

   As first signal, homophase output is as the input signal of this trigger with the anti-phase output of first trigger;

   With the anti-phase output of second trigger as secondary signal, with the input signal of first signal as this trigger,

   Wherein, first trigger adopts the mode of rising edge to trigger, and second trigger adopts the mode of trailing edge to trigger;

   First signal and secondary signal are carried out xor operation obtain clock signal.
2. 2. the method for claim 1, wherein when each rising edge according to this reference clock changes the level of this first signal, if the level of this first signal is one first level before this rising edge takes place, then after taking place, this rising edge make the level of this first signal change into one second level.
3. 3. method as claimed in claim 2 if the level of this first signal is this second level before this rising edge takes place, then makes the level of this first signal change into this first level after this rising edge takes place.
4. 4. the method for claim 1, wherein when each trailing edge according to this reference clock changes the level of this secondary signal, if the level of this secondary signal is one first level before this trailing edge takes place, then after taking place, this trailing edge make the level of this secondary signal change into one second level.
5. 5. method as claimed in claim 4 if the level of this secondary signal is this second level before this trailing edge takes place, then makes the level of this secondary signal change into this first level after this trailing edge takes place.
6. 6 one kinds of clock circuits comprise first, second trigger and an XOR circuit, wherein:

   The input end of clock of first, second trigger receives pulse reference clock simultaneously as triggering clock;

   The signal of first trigger reversed-phase output output is as first signal, and the signal of in-phase output end output is as the input signal of this zone of departure;

   The signal of second trigger in-phase output end output is as secondary signal, and this trigger receives first signal as input signal;

   First trigger is the rising edge trigger, and second trigger is the trailing edge trigger;

   XOR circuit is carried out XOR to first, second signal, and it is exported as clock signal.
7. 7. clock circuit as claimed in claim 6, wherein when this first Logical processing unit changes the level of this first signal with this each rising edge in this reference clock, if the level of this first signal is one first level before a rising edge takes place, then this first Logical processing unit can make the level of this first signal change into one second level after this rising edge takes place.
8. 8. clock circuit as claimed in claim 7, wherein if the level of this first signal is this second level before this rising edge takes place, this first Logical processing unit can make the level of this first signal change into this first level after this rising edge takes place.
9. 9. clock circuit as claimed in claim 6, wherein when this second Logical processing unit changes the level of this secondary signal with each trailing edge in this reference clock, if the level of this secondary signal is one first level before a trailing edge takes place, then this second Logical processing unit can make the level of this secondary signal change into one second level after this trailing edge takes place.
10. 10. clock circuit as claimed in claim 6, wherein if the level of this secondary signal is this second level before this trailing edge takes place, this second Logical processing unit can make the level of this secondary signal change into this first level after this trailing edge takes place.

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